Philips Semiconductors Product specification 10-bit D-type flip-flop; positive-edge trigger (3-State) 74ABT821 extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-type flip-flops The 74ABT821 is a buffered 10-bit wide version of the 74ABT374/74ABT534 functions. required with MOS microprocessors The 74ABT821 is a 10-bit, edge triggered register coupled to ten 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. and 200 V per Machine Model The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. • Ideal where high speed, light loading, or increased fan-in are • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 • Power-up 3-State • Power-up Reset The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. DESCRIPTION The active Low Output Enable (OE) controls all ten 3-State buffers independent of the register operation. When OE is Low, the data in the register appears at the outputs. When OE is High, the outputs are in high impedance ”off” state, which means they will neither drive nor load the bus. The 74ABT821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT821 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER tPLH tPHL Propagation delay CP to Qn CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC COUT Output capacitance Outputs disabled; VO = 0V or VCC ICCZ Total supply current Outputs disabled; VCC =5.5V TYPICAL UNIT 4.6 ns 4 pF 7 pF 500 nA ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP PACKAGES –40°C to +85°C 74ABT821 N 74ABT821 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT821 D 74ABT821 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT821 DB 74ABT821 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT821 PW 74ABT821PW DH SOT355-1 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 D0-D9 Data inputs 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 Q0-Q9 Data outputs 13 CP Output enable input (active-Low) OE 1 24 VCC D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 D5 7 18 Q5 D6 8 17 Q6 10 GND Ground (0V) D7 9 20 VCC Positive supply voltage TOP VIEW 16 Q7 D8 10 15 Q8 D9 11 14 Q9 GND 12 13 CP Clock pulse input (active rising edge) SA00223 1995 Sep 06 1 853-1616 15703 Philips Semiconductors Product specification 10-bit D-type flip-flop; positive-edge trigger (3-State) LOGIC SYMBOL 74ABT821 LOGIC SYMBOL (IEEE/IEC) 1 EN 13 2 3 4 5 6 7 8 9 C2 10 11 2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 2D 23 1 3 22 13 CP 4 21 1 OE 5 20 6 19 7 18 8 17 9 16 10 15 11 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 23 22 21 20 19 18 17 16 15 14 SA00224 SA00225 FUNCTION TABLE INTERNAL OUTPUTS OE INPUTS CP Dn REGISTER Q0 – Q9 L L ↑ ↑ l h L H L H L ↑ X NC NC H ↑ X NC ↑ H Dn Dn H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition OPERATING MODE Load and read register Hold Z Z Disable outputs NC= X = Z = ↑ = ↑ = No change Don’t care High impedance “off” state Low to High clock transition Not a Low-to-High clock transition LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 D8 D9 10 11 D D D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q 13 CP 1 OE 23 Q0 22 Q1 21 Q2 20 19 Q3 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 SA00226 1995 Sep 06 2 Philips Semiconductors Product specification 10-bit D-type flip-flop; positive-edge trigger (3-State) 74ABT821 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1995 Sep 06 2.0 3 V Philips Semiconductors Product specification 10-bit D-type flip-flop; positive-edge trigger (3-State) 74ABT821 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.9 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V II Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.0V; VO = 0.5V; VI = GND or VCC; V OE = VCC ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA Output current1 VCC = 5.5V; VO = 2.5V –100 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 0.5 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 25 38 38 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.5 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA IOFF IPU/IPD IO ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100µsec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM Min Typ Max Typ UNIT Max fMAX Maximum clock frequency 1 125 185 tPLH tPHL Propagation delay CP to Qn 1 2.1 2.8 4.1 4.6 5.6 6.2 2.1 2.8 6.2 6.7 ns tPZH tPZL Output enable time to High and Low level 3 4 1.0 2.2 3.0 4.1 4.5 5.6 1.0 2.2 5.3 6.3 ns tPHZ tPLZ Output disable time from High and Low level 3 4 2.7 2.8 4.7 4.6 6.2 6.1 2.7 2.8 6.7 6.5 ns 1995 Sep 06 4 125 ns Philips Semiconductors Product specification 10-bit D-type flip-flop; positive-edge trigger (3-State) 74ABT821 AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25oC VCC = +5.0V WAVEFORM Tamb = -40 to +85oC VCC = +5.0V ±0.5V Min Typ Min UNIT ts(H) ts(L) Setup time, High or Low Dn to CP 2 2.1 2.1 0.5 0.3 2.1 2.1 ns th(H) th(L) Hold time, High or Low Dn to CP 2 1.3 1.3 0.0 –0.3 1.3 1.3 ns tw(H) tw(L) CP pulse width High or Low 1 2.9 3.8 1.8 2.8 2.9 3.8 ns AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V Dn 1/fMAX CP VM tW(H) tW(L) VM VM th(H) VM ts(L) th(L) CP VM tPLH VM Qn VM ts(H) VM tPHL ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ VM VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00107 Waveform 2. Data Setup and Hold Times SA00159 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency OE VM VM tPZL OE VM tPLZ VM tPZH Qn tPHZ VM VOL+0.3V 0V Qn VM VOH–0.3V SA00067 0V Waveform 4. 3–State Output Enable Time to Low Level and Output Disable Time from Low Level SA00066 Waveform 3. 3–State Output Enable Time to High Level and Output Disable Time from High Level 1995 Sep 06 5 Philips Semiconductors Product specification 10-bit D-type flip-flop; positive-edge trigger (3-State) 74ABT821 TEST CIRCUIT AND WAVEFORM VCC 7.0V PULSE GENERATOR VIN tW 90% VOUT VM NEGATIVE PULSE CL 10% 0V RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open AMP (V) VM 10% RL D.U.T. RT 90% 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74ABT Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00012 1995 Sep 06 6