BF1214 Dual N-channel dual gate MOSFET Rev. 01 — 30 October 2007 Product data sheet 1. Product profile 1.1 General description The BF1214 is a combination of two dual gate MOSFET amplifiers with shared source and gate2 leads. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT363 micro-miniature plastic package. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features n Two low noise gain controlled amplifiers in a single package; both with a partly integrated bias n Superior cross modulation performance during AGC n High forward transfer admittance n High forward transfer admittance to input capacitance ratio n Both amplifiers optimized for VHF applications, yet suitable for VHF and UHF applications 1.3 Applications n Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage u digital and analog television tuners u professional communication equipment BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 1.4 Quick reference data Table 1. Quick reference data for amplifier A and B Symbol Parameter Conditions Min Typ Max Unit - - 6 V - - 30 mA VDS drain-source voltage DC ID drain current DC Ptot total power dissipation Tsp ≤ 107 °C |yfs| forward transfer admittance f = 100 MHz; Tj = 25 °C; ID = 18 mA Ciss(G1) input capacitance at gate1 f = 100 MHz Crss reverse transfer capacitance f = 100 MHz NF noise figure [1] - - 180 mW 27 32 37 mS [2] - 2.2 2.7 pF [2] - 20 - fF - 0.9 1.5 dB - 1.2 1.8 dB 102 105 - dBµV - - 150 °C f = 400 MHz; YS = YS(opt) f = 800 MHz; YS = YS(opt) Xmod cross modulation Tj junction temperature input level for k = 1 % at 40 dB AGC; fw = 50 MHz; funw = 60 MHz [1] Tsp is the temperature at the soldering point of the source lead. [2] Calculated from S-parameters. [3] Measured in Figure 24 test circuit. [3] 2. Pinning information Table 2. Discrete pinning Pin Description 1 drain (AMP A) 2 source 3 drain (AMP B) 4 gate1 (AMP B) 5 gate2 6 gate1 (AMP A) Simplified outline 6 5 Symbol 4 AMP A DA G1A S G2 1 2 3 DB G1B AMP B sym119 3. Ordering information Table 3. Ordering information Type number BF1214 Package Name Description Version - plastic surface-mounted package; 6 leads SOT363 BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 2 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 4. Marking Table 4. Marking Type number Marking Description BF1214 SB* * = p : made in Hong Kong * = t : made in Malaysia * = w : made in China 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per MOSFET VDS drain-source voltage DC - 6 V ID drain current DC - 30 mA IG1 gate1 current - ±10 mA IG2 gate2 current - ±10 mA Tsp ≤ 107 °C [1] Ptot total power dissipation - 180 mW Tstg storage temperature −65 +150 °C Tj junction temperature - 150 °C [1] Tsp is the temperature at the soldering point of the source lead. 001aac193 250 Ptot (mW) 200 150 100 50 0 0 50 100 150 200 Tsp (˚C) Fig 1. Power derating curve BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 3 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from junction to solder point Typ Unit 240 K/W 7. Static characteristics Table 7. Static characteristics Tj = 25 °C. Symbol Parameter Conditions Min Typ Max Unit amplifier A 6 - - V amplifier B 6 - - V Per MOSFET; unless otherwise specified V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0 V; ID = 10 µA V(BR)G1-SS gate1-source breakdown voltage VG2-S = VDS = 0 V; IG1-S = 10 mA 6 - 10 V V(BR)G2-SS gate2-source breakdown voltage VG1-S = VDS = 0 V; IG2-S = 10 mA 6 - 10 V VF(S-G1) forward source-gate1 voltage VG2-S = VDS = 0 V; IS-G1 = 10 mA 0.5 - 1.5 V VF(S-G2) forward source-gate2 voltage VG1-S = VDS = 0 V; IS-G2 = 10 mA 0.5 - 1.5 V VG1-S(th) gate1-source threshold voltage VDS = 5 V; VG2-S = 4 V; ID = 100 µA 0.3 - 1.0 V VG2-S(th) gate2-source threshold voltage VDS = 5 V; VG1-S = 5 V; ID = 100 µA 0.4 - 1.0 V amplifier A; VDS(A) = 5 V; RG1(A) = 68 kΩ 13 - 23 mA amplifier B; VDS(B) = 5 V; RG1(B) = 68 kΩ 13 - 23 mA amplifier A; VG1-S(A) = 5 V - - 50 nA amplifier B; VG1-S(B) = 5 V - - 50 nA - - 20 nA drain-source current IDS IG1-S IG2-S [1] gate1 cut-off current gate2 cut-off current VG2-S = 4 V [1] VG2-S = 0 V; VDS(A) = VDS(B) = 0 V VG2-S = 4 V; VDS(A) = VDS(B) = 0 V; VG1-S(A) = VG1-S(B) = 0 V RG1 connects gate1 to VGG = 5 V. BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 4 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 8. Dynamic characteristics Table 8. Dynamic characteristics for amplifier A and B Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 18 mA. Symbol Parameter Conditions |yfs| f = 100 MHz; Tj = 25 °C forward transfer admittance Min Typ Max Unit mS 27 32 37 Ciss(G1) input capacitance at gate1 f = 100 MHz [1] - 2.2 2.7 pF Ciss(G2) input capacitance at gate2 f = 100 MHz [1] - 3.5 - pF Coss output capacitance f = 100 MHz [1] - 0.8 - pF reverse transfer capacitance f = 100 MHz [1] - 20 - fF transducer power gain [1] f = 200 MHz; GS = 2 mS; GL = 0.5 mS 31 35 39 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 27 31 35 dB 22 26 30 dB f = 200 MHz; GS = 2 mS; GL = 0.5 mS 31 35 39 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 29 33 37 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 25 29 33 dB Crss Gtr amplifier A; BS = BS(opt); BL = BL(opt) f = 800 MHz; GS = 3.3 mS; GL = 1 mS amplifier B; BS = BS(opt); BL = BL(opt) NF noise figure [1] f = 11 MHz; GS = 20 mS; BS = 0 S - 3.0 - dB f = 400 MHz; YS = YS(opt) - 0.9 1.5 dB - 1.2 1.8 dB at 0 dB AGC 90 - - dBµV at 10 dB AGC - 94 - dBµV at 20 dB AGC - 99 - dBµV at 40 dB AGC 102 105 - dBµV f = 800 MHz; YS = YS(opt) Xmod cross modulation [1] Calculated from S-parameters. [2] Measured in Figure 24 test circuit. input level for k = 1 %; fw = 50 MHz; funw = 60 MHz BF1214_1 Product data sheet [2] © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 5 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 8.1 Graphs for amplifier A and B 001aag993 40 ID (mA) ID (mA) (1) (1) (2) 30 001aag994 40 30 (2) (3) (4) (3) (4) 20 20 (5) (5) (6) (7) (6) 10 10 (8) (9) (7) 0 0 0 0.5 1.0 1.5 2.0 0 2 VG1-S (V) 6 VDS (V) (1) VG2-S = 4.0 V. (1) VG1-S = 1.8 V. (2) VG2-S = 3.5 V. (2) VG1-S = 1.7 V. (3) VG2-S = 3.0 V. (3) VG1-S = 1.6 V. (4) VG2-S = 2.5 V. (4) VG1-S = 1.5 V. (5) VG2-S = 2.0 V. (5) VG1-S = 1.4 V. (6) VG2-S = 1.5 V. (6) VG1-S = 1.3 V. (7) VG2-S = 1.0 V. (7) VG1-S = 1.2 V. VDS = 5 V; Tj = 25 °C. 4 (8) VG1-S = 1.1 V. (9) VG1-S = 1.0 V. VG2-S = 4 V; Tj = 25 °C. Fig 2. Transfer characteristics; typical values Fig 3. Output characteristics; typical values BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 6 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 001aag995 120 IG1 (µA) 001aag996 40 |yfs| (mS) (1) (1) 30 (2) (2) 80 (3) (3) 20 (4) 40 (4) 10 (5) (5) (6) (6) (7) (7) 0 0 0 0.5 1.0 1.5 2.0 0 10 20 30 VG1-S (V) 40 ID (mA) (1) VG2-S = 4.0 V. (1) VG2-S = 4.0 V. (2) VG2-S = 3.5 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3.0 V. (3) VG2-S = 3.0 V. (4) VG2-S = 2.5 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2.0 V. (5) VG2-S = 2.0 V. (6) VG2-S = 1.5 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1.0 V. (7) VG2-S = 1.0 V. VDS = 5 V; Tj = 25 °C. VDS = 5 V; Tj = 25 °C. Fig 4. Gate1 current as a function of gate1 voltage; typical values 001aag997 24 ID (mA) Fig 5. Forward transfer admittance as a function of drain current; typical values 001aag998 20 ID (mA) 18 15 12 10 6 5 0 0 0 20 40 60 0 IG1 (µA) 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. VDS = 5 V; VG2-S = 4 V; RG1 = 68 kΩ; Tj = 25 °C. Fig 6. Drain current as a function of gate1 current; typical values Fig 7. Drain current as a function of gate1 supply voltage (VGG); typical values BF1214_1 Product data sheet 1 © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 7 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 001aag999 25 ID (mA) (1) ID (mA) (2) 20 001aah000 30 (3) (4) (1) 20 (5) (2) 15 (3) (4) (5) 10 10 (6) (7) (8) (9) 5 0 0 0 1 2 3 4 5 VGG = VDS (V) 0 1 (1) RG1 = 47 kΩ. (1) VGG = 5.0 V. (2) RG1 = 56 kΩ. (2) VGG = 4.5 V. (3) RG1 = 68 kΩ. (3) VGG = 4.0 V. (4) RG1 = 82 kΩ. (4) VGG = 3.5 V. (5) RG1 = 100 kΩ. (5) VGG = 3.0 V. 2 3 4 5 VG2-S (V) Tj = 25 °C; RG1 = 68 kΩ (connected to VGG). (6) RG1 = 120 kΩ. (7) RG1 = 150 kΩ. (8) RG1 = 180 kΩ. (9) RG1 = 220 kΩ. VG2-S = 4 V; Tj = 25 °C. Fig 8. Drain current as a function of VDS and VGG; typical values Fig 9. Drain current as a function of gate2 voltage; typical values BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 8 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 8.2 Graphs for amplifier A 001aah001 0 gain reduction (dB) 10 001aah002 110 Vunw (dBµV) 100 20 30 90 40 80 50 0 1 2 3 4 0 10 20 VAGC (V) VDS(A) = 5 V; VGG = 5 V; ID(nom)(A) = 18 mA; RG1(A) = 68 kΩ; fw = 50 MHz; Tamb = 25 °C; see Figure 24. 30 40 50 gain reduction (dB) VDS(A) = 5 V; VGG = 5 V; VG2-S(nom) = 4 V; RG1(A) = 68 kΩ; fw = 50 MHz; funw = 60 MHz; ID(nom)(A) = 18 mA; Tamb = 25 °C; see Figure 24. Fig 10. Amplifier A: typical gain reduction as a function of the AGC voltage; typical values Fig 11. Amplifier A: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values 001aah003 30 ID (mA) 20 10 0 0 10 20 30 40 50 gain reduction (dB) VDS(A) = 5 V; VGG = 5 V; VG2-S(nom) = 4 V; RG1(A) = 68 kΩ; fw = 50 MHz; ID(nom)(A) = 18 mA; Tamb = 25 °C; see Figure 24. Fig 12. Amplifier A: typical drain current as a function of gain reduction; typical values BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 9 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 001aah004 102 001aah005 102 −102 bis, gis (mS) |yfs| (mS) 10 ϕfs (deg) |yfs| bis 1 −10 10 ϕfs gis 10−1 10−2 10 102 1 103 10 −1 103 102 f (MHz) f (MHz) VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 0 V; ID(A) = 18 mA. VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 0 V; ID(A) = 18 mA. Fig 13. Amplifier A: input admittance as a function of frequency; typical values 001aah006 103 −103 ϕrs (deg) |yrs| (µS) ϕrs 102 −102 Fig 14. Amplifier A: forward transfer admittance and phase as a function of frequency; typical values 001aah007 10 bos, gos (mS) 1 bos 10−1 gos |yrs| −10 10 1 10 −1 103 102 10−2 10 102 103 f (MHz) f (MHz) VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 0 V; ID(A) = 18 mA. VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 0 V; ID(A) = 18 mA. Fig 15. Amplifier A: reverse transfer admittance and phase as a function of frequency; typical values Fig 16. Amplifier A: output admittance as a function of frequency; typical values BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 10 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 8.2.1 Scattering parameters for amplifier A Table 9. Scattering parameters for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 18 mA; VDS(B) = 0 V; VG1-S(B) = 0 V; Tamb = 25 °C; typical values. f (MHz) s11 s21 s12 s22 Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) 40 0.9877 −3.07 3.07 176.73 0.0006 88.01 0.9902 −1.00 100 0.9888 −7.81 3.07 171.67 0.0012 85.54 0.9918 −2.74 200 0.9852 −15.61 3.04 163.23 0.0022 80.05 0.9910 −5.50 300 0.9766 −23.41 3.00 154.91 0.0033 75.66 0.9896 −8.22 400 0.9643 −31.14 2.95 146.63 0.0042 71.57 0.9881 −10.93 500 0.9504 −38.62 2.89 138.57 0.0050 67.10 0.9859 −13.61 600 0.9339 −45.96 2.82 130.61 0.0056 63.38 0.9836 −16.28 700 0.9151 −53.13 2.74 122.79 0.0061 59.74 0.9813 −18.96 800 0.8960 −60.18 2.66 115.17 0.0064 56.44 0.9790 −21.60 900 0.8766 −67.00 2.57 107.66 0.0065 53.53 0.9769 −24.20 1000 0.8564 −73.58 2.49 100.35 0.0066 50.29 0.9753 −26.88 8.2.2 Noise data for amplifier A Table 10. Noise data for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 18 mA; Tamb = 25 °C; typical values. f (MHz) NFmin (dB) Γopt rn (ratio) (ratio) (deg) 400 0.91 0.76 23.60 0.677 800 1.23 0.71 48.91 0.620 BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 11 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 8.3 Graphs for amplifier B 001aah008 0 gain reduction (dB) 10 001aah009 110 Vunw (dBmV) 100 20 30 90 40 80 50 0 1 2 3 4 0 10 20 VAGC (V) VDS(B) = 5 V; VGG = 5 V; ID(nom)(B) = 18 mA; RG1(B) = 68 kΩ; fw = 50 MHz; Tamb = 25 °C; see Figure 24. 30 40 50 gain reduction (dB) VDS(B) = 5 V; VGG = 5 V; VG2-S(nom) = 4 V; RG1(B) = 68 kΩ; fw = 50 MHz; funw = 60 MHz; ID(nom)(B) = 18 mA; Tamb = 25 °C; see Figure 24. Fig 17. Amplifier B: typical gain reduction as a function of the AGC voltage; typical values Fig 18. Amplifier B: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values 001aah010 30 ID (mA) 20 10 0 0 10 20 30 40 50 gain reduction (dB) VDS(B) = 5 V; VGG = 5 V; VG2-S(nom) = 4 V; RG1(B) = 68 kΩ; ID(nom)(B) = 18 mA; fw = 50 MHz; Tamb = 25 °C; see Figure 24. Fig 19. Amplifier B: typical drain current as a function of gain reduction; typical values BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 12 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 001aah011 102 001aah012 102 −102 bis, gis (mS) ϕfs (deg) |yfs| |yfs| (mS) 10 bis 1 −10 10 ϕfs gis 10−1 10−2 10 102 1 103 10 −1 103 102 f (MHz) f (MHz) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = 0 V; ID(B) = 18 mA. VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = 0 V; ID(B) = 18 mA. Fig 20. Amplifier B: input admittance as a function of frequency; typical values 001aah013 103 −103 ϕrs (deg) |yrs| (µS) ϕrs 102 −102 Fig 21. Amplifier B: forward transfer admittance and phase as a function of frequency; typical values 001aah014 10 bos, gos (mS) 1 bos 10−1 gos |yrs| −10 10 1 10 −1 103 102 10−2 10 102 103 f (MHz) f (MHz) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = 0 V; ID(B) = 18 mA. VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = 0 V; ID(B) = 18 mA. Fig 22. Amplifier B: reverse transfer admittance and phase as a function of frequency; typical values Fig 23. Amplifier B: output admittance as a function of frequency; typical values BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 13 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 8.3.1 Scattering parameters for amplifier B Table 11. Scattering parameters for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 18 mA; VDS(A) = 0 V; VG1-S(A) = 0 V; Tamb = 25 °C; typical values. f (MHz) s11 s21 s12 s22 Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) 40 0.9836 −2.92 3.06 176.89 0.0005 89.71 0.9897 −0.98 100 0.9890 −7.68 3.06 171.63 0.0012 92.19 0.9920 −2.79 200 0.9869 −15.32 3.03 163.14 0.0023 88.94 0.9914 −5.62 300 0.9801 −23.00 2.99 154.74 0.0034 87.64 0.9902 −8.42 400 0.9704 −30.69 2.94 146.34 0.0045 86.52 0.9889 −11.21 500 0.9595 −38.13 2.88 138.13 0.0056 85.29 0.9869 −14.01 600 0.9458 −45.45 2.81 129.99 0.0066 84.60 0.9845 −16.81 700 0.9300 −52.67 2.73 121.93 0.0075 83.78 0.9818 −19.64 800 0.9132 −59.82 2.65 114.01 0.0085 82.86 0.9786 −22.44 900 0.8959 −66.74 2.56 106.18 0.0093 81.97 0.9750 −25.22 1000 0.8775 −73.43 2.47 98.51 0.0101 80.62 0.9717 −28.10 8.3.2 Noise data for amplifier B Table 12. Noise data for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 18 mA; Tamb = 25 °C; typical values. f (MHz) Γopt NFmin (dB) rn (ratio) (ratio) (deg) 400 0.91 0.76 22.58 0.690 800 1.24 0.71 47.34 0.620 9. Test information VAGC R1 10 kΩ C1 C3 4.7 nF 4.7 nF C2 RGEN 50 Ω VI 4.7 nF R2 50 Ω DUT L1 ≈ 2.2 µH RL 50 Ω C4 RG1 VGG 4.7 nF VDS 001aad926 Fig 24. Cross modulation test setup (for one MOSFET) BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 14 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 10. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 c bp Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 25. Package outline SOT363 BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 15 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 11. Abbreviations Table 13. Abbreviations Acronym Description AGC Automatic Gain Control DC Direct Current MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor UHF Ultra High Frequency VHF Very High Frequency 12. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes BF1214_1 20071030 Product data sheet - - BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 16 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] BF1214_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 30 October 2007 17 of 18 BF1214 NXP Semiconductors Dual N-channel dual gate MOSFET 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.2.1 8.2.2 8.3 8.3.1 8.3.2 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Graphs for amplifier A and B . . . . . . . . . . . . . . 6 Graphs for amplifier A . . . . . . . . . . . . . . . . . . . . 9 Scattering parameters for amplifier A . . . . . . . 11 Noise data for amplifier A . . . . . . . . . . . . . . . . 11 Graphs for amplifier B . . . . . . . . . . . . . . . . . . . 12 Scattering parameters for amplifier B . . . . . . . 14 Noise data for amplifier B . . . . . . . . . . . . . . . . 14 Test information . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 October 2007 Document identifier: BF1214_1