Philips Semiconductors Advanced BiCMOS Products Product specification Octal latched transceiver with dual enable, inverting (3-State) FEATURES • Combines 74ABT245 and 74ABT373 type functions in one device • 8-bit octal transceiver with D-type latch • Back-to-back registers for storage • Separate controls for data flow in each direction • Output capability: +64mA/–32mA • Live insertion/extraction permitted • Power-up 3-State • Power-up reset • Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 74ABT544 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model DESCRIPTION The 74ABT544 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT544 Octal Registered Transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64mA. FUNCTIONAL DESCRIPTION The ’ABT544 contains two sets of eight D–type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (EAB) input and the A-to-B Latch Enable (LEAB) input are Low the A-to-B path is transparent. A subsequent Low-to-High transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both Low, the 3-State B output buffers are active and invert the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 24-pin plastic DIP –40°C to +85°C 74ABT544N 0410D 24-pin plastic SOL –40°C to +85°C 74ABT544D 0173D 24-pin plastic SSOP Type II –40°C to +85°C 74ABT544DB 1641A PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 2 23 LEBA 1 24 VCC OEBA 2 23 EBA A0 3 22 B0 A1 4 21 B1 5 20 B2 A2 6 19 B3 A4 7 18 B4 A5 8 17 B5 9 16 B6 A3 A6 A7 10 13 3 4 5 6 7 8 9 10 11 14 A0 A1 A2 A3 A4 A5 A6 A7 3 G1 1C5 2EN4 (BA) G2 2C6 ∇ 3 22 5D 11 EAB 23 EBA OEAB 13 14 LEAB OEBA 2 5 20 1 LEBA 6 19 B0 B1 B2 B3 B4 B5 B6 B7 7 18 8 17 9 16 10 15 4 5D ∇ 4 21 15 B7 EAB 11 14 LEAB GND 12 13 OEAB June 1, 1993 1 1EN3 (AB) 22 21 20 19 18 17 16 15 1 853–1610 09907 Philips Semiconductors Advanced BiCMOS Products Product specification Octal latched transceiver with dual enable, inverting (3-State) 74ABT544 PIN DESCRIPTION PIN NUMBER SYMBOL 14, 1 LEAB / LEBA FUNCTION A to B / B to A Latch Enable input (active-Low) 11, 23 EAB / EBA 13, 2 OEAB / OEBA A to B / B to A Enable input (active-Low) 3, 4, 5, 6, 7, 8, 9, 10 A0 – A7 Port A, 3-State outputs 22, 21, 20, 19, 18, 17, 16, 15 B0 – B7 Port B, 3-State outputs 12 GND Ground (0V) 24 VCC Positive supply voltage A to B / B to A Output Enable input (active-Low) QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 3.9 ns tPLH tPHL Propagation delay An to Bn or Bn to An CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF CI/O I/O capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 110 µA June 1, 1993 2 Philips Semiconductors Advanced BiCMOS Products Product specification Octal latched transceiver with dual enable, inverting (3-State) 74ABT544 LOGIC DIAGRAM DETAIL A D 22 Q B0 LE A0 3 Q D LE A1 A2 A3 A4 A5 A6 A7 OEBA 4 21 5 20 6 19 7 DETAIL A X 7 18 8 17 9 16 10 15 LEBA 11 1 FUNCTION TABLE INPUTS OUTPUTS STATUS OEXX EXX LEXX An or Bn An or Bn H X X X Z Disabled X H X X Z Disabled L L ↑ ↑ L L h l Z Z Disabled + Latch L L L L ↑ ↑ h l L H Latch + Display L L L L L L H L L H Transparent L L H X NC Hold High voltage level High voltage level one set-up time prior to the Low-to-High clock transition Low voltage level Low voltage level one set-up time prior to the Low-to-High clock transition Don’t care Low-to-High clock transition No change High impedance or “off” state June 1, 1993 B3 B4 B5 B6 B7 OEAB 23 14 H = h = L = l = X = ↑ = NC= Z = B2 2 13 EBA B1 3 EAB LEAB Philips Semiconductors Advanced BiCMOS Products Product specification Octal latched transceiver with dual enable, inverting (3-State) 74ABT544 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range June 1, 1993 2.0 4 V Philips Semiconductors Advanced BiCMOS Products Product specification Octal latched transceiver with dual enable, inverting (3-State) 74ABT544 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.9 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 3.2 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.7 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.3 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA II Power-off leakage current VCC = 0.0V; VI or VO ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = Don’t care ±5.0 ±50 ±50 µA IIH + IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA Output current1 VCC = 5.5V; VO = 2.5V –65 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 110 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 20 30 30 mA VCC = 5.5V; Outputs 3–State; VI = GND or VCC 110 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND; VCC = 5.5V 0.3 1.5 1.5 mA IOFF IPU/PD IO ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip–flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition of 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a transition time of up to 100µsec is permitted. June 1, 1993 5 Philips Semiconductors Advanced BiCMOS Products Product specification Octal latched transceiver with dual enable, inverting (3-State) 74ABT544 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM UNIT Min Typ Max Min Max 2 1.1 1.4 3.6 3.9 5.1 5.4 1.1 1.4 6.1 6.4 ns tPLH tPHL Propagation delay An to Bn, Bn to An tPLH tPHL Propagation delay LEBA to An, LEAB to Bn 1, 2 1.6 2.1 4.1 4.6 5.6 6.1 1.6 2.1 6.6 7.1 ns tPZH tPZL Output enable time OEBA to An, OEAB to Bn 4 5 1.4 2.5 3.9 5.0 5.4 6.5 1.4 2.5 6.4 7.5 ns tPHZ tPLZ Output disable time OEBA to An, OEAB to Bn 4 5 2.5 1.0 5.9 5.5 7.4 7.0 3.4 3.0 8.4 8.0 ns tPZH tPZL Output enable time EBA to An, EAB to Bn 4 5 1.4 2.5 3.9 5.0 5.4 6.5 1.4 2.5 6.4 7.5 ns tPHZ tPLZ Output disable time EBA to An, EAB to Bn 4 5 2.5 1.0 5.9 5.5 7.4 7.0 3.4 3.0 8.4 8.0 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER +25oC Tamb = VCC = +5.0V WAVEFORM Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT Min Typ Min 3 3.0 3.0 1.5 0.6 3.0 3.0 ns Hold time An to LEAB, Bn to LEBA 3 0.5 0.5 –0.3 –1.3 0.5 0.5 ns ts(H) ts(L) Setup time An to EAB, Bn to EBA 3 3.0 3.0 1.5 0.6 3.0 3.0 ns th(H) th(L) Hold time An to EAB, Bn to EBA 3 0.5 0.5 –0.2 –1.3 0.5 0.5 ns tw(L) Latch enable pulse width, Low 3 3.5 1.8 3.5 ns ts(H) ts(L) Setup time An to LEAB, Bn to LEBA th(H) th(L) June 1, 1993 6 Philips Semiconductors Advanced BiCMOS Products Product specification Octal latched transceiver with dual enable, inverting (3-State) 74ABT544 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V VIN VM VIN VM tPHL VM tPLH VOUT VM tPLH tPHL VOUT VM ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ VM VM ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Waveform 1. Propagation Delay For Inverting Output An, Bn VM Waveform 2. Propagation Delay For Non–Inverting Output VM VM ts(H) VM th(H) VM ts(L) th(L) LEAB, LEBA VM tw(L) VM Waveform 3. Data Setup and Hold Times And Latch Enable Pulse Width OEAB, OEBA, EAB, EBA VM OEAB, OEBA, EAB, EBA VM tPZH tPHZ An, Bn VM VM VM tPZL tPLZ An, Bn VOH –0.3V VM 0V Waveform 4. 3–State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3–State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. June 1, 1993 VOL +0.3V 0V 7 Philips Semiconductors Advanced BiCMOS Products Product specification Octal latched transceiver with dual enable, inverting (3-State) 74ABT544 TEST CIRCUIT AND WAVEFORM VCC 7.0V VOUT VIN PULSE GENERATOR tW 90% VM NEGATIVE PULSE 10% 0V tTHL (tF) CL tTLH (tR) tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. 74ABT RT = Termination resistance should be equal to ZOUT of pulse generators. June 1, 1993 AMP (V) VM 10% RL D.U.T RT 90% 8 Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns