74LVTH32245 3.3 V 32-bit bus transceiver; 3-state Rev. 01 — 23 January 2008 Product data sheet 1. General description The 74LVTH32245 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. The 74LVTH32245 is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features four output enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction control. Pin nOE controls the outputs so that the buses are effectively isolated. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features n n n n n n n n n n 32-bit bidirectional bus interface 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection: u JESD78 Class II level A exceeds 500 mA n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package 74LVTH32245EC −40 °C to +85 °C Temperature range Name Description LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 × 5.5 × 1.05 mm Version SOT536-1 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state 4. Functional diagram A3 1DIR H3 1OE A5 A6 E5 4B5 T6 4B6 T5 3B7 R1 4A6 M2 3A7 R2 4A5 L1 3A6 3B6 M6 4B4 R6 P1 4A4 L2 3A5 3B5 M5 4B3 R5 P2 4A3 K1 3A4 3B4 L6 4B2 P6 N1 4A2 K2 3A3 3B3 L5 4B1 P5 N2 4A1 J1 3A2 3B2 K6 4B0 N6 T4 4A0 J2 3A1 3B1 K5 4OE N5 H2 4DIR J4 3A0 3B0 J6 2B7 T3 H1 2A7 D1 3DIR 3OE J5 2B6 H5 G1 2A6 D2 1A7 1B7 J3 2B5 H6 G2 2A5 C1 1A6 1B6 D6 2B4 G6 F1 2A4 C2 1A5 1B5 D5 2B3 G5 F2 2A3 B1 1A4 1B4 C6 2B2 F6 E1 2A2 B2 1A3 1B3 C5 2B1 F5 E2 2A1 A1 1A2 1B2 B6 2B0 E6 H4 2A0 A2 1A1 1B1 B5 2OE A4 1A0 1B0 2DIR T1 4A7 M1 4B7 T2 mna476 Fig 1. Logic symbol 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 2 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state VCC VCC output data input to internal circuit mna473 001aah682 Fig 2. Schematic of each output Fig 3. Bus hold circuit 5. Pinning information 5.1 Pinning mna475 6 1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A6 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A6 5 1A0 1A2 1A4 1A6 2A0 2A2 2A4 2A7 3A0 3A2 3A4 3A6 4A0 4A2 4A4 4A7 4 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 3 1DIR GND VCC GND GND VCC GND 2DIR 3DIR GND VCC GND GND VCC GND 4DIR 2 1B0 1B2 1B4 1B6 2B0 2B2 2B4 2B7 3B0 3B2 3B4 3B6 4B0 4B2 4B4 4B7 1 1B1 1B3 1B5 1B7 2B1 2B3 2B5 2B6 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B6 A B C D E F G H J K L M N P R T Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Ball Description nDIR (n = 1 to 4) A3, H3, J3, T3 direction control nOE (n = 1 to 4) A4, H4, J4, T4 output enable input (active LOW) 1A[0:7] A5, A6, B5, B6, C5, C6, D5, D6 input or output 1B[0:7] A2, A1, B2, B1, C2, C1, D2, D1 input or output 2A[0:7] E5, E6, F5, F6, G5, G6, H6, H5 input or output 2B[0:7] E2, E1, F2, F1, G2, G1, H1, H2 input or output 3A[0:7] J5, J6, K5, K6, L5, L6, M5, M6 input or output 3B[0:7] J2, J1, K2, K1, L2, L1, M2, M1 input or output 4A[0:7] N5, N6, P5, P6, R5, R6, T6, T5 input or output 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 3 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state Table 2. Pin description …continued Symbol Ball Description 4B[0:7] N2, N1, P2, P1, R2, R1, T1, T2 input or output GND B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, ground (0 V) M3, M4, N3, N4, R3, R4 VCC C3, C4, F3, F4, L3, L4, P3, P4 supply voltage 6. Functional description Table 3. Function selection[1] Input Input/output nOE nDIR nAn nBn L L nAn = nBn inputs L H inputs nBn = nAn H X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)[1][2] Symbol Parameter Conditions supply voltage VCC Min Max Unit −0.5 +4.6 V −0.5 +7.0 V input voltage [3] VO output voltage output in OFF or HIGH-state [3] −0.5 +7.0 V IIK input clamping current VI < 0 V −50 - mA IOK output clamping current VO < 0 V −50 - mA IO output current output in LOW-state - 128 mA output in HIGH-state −64 - mA Tstg storage temperature −65 +150 °C Tj junction temperature - 150 °C VI [1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond indicated under Section 8 “Recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 4 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 2.7 - 3.6 V VI input voltage 0 - 5.5 V IOH HIGH-level output current IOL LOW-level output current −32 - - mA none - - 32 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 64 mA Tamb ambient temperature in free air −40 - +85 °C ∆t/∆V input transition rise and fall rate outputs enabled - - 10 ns/V - - 1000 mW [1] total power dissipation Ptot Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. [1] 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 Conditions Min Typ Max Unit VCC = 2.7 V; IIK = −18 mA −1.2 −0.85 - V °C[1] VIK input clamping voltage VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V VOH HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH = −100 µA VCC − 0.2 VCC - V VCC = 2.7 V; IOH = −8 mA 2.4 2.5 - V VCC = 3.0 V; IOH = −32 mA 2.0 2.3 - V VCC = 2.7 V; IOL = 100 µA - 0.07 0.2 V VOL II LOW-level output voltage input leakage current VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 16 mA - 0.25 0.4 V VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 64 mA - 0.4 0.55 V - 0.1 ±1 µA - 0.1 10 µA control pins VCC = 3.6 V; VI = VCC or GND VCC = 0 V or 3.6 V; VI = 5.5 V input/output data pins; VCC = 3.6 V VI = 5.5 V - 0.1 20 µA VI = VCC - 0.5 10 µA VI = 0 V −5 −0.1 - µA - 0.1 ±100 µA IOFF power-off leakage current ILO output leakage current output HIGH; VO = 5.5 V; VCC = 3.0 V IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care VCC = 0 V; VI or VO = 0 V to 4.5 V 74LVTH32245_1 Product data sheet [2] [4] - 75 125 µA - 40 ±100 µA © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 5 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IBHL bus hold LOW current VCC = 3 V; VI = 0.8 V 75 135 - µA IBHH bus hold HIGH current VCC = 3 V; VI = 2.0 V IBHLO bus hold LOW overdrive current VCC = 0 V to 3.6 V; VI = 3.6 V [3] IBHHO bus hold HIGH overdrive current VCC = 0 V to 3.6 V; VI = 3.6 V [3] ICC supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled - −135 −75 µA 500 - - µA - - −500 µA - 0.14 0.24 mA - 8.4 12 mA [5] - 0.14 0.24 mA [6] - 0.1 0.2 mA ∆ICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC − 0.6 V; other inputs at VCC or GND CI input capacitance control pins; VO = 0 V or 3.0 V - 3 - pF CI/O input/output capacitance input/output data pins; outputs disabled; VCC = 3.6 V; IO = 0 A; VI = GND or VCC - 9 - pF [1] All typical values are at VCC = 3.3 V and Tamb = 25 °C unless otherwise specified. [2] Unused pins at VCC or GND. [3] This is the bus-hold overdrive current required to force the input to the opposite logic state. [4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. [5] ICC is measured with outputs pulled to VCC or GND. [6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 7. Symbol Parameter Min Typ[1] Max Unit VCC = 2.7 V - - 3.5 ns VCC = 3.0 V to 3.6 V 1.0 1.9 3.3 ns VCC = 2.7 V - - 3.5 ns VCC = 3.0 V to 3.6 V 1.0 1.7 3.3 ns VCC = 2.7 V - - 5.3 ns VCC = 3.0 V to 3.6 V 1.0 2.8 4.5 ns Conditions Tamb = −40 °C to +85 °C tPLH tPHL tPZH LOW to HIGH propagation delay HIGH to LOW propagation delay OFF-state to HIGH propagation delay nAn to nBn or nBn to nAn; see Figure 5 nAn to nBn or nBn to nAn; see Figure 5 nOE to nAn or nBn; see Figure 6 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 6 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 7. Min Typ[1] Max Unit VCC = 2.7 V - - 5.1 ns VCC = 3.0 V to 3.6 V 1.0 2.8 4.1 ns VCC = 2.7 V - - 5.7 ns VCC = 3.0 V to 3.6 V 1.5 3.2 5.1 ns VCC = 2.7 V - - 4.6 ns VCC = 3.0 V to 3.6 V 1.5 3.0 4.6 ns Symbol Parameter Conditions tPZL OFF-state to LOW propagation delay nOE to nAn or nBn; see Figure 6 HIGH to OFF-state propagation delay nOE to nAn or nBn; see Figure 6 tPHZ LOW to OFF-state propagation delay tPLZ [1] nOE to nAn or nBn; see Figure 6 All typical values are at VCC = 3.3 V and Tamb = 25 °C. 11. Waveforms VI nAn, nBn input VM GND t PHL t PLH VOH nBn, nAn output VM VOL mna477 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Input to output propagation delays 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 7 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state VI VM nOE input GND tPLZ tPZL 3.0 V output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aah683 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY 2.7 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 8 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Load circuitry for switching times Table 9. Test data Input VEXT Load VI fi tW tr, tf RL CL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 500 Ω 50 pF GND 6V open 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 9 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 A B D ball A1 index area A A2 E A1 detail X e1 C 1/2 e ∅v M C A B e T R P N M L K J H G F E D C B A ball A1 index area y1 C y ∅w M C b e e2 1/2 e 1 2 3 4 5 6 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1.5 0.41 0.31 1.2 0.9 0.51 0.41 5.6 5.4 13.6 13.4 0.8 4 12 0.15 0.1 0.1 0.2 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-02-05 SOT536-1 Fig 8. Package outline SOT536-1 (LFBGA96) 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 10 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVTH32245_1 20080123 Product data sheet - - 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 11 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVTH32245_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 January 2008 12 of 13 74LVTH32245 NXP Semiconductors 3.3 V 32-bit bus transceiver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 23 January 2008 Document identifier: 74LVTH32245_1