PHILIPS TDA9331H

INTEGRATED CIRCUITS
DATA SHEET
TDA933xH series
I2C-bus controlled TV display
processors
Preliminary specification
Supersedes data of 1998 Oct 22
File under Integrated Circuits, IC02
2000 May 08
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
FEATURES
Available in all ICs:
• Can be used in both single scan (50 or 60 Hz) and
double scan (100 or 120 Hz) applications
• YUV input and linear RGB input with fast blanking
• Separate OSD/text input with fast blanking or blending
• Black stretching of non-standard luminance signals
GENERAL DESCRIPTION
• Switchable matrix for the colour difference signals
The TDA933xH series are display processors for
‘High-end’ television receivers which contain the following
functions:
• RGB control circuit with Continuous Cathode Calibration
(CCC), plus white point and black level offset
adjustment
• RGB control processor with Y, U and V inputs, a linear
RGB input for SCART or VGA signals with fast blanking,
a linear RGB input for OSD and text signals with a fast
blanking or blending option and an RGB output stage
with black current stabilization, which is realized with the
CCC (2-point black current measurement) system.
• Blue stretch circuit which offsets colours near white
towards blue
• Internal clock generation for the deflection processing,
which is synchronized by a 12 MHz ceramic resonator
oscillator
• Programmable deflection processor with internal clock
generation, which generates the drive signals for the
horizontal, East-West (E-W) and vertical deflection.
The circuit has various features that are attractive for the
application of 16 : 9 picture tubes.
• Horizontal synchronization with two control loops and
alignment-free horizontal oscillator
• Slow start and slow stop of the horizontal drive pulses
• Low-power start-up option for the horizontal drive circuit
• The circuit can be used in both single scan (50 or 60 Hz)
and double scan (100 or 120 Hz) applications.
• Vertical count-down circuit
• Vertical driver optimized for DC-coupled vertical output
stages
In addition to these functions, the TDA9331H and
TDA9332H have a multi-sync function for the horizontal
PLL, with a frequency range from 30 to 50 kHz (2fH mode)
or 15 to 25 kHz (1fH mode), so that the ICs can also be
used to display SVGA signals.
• Vertical and horizontal geometry processing
• Horizontal and vertical zoom possibility and vertical
scroll function for application with 16 : 9 picture tubes
• Horizontal parallelogram and bow correction
The supply voltage of the ICs is 8 V. They are each
contained in a 44-pin QFP package.
• I2C-bus control of various functions
• Low dissipation.
ORDERING INFORMATION
TYPE
NUMBER
TDA9330H
TDA9331H
PACKAGE
NAME
QFP44
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
TDA9332H
2000 May 08
2
VERSION
SOT307-2
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
SURVEY OF IC TYPES
IC VERSION
VGA MODE
DAC OUTPUT
TDA9330H
no
I2C-bus
TDA9331H
yes
proportional to VGA frequency
TDA9332H
yes
I2C-bus controlled
controlled
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Supply
VP
supply voltage
−
8.0
−
V
IP
supply current (VP1 plus VP2)
−
50
−
mA
Vi(Y)(b-w)
luminance input signal (black-to-white value)
−
1.0/0.315
−
V
Vi(U)(p-p)
U input signal (peak-to-peak value)
−
1.33
−
V
Vi(V)(p-p)
V input signal (peak-to-peak value)
−
1.05
−
V
Vi(RGB)(b-w)
RGB input signal (black-to-white value)
−
0.7
−
V
Vi(Hsync)
horizontal sync input (HD)
−
TTL
−
V
Vi(Vsync)
vertical sync input (VD)
−
TTL
−
V
Vi(IIC)
I2C-bus
−
CMOS 5 V −
V
2.0
−
V
Input voltages
inputs (SDA and SCL)
Output signals
Vo(RGB)(b-w)
RGB output signal amplitude (black-to-white value)
−
Io(hor)
horizontal output current
−
−
10
mA
Io(ver)(p-p)
vertical output current (peak-to-peak value)
−
0.95
−
mA
Io(EW)
E-W drive output current
−
−
1.2
mA
2000 May 08
3
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
33
YIN
UIN
VIN
28
Y
27
U
SWITCH
V
26
Y
RI1
GI1
BI1
VP2
35
U
R
SATURATION
CONTROL
COLOUR
DIFFERENCE
MATRIX
G
B
37
38
R
CONTRAST
CONTROL
G
B
R
RGB
INSERTION
32
RGB-YUV
MATRIX
G
B
WHITE POINT
AND
BRIGHTNESS
CONTROL
BLACK
STRETCH
R
G
B
OUTPUT
AMPLIFIER
AND
BUFFER
BLUE STRETCH
40
CONTINUOUS
CATHODE
CALIBRATION
44
41
42
PWL
AND
BEAM
CURRENT
LIMITER
TDA933xH
4
39
43
VP1 17
DECVD 7
25
DECBG 18
GND1
6
GND2 19
VD
HD
HSEL
10
SOFT
START/STOP
LOW-POWER
START-UP
SUPPLY
H-SHIFT
H/V DIVIDER
19 × 6-BIT DACs
2 × 4-BIT DACs
23
24
12
RO
GO
BO
white
BRI point
30
31
29
34
CONTR
SAT
V
36
I2C-BUS
TRANSCEIVER
11
BLKIN
BCL
DACOUT
Philips Semiconductors
FBCSO
PWL
I2C-bus controlled TV display processors
RI2 GI2 BI2 BL2
BLOCK DIAGRAM
handbook, full pagewidth
2000 May 08
BL1
SCL
SDA
GEOMETRY CONTROL
CLOCK
GENERATION
AND
1st LOOP
PHASE-2
LOOP
9
SCO HFB
13
14
DPC
5
FLASH
8
22
15
16
VSC
Iref
HOUT LPSU
Fig.1 Block diagram.
E-W
GEOMETRY
VERTICAL
GEOMETRY
1
VDOA
2
VDOB
4
EHTIN
3
EWO
MGR445
Preliminary specification
21
XTALO
RAMP
GENERATOR
TDA933xH series
20
XTALI
HORIZONTAL
OUTPUT
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
PINNING
SYMBOL
PIN
DESCRIPTION
VDOA
1
vertical drive output A
VDOB
2
vertical drive output B
EWO
3
E-W output
EHTIN
4
EHT compensation input
FLASH
5
flash detection input
GND1
6
ground 1
DECVD
7
digital supply decoupling
HOUT
8
horizontal output
SCO
9
sandcastle pulse output
SCL
10
serial clock input
SDA
11
serial data input/output
HSEL
12
selection of horizontal frequency
HFB
13
horizontal flyback pulse input
DPC
14
dynamic phase compensation
VSC
15
vertical sawtooth capacitor
Iref
16
reference current input
VP1
17
positive supply 1 (+8 V)
DECBG
18
band gap decoupling
GND2
19
ground 2
XTALI
20
crystal input
XTALO
21
crystal output
LPSU
22
low-power start-up supply
VD
23
vertical sync input
HD
24
horizontal sync input
DACOUT
25
DAC output
VIN
26
V-signal input
UIN
27
U-signal input
YIN
28
luminance input
FBCSO
29
fixed beam current switch-off input
RI1
30
red 1 input for insertion
GI1
31
green 1 input for insertion
BI1
32
blue 1 input for insertion
BL1
33
fast blanking input for RGB-1
PWL
34
peak white limiting decoupling
RI2
35
red 2 input for insertion
GI2
36
green 2 input for insertion
BI2
37
blue 2 input for insertion
BL2
38
fast blanking/blending input for RGB-2
VP2
39
positive supply 2 (+8 V)
RO
40
red output
2000 May 08
5
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
black current input
handbook, full pagewidth
VDOA 1
33 BL1
VDOB 2
32 BI1
EWO 3
31 GI1
EHTIN 4
30 RI1
FLASH 5
29 FBCSO
GND1 6
28 YIN
TDA933xH
DECVD 7
27 UIN
HOUT 8
26 VIN
6
LPSU 22
XTALI 20
XTALO 21
GND2 19
VP1 17
Iref 16
23 VD
VSC 15
SDA 11
DPC 14
24 HD
HFB 13
25 DACOUT
SCL 10
HSEL 12
SCO 9
Fig.2 Pin configuration.
2000 May 08
34 PWL
44
35 RI2
BLKIN
36 GI2
beam current limiting input
37 BI2
blue output
43
40 RO
42
BCL
41 GO
BO
42 BO
green output
43 BCL
41
44 BLKIN
GO
38 BL2
DESCRIPTION
39 VP2
PIN
DECBG 18
SYMBOL
TDA933xH series
MGR446
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
This 2-point stabilization is based on the principle that the
ratio between the cathode currents is coupled to the ratio
FUNCTIONAL DESCRIPTION
RGB control circuit
V dr1 γ
I k1
between the drive voltages according to: ------ =  -----------
V
I k2
dr1
INPUT SIGNALS
The RGB control circuit of the TDA933xH contains three
sets of input signals:
The feedback loop makes the ratio between cathode
currents Ik1 and Ik2 equal to the ratio between the
reference currents (which are internally fixed) by changing
the (black) level and the amplitude of the RGB output
signals via two converging loops. The system operates in
such a way that the black level of the drive signal is
controlled to the cut-off point of the gun. In this way, a very
good grey scale tracking is obtained. The accuracy of the
adjustment of the black level is only dependent on the ratio
of internal currents and these can be made very accurately
in integrated circuits. An additional advantage of the
2-point measurement is that the control system makes the
absolute value of Ik1 and Ik2 identical to the internal
reference currents. Because this adjustment is obtained
by adapting the gain of the RGB control stage, this control
stabilizes the gain of the complete channel (RGB output
stage and cathode characteristic). As a result, this 2-point
loop compensates for variations in the gain figures during
life.
• YUV input signals, which are supplied by the input
processor or the feature box. Bit GAI can be used to
switch the luminance input signal sensitivity between
0.45 V (p-p) and 1.0 V (b-w). The nominal input signals
for U and V are 1.33 V (p-p) and 1.05 V (p-p),
respectively. These input signals are controlled on
contrast, saturation and brightness.
• The first RGB input is intended for external signals
(SCART in 1fH and VGA in 2fH applications), which have
an amplitude of 0.7 V (p-p) typical. This input is also
controlled on contrast, saturation and brightness.
• The second RGB input is intended for OSD and teletext
signals. The required input signals have an amplitude of
0.7 V (p-p). The switching between the internal signal
and the OSD signal can be realized via a blending
function or via fast blanking. This input is only controlled
on brightness.
An important property of the 2-point stabilization is that the
offset and the gain of the RGB path are adjusted by the
feedback loop. Hence, the maximum drive voltage for the
cathode is fixed by the relationship between the test
pulses, the reference current and the relative gain setting
of the three channels. Consequently, the drive level of the
CRT cannot be adjusted by adapting the gain of the RGB
output stage. Because different picture tubes may require
different drive levels, the typical ‘cathode drive level’
amplitude can be adjusted by means of an I2C-bus setting.
Depending on the selected cathode drive level, the typical
gain of the RGB output stages can be fixed, taking into
account the drive capability of the RGB outputs
(pins 40 to 42). More details about the design are given in
the application report (see also Chapter “Characteristics”;
note 11).
Switching between the various sources can be realized via
the I2C-bus and by fast insertion switches. The fast
insertion switches can be enabled via the I2C-bus.
The circuit contains switchable matrix circuits for the
colour difference signals so that the colour reproduction
can be adapted for PAL/SECAM and NTSC. For NTSC,
two different matrices can be chosen. In addition, a matrix
for high-definition ATSC signals is available.
OUTPUT AMPLIFIER
The output signal has an amplitude of approximately
2 V (b-w) at nominal input signals and nominal settings of
the controls. The required ‘white point setting’ of the
picture tube can be realized by means of three separate
gain settings for the RGB channels.
The measurement of the high and the low currents of the
2-point stabilization circuit is performed in two consecutive
fields. The leakage current is measured in each field. The
maximum allowable leakage current is 100 µA.
To obtain an accurate biasing of the picture tube, a CCC
circuit has been developed. This function is realized by a
2-point black level stabilization circuit.
By inserting two test levels for each gun and comparing the
resulting cathode currents with two different reference
currents, the influence of the picture tube parameters such
as the spread in cut-off voltage can be eliminated.
2000 May 08
TDA933xH series
For extra flexibility, it also possible to switch the CCC
circuit to 1-point stabilization with the OPC bit. In this
mode, only the black level at the RGB outputs is controlled
by the loop. The cathode drive level setting has no
influence on the gain in this mode. This level should be set
to the nominal value to get the correct amplitude of the
measuring pulses.
7
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
Via the I2C-bus, an adjustable offset can be made on the
black level of red and green channels with respect to the
level that is generated by the black current control loop.
These controls can be used to adjust the colour
temperature of the dark part of the picture, independent of
the white point adjustment.
Synchronization and deflection processing
HORIZONTAL SYNCHRONIZATION AND DRIVE CIRCUIT
The horizontal drive signal is obtained from an internal
VCO which runs at a frequency of 440 times (2fH mode) or
880 times (1fH mode) the frequency of the incoming HD
signal. The free-running frequency of this VCO is
calibrated by a crystal oscillator which needs an external
12 MHz crystal or ceramic resonator as a reference. It is
also possible to supply an external reference signal to the
IC (in this case, the external resonator should be
removed).
When the TV receiver is switched on, the black current
stabilization circuit is directly activated and the RGB
outputs are blanked. The blanking is switched off as soon
as the loop has stabilized (e.g. the first time that bit BCF
changes from 1 to 0, see also Chapter “Characteristics”;
note 15). This ensures that the switch-on time is reduced
to a minimum and is only dependent on the warm-up time
of the picture tube.
The VCO is synchronized to the incoming horizontal HD
pulse (applied from the feature box or the input processor)
by a PLL with an internal time constant. The frequency of
the horizontal drive signal (1fH or 2fH) is selected by means
of a switching pin, which must be connected to ground or
left open circuit.
The black current stabilization system checks the output
level of the three channels and indicates whether the black
level of the lowest RGB output of the IC is in a certain
window (WBC bit), below or above this window (HBC bit).
This indication can be read from the I2C-bus and can be
used for automatic adjustment of voltage Vg2 during the
production of the TV receiver.
For HDTV applications, it is possible to change the
free-running frequency of the horizontal drive output from
31.2 kHz to 33.7 kHz by means of bit HDTV.
When a failure occurs in the black current loop (e.g. due to
an open circuit), status bit BCF is set. This information can
be used to blank the picture tube to avoid damage to the
screen.
For safety reasons, switching between 1fH and 2fH
modes is only possible when the IC is in the standby
mode.
For the TDA9331H and TDA9332H, it is also possible to
set the horizontal PLL to a ‘multi-sync’ mode by means of
bit VGA. In this mode, the circuit detects the frequency of
the incoming sync pulses and adjusts the centre frequency
of the VCO accordingly by means of an internal
Digital-to-Analog-Converter (DAC). The frequency range
in this mode is 30 to 50 kHz at the output.
The control circuit contains an average beam current
limiting circuit and a peak white level (PWL) circuit. The
PWL detects small white areas in the picture that are not
detected by the average beam current limiter. The PWL
can be adjusted via the I2C-bus. A low-pass filter is placed
in front of the peak detector to prevent it from reacting to
short transients in the video signal. The capacitor of the
low-pass filter is connected externally so that the set
maker can adapt the time constant as required. The IC
also contains a soft clipper that limits the amplitude of the
short transients in the RGB output signals. In this way, spot
blooming on, for instance, subtitles is prevented. The
difference between the PWL and the soft clipping level can
be adjusted via the I2C-bus in a few steps.
The polarities of the incoming HD and VD pulses are
detected internally. The detected polarity can be read out
via status bits HPOL and VPOL.
The horizontal drive signal is generated by a second
control loop which compares the phase of the reference
signal (applied from the internal VCO) with the flyback
pulse. The time constant of this loop is set internally. The
IC has a dynamic horizontal phase correction input, which
can be used to compensate phase shifts that are caused
by beam current variations. Additional settings of the
horizontal deflection (which are realized via the second
loop) are the horizontal shift and horizontal parallelogram
and bow corrections (see Chapter “Characteristics”;
Fig.16). The adjustments are realized via the I2C-bus.
The vertical blanking is adapted to the vertical frequency
of the incoming signal (50 or 100 Hz or, 60 or 120 Hz).
When the flyback time of the vertical output stage is
greater than the 60 Hz blanking time, the blanking can be
increased to the same value as that of the 50 Hz blanking.
This can be set by means of bit LBM.
When no video is available, it is possible to insert a blue
background. This feature can be activated via bit EBB.
2000 May 08
TDA933xH series
When no horizontal flyback pulse is detected during three
consecutive line periods, status bit NHF is set (output
status byte 01-D3; see Table 3).
8
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
The horizontal drive signal is switched on and off via the
so-called slow-start/slow-stop procedure. This function is
realized by varying the ton of the horizontal drive pulse. For
EHT generators without a bleeder, the IC can be set to a
‘fixed beam current mode’ via bit FBC. In this case, the
picture tube capacitance is discharged with a current of
approximately 1 mA. The magnitude of the discharge
current is controlled via the black current feedback loop.
If necessary, the discharge current can be enlarged with
the aid of an external current division circuit. With the fixed
beam current option activated, it is still possible to have a
black screen during switch-off. This can be realized by
placing the vertical deflection in an overscan position. This
mode is activated via bit OSO.
and independent of the incoming vertical frequency. In this
mode, the E-W drive amplitude is proportional to the
horizontal frequency so that the correction on the screen is
not affected.
The vertical drive is realized by a differential output
current. The outputs must be DC-coupled to the vertical
output stage (e.g. TDA8354).
The vertical geometry can be adjusted via the I2C-bus.
Controls are possible for the following parameters:
• Vertical amplitude
• S-correction
• Vertical slope
• Vertical shift (only for compensation of offsets in output
stage or picture tube)
An additional mode of the IC is the ‘low-power start-up’
mode. This mode is activated when a supply voltage of 5 V
is supplied to the start-up pin.
• Vertical zoom
• Vertical scroll (shifting the picture in the vertical direction
when the vertical scan is expanded)
The required current for this mode is 3 mA (typ.). In this
condition, the horizontal drive signal has the nominal toff
and the ton grows gradually from zero to approximately
30% of the nominal value. This results in a line frequency
of approximately 50 kHz (2fH) or 25 kHz (1fH). The output
signal remains unchanged until the main supply voltage is
switched on and the I2C-bus data has been received. The
horizontal drive then gradually changes to the nominal
frequency and duty cycle via the slow-start procedure.
• Vertical wait, an adjustable delay for the start of the
vertical scan.
With regard to the vertical wait, the following conditions are
valid:
• In the 1fH TV mode, the start of the vertical scan is fixed
and cannot be adjusted with the vertical wait
• In the 2fH TV mode, the start of the vertical scan
depends on the value of the Vertical Scan Reference
(VSR) bus bit. If VSR = 0, the start of the vertical scan is
related to the end of the incoming VD pulse. If VSR = 1,
it is related to the start. In both cases, the start of the
scan can be adjusted with the vertical wait setting
The IC can only be switched on and to standby mode when
both standby bits (STB0 and STB1) are changed. The
circuit will not react when only one bit changes polarity.
The IC has a general purpose bus controlled DAC output
with a 6-bit resolution and with an output voltage range
between 0.2 to 4 V. In the TDA9331H, the DC voltage on
this output is proportional to the horizontal line frequency
(only in VGA mode). This voltage can be used to control
the supply voltage of the horizontal deflection stage, to
maintain constant picture width for higher line frequencies.
• In the multi-sync mode (TDA9331H and TDA9332H
both in 1fH mode and 2fH mode), the start of the vertical
scan is related to the start of the incoming VD pulse and
can be adjusted with the vertical wait setting.
The minimum value for the vertical wait setting is 8 line
periods. If the setting is lower than 8, the wait period will
remain at 8 line periods.
VERTICAL DEFLECTION AND GEOMETRY CONTROL
The drive signals for the vertical and E-W deflection
circuits are generated by a vertical divider, which derives
its clock signal from the line oscillator. The divider is
synchronized by the incoming VD pulse, generated by the
input processor or the feature box. The vertical ramp
generator requires an external resistor and capacitor; the
tolerances for these components must be small. In the
normal mode, the vertical deflection operates in constant
slope and adapts its amplitude, depending on the
frequency of the incoming signal (50 or 60 Hz, or
100 or 120 Hz). When the TDA933xH is switched to the
VGA mode, the amplitude of the vertical scan is stabilized
2000 May 08
TDA933xH series
The E-W drive circuit has a single-ended output. The E-W
geometry can be adjusted on the following parameters:
• Horizontal width with increased range because of the
‘zoom’ feature
• E-W parabola/width ratio
• E-W upper corner/parabola ratio
• E-W lower corner/parabola ratio
• E-W trapezium.
9
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
The IC has an EHT compensation input which controls
both the vertical and the E-W output signals. The relative
control effect on both outputs can be adjusted via the
I2C-bus (sensitivity of vertical correction is fixed; E-W
correction variable).
I2C-BUS SPECIFICATION
The slave address of the IC is given in Table 1. The circuit
operates up to clock frequencies of 400 kHz. Valid
subaddresses: 00 to 1F, subaddress FE is reserved for
test purposes. The auto-increment mode is available for
subaddresses.
To avoid damage to the picture tube in the event of missing
or malfunctioning vertical deflection, a vertical guard
function is available at the sandcastle pin (pin SCO). The
vertical guard pulse from the vertical output stage
(TDA835x) should be connected to the sandcastle pin,
which acts as a current sense input. If the guard pulse is
missing or lasts too long, bit NDF is set in the status
register and the RGB outputs are blanked. If the guard
function is disabled via bit EVG, only NDF status bit NHF
is set.
Table 1
The IC also has inputs for flash and overvoltage protection.
More details about these functions are given in Chapter
“Characteristics”; note 43.
2000 May 08
TDA933xH series
10
Slave address (8C)
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
1
1
0
1/0
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
Table 2
TDA933xH series
Input control bits
FUNCTION
SUBADDRESS
(HEX)
RGB processing-1
RGB processing-2
Wide horizontal blanking
Horizontal deflection
Vertical deflection
Brightness
Saturation
Contrast
White point R
White point G
White point B
Peak white limiting
Horizontal shift
Horizontal parallelogram(1)
E-W width
E-W parabola/width
E-W upper corner/parabola
E-W trapezium
E-W EHT compensation sensitivity
Vertical slope
Vertical amplitude
S-correction
Vertical shift
Vertical zoom
Vertical scroll
Vertical wait
DAC output(2)
Black level offset R
Black level offset G
Horizontal timing
E-W lower corner/parabola
Horizontal bow(1)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
DATA BYTE
D7
D6
MAT
EBB
MUS FBC
HBL TFBC
HDTV VSR
OPC VFF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D5
SBL
OBL
GAI
0
LBM
A5
A5
A5
A5
A5
A5
SC1
A5
0
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
0
A5
0
0
0
A5
0
Notes
1. For zero parallelogram and bow correction use register value 7 DEC.
2. See Chapter “Characteristics”; note 47.
3. Bit VGA is not available in the TDA9330H.
2000 May 08
11
D4
D3
RBL
BLS
AKB
CL3
STB0 HB3
STB1 POC
DIP
OSO
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
SC0
A3
A4
A3
0
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
0
A3
0
A3
HDCL LBL3
A4
A3
0
A3
D2
D1
D0
BKS
IE1
IE2
CL2
CL1
CL0
HB2
HB1
HB0
PRD VGA(3) ESS
SVF
EVG
DL
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
LBL2 LBL1 LBL0
A2
A1
A0
A2
A1
A0
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
Table 3
Output status bits
FUNCTION
DATA BYTE
SUBADDRESS
(HEX)
D7
D6
Output status bytes
MAT
D1
D0
FSI
SL
XPR
NDF
IN1
IN2
WBC
ID2
ID1
ID0
NHF
BCF
FLS
NRF
02
X
X
X
X
X
HPOL
VPOL
HBC
Table 10 Enable fast blanking RGB-1
Colour difference matrix
MUS
IE1
FAST BLANKING
MATRIX POSITION
0
not active
PAL
1
active
1
ATSC
1
0
NTSC Japan
1
1
NTSC USA
Table 11 Enable fast blanking RGB-2
Enable ‘blue-back’
EBB
MODE
0
blue-black switched off
1
blue-black switched on
SERVICE BLANKING MODE
0
off
1
on
RGB BLANKING
0
not active
1
active
FAST BLANKING
0
not active
1
active
FBC
MODE
0
switch-off with blanked RGB outputs
1
switch-off with fixed beam current
Table 13 Blending function on OSD; note 1
OBL
RGB blanking
RBL
IE2
Table 12 Fixed beam current switch-off
Service blanking
SBL
Table 8
D2
N2
0
Table 7
D3
POR
0
Table 6
D4
00
0
Table 5
D5
01
Input control bits
Table 4
TDA933xH series
MODE
0
OSD via fast blanking
1
OSD via blending function
Note
1. When bit OBL is set to 1, the blending function is
always activated, independent of the setting of bit IE2.
Table 14 Black current stabilization
Blue stretch
BLS
BLUE STRETCH MODE
AKB
OPC
MODE
0
off
0
0
2-point control
on
0
1
1-point control
1
−
not active
1
Table 9
Black stretch
BKS
BLACK STRETCH MODE
0
off
1
on
2000 May 08
12
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
Table 15 Cathode drive level (15 steps; 3.6 V/step)
CL3
CL2
CL1
CL0
Table 20 Position of wide blanking (14 steps; 1fH mode
0.29 µs/step; 2fH mode 0.145 µs/step)
SETTING OF CATHODE
DRIVE AMPLITUDE(1)
0
0
0
0
41 V (b-w)
1
0
0
0
70 V (b-w)
1
1
1
1
95 V (b-w)
TDA933xH series
TIMING OF BLANKING(1)
HB3
Note
1. The given values are valid for the following conditions:
HB2
HB1 HB0
1fH MODE
2fH MODE
0
0
0
0
−2.03 µs
−1.015 µs
0
1
1
1
0 µs
0 µs
1
1
1
−
2.03 µs
1.015 µs
Note
a) Nominal CVBS input signal.
1. See Chapter “Characteristics”; note 13.
b) Settings for contrast and white point nominal.
Table 21 Horizontal free-running frequency in TV mode
c) Black and blue stretch switched off.
d) Gain of output stage such that no clipping occurs.
FREQUENCY
HDTV
e) Beam current limiting not active.
f) Gamma of picture tube is 2.25.
g) The tolerance on these values is approximately
±3 V.
1fH MODE
2fH MODE
0
15.65 kHz
31.3 kHz
1
16.85 kHz
33.7 kHz
Table 22 Vertical scan reference in 2fH TV mode
Table 16 RGB blanking mode
HBL
MODE
0
normal blanking (horizontal flyback)
1
wide blanking
MODE
0
18.6 ms
1
25 ms
VERTICAL SCAN REFERENCE
0
end of VD pulse
1
start of VD pulse
Table 23 Synchronization mode
Table 17 Picture tube discharge time
TFBC
VSR
POC
MODE
0
synchronization active
1
synchronization not active
Table 24 Overvoltage input mode
Note
1. See Chapter “Characteristics”; Fig.15
PRD
Table 18 Gain of luminance channel
GAI
OVERVOLTAGE MODE
0
detection mode
1
protection mode
MODE
0
normal gain [V28 = 1 V (b-w)]
1
high gain [V28 = 0.45 V (p-p)]
Table 25 Multi-sync mode
Table 19 Standby
VGA
MODE
0
horizontal frequency fixed by internal
reference
1
multi-sync function switched on
STB0
STB1
CONDITION
0
0
horizontal drive off
0
1
no action
1
0
no action
ESS
EXTENDED SLOW START MODE
1
1
horizontal drive on
0
not active
1
active
2000 May 08
Table 26 Extended slow start mode
13
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
Table 27 Long blanking mode
LBM
TDA933xH series
Table 34 Soft clipping level
BLANKING MODE
0
adapted to standard (50 or 60 Hz)
1
fixed in accordance with 50 Hz standard
Table 28 Vertical free-running frequency in TV mode
VFF
FREQUENCY
0
50 Hz (SVF = 0) or 100 Hz (SVF = 1)
1
60 Hz (SVF = 0) or 120 Hz (SVF = 1)
PHASE
0
delay of 1st field (start of synchronized VD
pulse coincides with H-flyback) with 0.5 H
1
delay of 2nd field with 0.5 H
MODE
0
switch-off undefined
1
switch-off in vertical overscan
MODE
0
vertical frequency is 50 or 60 Hz
1
vertical frequency is 100 or 120 Hz
0
0
0% above PWL
0
1
5% above PWL
1
0
10% above PWL
1
1
soft clipping off
HDCL
MODE(1)
0
normal timing
1
HDTV timing
1. See Chapter “Characteristics”; note 13.
Table 36 Start line blanking (15 steps; 2 line locked clock
period per step; 1 line period is 440 LLC pulses)
Table 31 Select vertical frequency
SVF
VOLTAGE DIFFERENCE
BETWEEN SOFT CLIPPING AND
PWL
Note
Table 30 Switch-off in vertical overscan
OSO
SC0
Table 35 Clamp pulse timing
Table 29 De-interlace phase
DIP
SC1
LBL3
LBL2
LBL1
LBL0
START LINE
BLANKING(1)
0
0
0
0
+14 LLC
0
1
1
1
normal
1
1
1
1
−16 LLC
Note
1. See Chapter “Characteristics”; note 13.
Output status bits
Table 32 Enable vertical guard (RGB blanking)
Table 37 Power-on reset
EVG
VERTICAL GUARD MODE
0
not active
POR
1
active
0
normal
1
power-down
Table 33 Interlace
MODE
Table 38 Field frequency indication
DL
STATUS
0
interlace
FSI
FREQUENCY
1
de-interlace
0
50 or 100 Hz
1
60 or 120 Hz
Table 39 Phase 1 (ϕ1) lock indication
2000 May 08
14
SL
INDICATION
0
not locked
1
locked
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
Table 40 X-ray protection
TDA933xH series
Table 47 Condition of horizontal flyback
XPR
OVERVOLTAGE
NHF
CONDITION
0
no overvoltage detected
0
flyback pulse present
1
overvoltage detected
1
flyback pulse not present
Table 48 Indication of failure in black current circuit
Table 41 Output of vertical guard
NDF
VERTICAL OUTPUT STAGE
BCF
CONDITION
0
OK
0
normal operation
1
failure
1
failure in black current stabilization circuit
Table 49 Indication of flash detection
Table 42 Indication of RGB-1 insertion
IN1
RGB INSERTION
FLS
CONDITION
0
no
0
no flash-over detected
1
yes
1
flash-over detected
Table 50 Locking of reference oscillator to crystal
oscillator
Table 43 Indication of RGB-2 insertion
IN2
RGB INSERTION
0
no
NRF
CONDITION
1
yes
0
reference oscillator is locked
1
reference oscillator is not locked
Table 44 Indication of output black level inside/outside
Vg2 alignment window
Table 51 Indication of output black level below or above
the middle of Vg2 alignment window
WBC
CONDITION(1)
0
black current stabilization outside window
HBC
CONDITION(1)
1
black current stabilization inside window
0
black current stabilization below window
1
black current stabilization above window
Note
Note
1. See Chapter “Characteristics”; note 16.
1. See Chapter “Characteristics”; note 16.
Table 45 IC identification
Table 52 Polarity of HD input pulse
ID2
ID1
ID0
IC VERSION
0
0
0
TDA9330H
HPOL
POLARITY
0
0
1
TDA9332H
0
positive
0
1
1
TDA9331H
1
negative
Table 53 Polarity of VD input pulse
Table 46 Mask version indication
N2
MASK VERSION
VPOL
POLARITY
0
N1 version
0
positive
1
N2 version
1
negative
2000 May 08
15
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VP
supply voltage
−
9.0
V
Tstg
storage temperature
−25
+150
°C
Tamb
ambient temperature
Tsol
soldering temperature
Tj
junction temperature
for 5 s
0
70
°C
−
260
°C
−
150
°C
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient in free air
VALUE
UNIT
60
K/W
QUALITY SPECIFICATION
Latch-up performance
In accordance with “SNW-FQ-611E-part E”.
At an ambient temperature of 50 °C all pins meet the
following specification:
ESD protection
• Positive stress test: Itrigger ≥ 100 mA
or Vpin ≥ 1.5 × VCC(max)
All pins are protected against ESD by internal protection
diodes, and meet the following specification:
• Negative stress test: Itrigger ≤ −100 mA
or Vpin ≤ −0.5 × VCC(max).
• Human body model (R = 1.5 kΩ; C = 100 pF):
all pins > ±3000 V
At an ambient temperature of 70 °C, all pins meet the
specification as mentioned above, with the exception of
pin 32, which can withstand a negative stress current of at
least 50 mA.
• Machine model (R = 0 Ω; C = 200 pF):
all pins > ±300 V.
2000 May 08
16
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
CHARACTERISTICS
VP = 8 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
MAIN SUPPLY; PINS 17 AND 39
VP1
supply voltage
7.2
8.0
8.8
V
VPOR
power-on reset voltage level
note 1
5.8
6.1
6.5
V
IP1
supply current
pin 17 plus pin 39
44
50
58
mA
pin 17
−
22
−
mA
pin 39
−
28
−
mA
−
400
−
mW
4.5
5.0
5.5
V
−
3.0
4.5
mA
−
1.0
1.5
V
Ptot
total power dissipation
LOW-POWER START-UP; PIN 22
VP2
supply voltage
IP2
supply current
note 2
RGB control circuit
LUMINANCE INPUT; PIN 28
Vi(Y)(b-w)
luminance input voltage
(black-to-white value)
GAI = 0
Zi
input impedance
10
−
−
MΩ
Ci
input capacitance
−
−
5
pF
Ii(Y)(clamp)
input current during clamping
−25
0
+25
µA
U/V INPUTS; PINS 27 AND 26
Vi(U)(p-p)
U input signal amplitude
(peak-to-peak value)
−
1.33
2.0
V
Vi(V)(p-p)
V input signal amplitude
(peak-to-peak value)
−
1.05
1.6
V
Zi
input impedance
10
−
−
MΩ
Ci
input capacitance
−
−
5
pF
Ii(UV)(clamp)
input current during clamping
−20
0
+25
µA
RGB-1 INPUT (SCART/VGA); PINS 30 TO 32; note 3
Vi(b-w)
input signal amplitude
(black-to-white value)
−
0.7
1.0
V
∆Vo
difference between black level of
YUV and RGB-1 signals at the
outputs
−
−
10
mV
Zi
input impedance
10
−
−
MΩ
Ci
input capacitance
−
−
5
pF
Ii(clamp)
input current during clamping
−25
0
+25
µA
∆td
delay difference for the three
channels
−
0
−
ns
2000 May 08
note 5
17
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
PARAMETER
CONDITIONS
TDA933xH series
MIN.
TYP.
MAX.
UNIT
FAST BLANKING INPUT (RGB-1); PIN 33
Vi(BL1)
input voltage
no data insertion
0
−
0.45
V
data insertion
0.9
−
3.0
V
∆td
delay difference between insertion data insertion; note 5
to RGB out and RGB in to RGB out
−
10
20
ns
Ii(BL1)
input current
source current; note 6
−
−0.12
−0.2
mA
SSint
suppression of internal RGB
signals
insertion; fi = 0 to 10 MHz;
notes 5 and 7
50
55
−
dB
SSext
suppression of external RGB
signals
no insertion;
fi = 0 to 10 MHz;
notes 5 and 7
50
55
−
dB
RGB-2 INPUT (OSD/TEXT); PINS 35 TO 37
Vi(b-w)
input signal amplitude
(black-to-white value)
−
0.7
1.0
V
∆Vo
difference between black level of
YUV/RGB-1 and RGB-2 signals at
the outputs
−
−
tbf
mV
Zi
input impedance
10
−
−
MΩ
Ci
input capacitance
−
−
5
pF
Ii(clamp)
input current during clamping
∆td
delay difference for the three
channels
−40
0
+40
µA
−
0
−
ns
no data insertion
0
−
0.05
V
50% insertion
0.69
0.725
0.76
V
100% insertion
1.42
1.47
3.0
V
active blending range
0.31
−
1.14
V
note 5
BLENDING (FAST BLANKING) INPUT (RGB-2); PIN 38; note 8
Blending function (OBL = 1)
Vi(BL2)(1)
Ins(osd)
Vi(max)
input voltage
percentage of data insertion
slope of blending curve
Vi = 0.31 V
0
1
4
%
Vi = 0.725 V
45
50
55
%
Vi = 1.14 V
96
99
100
%
internal signal is 50%
48
50
52
%
50% insertion
−
160
−
%/V
no data insertion
0
−
0.3
V
data insertion
0.9
−
3.0
V
Fast blanking function (OBL = 0)
Vi(BL2)(0)
2000 May 08
input voltage
18
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
PARAMETER
CONDITIONS
TDA933xH series
MIN.
TYP.
MAX.
UNIT
General
∆td
delay difference between insertion data insertion; note 5
to RGB out and RGB in to RGB out
−
20
26
ns
Ii(BL2)
input current
source current; note 6
−
−1
−5
µA
SSint
suppression of internal RGB
signals
insertion; fi = 0 to 10 MHz;
notes 5 and 7
50
55
−
dB
SSext
suppression of external RGB
signals
no insertion;
fi = 0 to 10 MHz;
notes 5 and 7
50
55
−
dB
COLOUR DIFFERENCE MATRICES; note 3
PAL/SECAM mode; the matrix results in the following signal
G−Y
G−Y
− 0.51 (R − Y) − 0.19 (B − Y)
ATSC mode; the matrix results in the following signal; note 4
G−Y
G−Y
− 0.30 (R − Y) − 0.10 (B − Y)
NTSC mode; the matrix results in the following modified colour difference signals
MUS bit = 0 (Japan)
R−Y
(R − Y)*
1.39 (R − Y) − 0.07 (B − Y)
G−Y
(G − Y)*
− 0.46 (R − Y) − 0.15 (B − Y)
B−Y
(B − Y)*
B−Y
MUS bit = 1 (USA)
R−Y
(R − Y)*
1.32 (R − Y) − 0.12 (B − Y)
G−Y
(G − Y)*
− 0.42 (R − Y) − 0.25 (B − Y)
B−Y
(B − Y)*
− 0.03 (R − Y) +1.08 (B − Y)
CONTROLS
Saturation control; note 9
−
300
−
20 DEC
−
I2C-bus setting 0
−
−50
−
dB
63 steps; see Fig.6
−
18
−
dB
−
−
0.5
dB
−
±1.1
−
V
CRsat
saturation control range
small signal gain; 63 steps; 0
see Fig.5
CRsat(nom)
I2C-bus setting for nominal
saturation
YUV input signal
CRsat(min)
minimum saturation
%
Contrast control; note 9
CRcontr
contrast control range
tracking between the three
channels over a control range of
10 dB
Brightness control; note 9
CRbri
2000 May 08
brightness control range
63 steps; see Fig.7
19
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
PARAMETER
CONDITIONS
TDA933xH series
MIN.
TYP.
MAX.
UNIT
BLACK LEVEL STRETCHER; note 10
∆Vbl(max)
maximum black level shift
A-to-A; see Fig.8
15
21
27
IRE
∆Vbl
black level shift
at 100% peak white
−1
0
+1
IRE
at 50% peak white
−1
−
+3
IRE
at 15% peak white
6
8
10
IRE
at nominal luminance input
signal and nominal
contrast, cathode drive
level and white-point
adjustment; note 11
−
2.0
−
V
1
−
VCC − 2
V
note 12
−
120
150
Ω
RGB AMPLIFIER OUTPUTS: PINS 40 TO 42
V40-42(b-w)
output signal amplitude
(black-to-white value)
Vo
output voltage range
Zo
output impedance
Isink
sink current
emitter follower output
−
2
−
mA
Vo(RED)(p-p)
output signal amplitude for the ‘red’
channel (peak-to-peak value)
at nominal settings for
contrast and saturation
control and no luminance
signal at the input (R−Y,
PAL); note 11
−
2.1
−
V
Vbl(nom)
nominal black level voltage
−
2.5
−
V
Vbl
black level voltage
when black level
stabilization is switched off
(via AKB bit)
−
2.5
−
V
tW(blank)
width of video blanking pulse with
bit HBL active
at 1fH; note 13
14.4
14.7
15.0
µs
at 2fH; note 13
7.2
7.35
7.5
µs
CRbl
control range of the black current
stabilization
notes 15 and 16
−
±1
−
V
Vblank
blanking voltage level
−0.4
−0.5
−0.6
V
Vblank(leak)
blanking voltage level during
leakage measurement
difference with black level;
note 11
−
−0.1
−
V
Vblank(l)
blanking voltage level during low
measuring pulse
−
0.25
−
V
Vblank(h)
blanking voltage level during high
measuring pulse
−
0.38
−
V
∆V(RGB)(mp)
adjustment range of the ratio
between the amplitudes of the
RGB drive voltage and the
measuring pulses
note 11
−
±6
−
dB
Vbl(WBC)
black level at the output at which
bit WBC is set to 1
nominal value
2.4
2.5
2.6
V
window; note 16
−
±100
−
mV
∆bl/∆T
variation of black level with
temperature
note 5
−
1.0
−
mV/K
CRbl
black level offset adjustment range
on red and green channels
15 steps; 10 mV/step
± 70
± 75
± 80
mV
2000 May 08
20
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
∆Vbl
PARAMETER
relative variation in black level
between the three channels during
variations of
CONDITIONS
MIN.
TYP.
MAX.
UNIT
note 5
supply voltage (±10%)
nominal controls
−
−
20
mV
saturation (50 dB)
nominal contrast
−
−
20
mV
contrast (20 dB)
nominal saturation
−
−
20
mV
brightness (±0.5 V)
nominal controls
−
−
20
mV
−
−
20
mV
60
−
−
dB
RGB-1 input; at −3 dB
22
25
−
MHz
RGB-2 input; at −3 dB
29
33
−
MHz
luminance input; at −3 dB 23
26
−
MHz
temperature (range 40 °C)
S/N
signal-to-noise ratio of the output
signals
notes 5 and 17
Bo(Y)(10pF)
luminance bandwidth of output
signals
with 10pF load
capacitance; note 12
Bo(Y)(25pF)
TDA933xH series
luminance bandwidth of output
signals
with 25pF load capacitance
RGB-1 input; at −3 dB
20
23
−
MHz
RGB-2 input; at −3 dB
23
26
−
MHz
luminance input; at −3 dB 21
24
−
MHz
WHITE-POINT ADJUSTMENT
I2Cnom
I2C-bus setting for nominal gain
−
32 DEC
−
∆GRGB
adjustment range of RGB drive
levels
CL control bits; see
Table 15
±3.2
±3.6
±4.0
dB
∆Gv
gain control range to compensate
spreads in picture tube
characteristics
white point controls
−
±3
−
dB
−
µA
2-POINT BLACK CURRENT STABILIZATION; INPUT PIN 44; note 18
Iref(l)
amplitude of low reference current
−
8
Iref(h)
amplitude of high reference current
−
20
−
µA
IL
acceptable leakage current
−
±100
−
µA
VIref
voltage on measurement pin
pin 44; loop closed
3.15
3.3
3.45
V
Iscan(max)
maximum current during scan
pin 44; loop open circuit
note 18
−
−
−
2000 May 08
21
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
PARAMETER
CONDITIONS
TDA933xH series
MIN.
TYP.
MAX.
UNIT
BEAM CURRENT LIMITING; INPUT PIN 43
Vbias
internal bias voltage
3.5
3.6
3.7
V
VCR
contrast reduction starting voltage
3.1
3.3
3.5
V
Vdif(CR)
voltage difference for full contrast
reduction
2.0
2.2
2.4
V
Vbri
brightness reduction starting
voltage
1.6
1.8
2.0
V
Vdif(BR)
voltage difference for full brightness
reduction
−
1
−
V
Ich(int)
internal charge current
1.5
2.0
2.5
µA
Idch(max)
maximum discharge current when
the PWL is active
3.5
4.0
4.5
mA
PEAK WHITE LIMITER; note 19
Ich(PWL)
charge current PWL filter pin
pin 34; 1fV mode
13
16
19
µA
pin 34; 2fV mode
26
32
38
µA
52
64
76
µA
Idch(PWL)
discharge current PWL filter pin
pin 34; 1fV mode
pin 34; 2fV mode
100
120
140
µA
Vi(Y)(b-w)
Y-input signal amplitude at which
peak white limiter is activated
(black-to-white value)
PWL range, 15 steps; at
maximum contrast
0.65
−
1.0
V
Vo(RGB)(b-w)
RGB output signal amplitude at
PWL range, 15 steps;
which peak white limiter is activated nominal setting of white
(black-to-white value)
point controls; note 20
2.2
−
3.4
V
SOFT CLIPPER; note 21
∆Gv(sc)
soft clipper gain reduction
at maximum contrast;
see Fig.9
−
15
−
dB
Vo(clip-pwl)
output level compared to PWL for
100 IRE peak signal
(A+B)/A; see Fig.9
−
118
−
%
BLUE STRETCH;
note 22
∆GRG
decrease of small signal gain for
red and green channels
−
17
−
%
1
1.5
2
V
−
−
5.5
V
1.0
1.15
mA
FIXED BEAM CURRENT SWITCH-OFF; notes 23, 24 and 25
VFBCSO
detection level
Vi(FBCSO)(max) maximum input voltage
Idch
discharge current when the fixed
beam current function is activated
sink current pin 44; note 26 0.85
Vo(max)
maximum output voltage at the
RGB outputs
2-point stabilization;
note 26
−
6.0
−
V
1-point stabilization;
note 26
−
5.6
−
V
−
18.6
−
ms
−
25
−
ms
tdch
2000 May 08
discharge time of picture tube when TFBC = 0; see Fig.15
switching to standby
TFBC = 1; see Fig.15
22
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
PARAMETER
TDA933xH series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Horizontal synchronization and deflection
HD INPUT SIGNAL; PIN 24
−
−
0.8
V
2.0
−
5.5
V
−10
−
+10
µA
−
−
100
ns
fall time
−
−
100
ns
pulse width
200 ns −
VIL
LOW-level of input voltage
note 27
VIH
HIGH-level of input voltage
note 27
Ii(HD)
input current
tr(HD)
rise time
tf(HD)
tW(HD)
1/4 line
INTERNAL REFERENCE SIGNAL; CRYSTAL OR RESONATOR CONNECTED TO PINS 20 AND 21; note 28
−
12
−
MHz
−
−
30
Ω
stabilized input signal
(peak-to-peak value)
0.5
0.8
1.0
V
gm(max)
maximum transconductance
4
5
−
mA/V
Zi
input impedance
50
−
−
kΩ
Ci
input capacitance
−
−
10
pF
Co
output capacitance
−
−
5
pF
−
12
−
MHz
AC coupled
0.8
−
2
V
1fH mode; note 30
−
15.65
−
kHz
2fH mode; note 30
−
31.3
−
kHz
2fH mode; HDTV = 1;
note 30
−
33.7
−
kHz
fxtal
resonator frequency
Rs(xtal)
resonator series resistance
Vi(stab)(p-p)
CL = 60 pF
EXTERNAL REFERENCE SIGNAL; INPUT PIN 20
fXTALI
input signal frequency
Vi(XTALI)(p-p)
input signal amplitude
(peak-to-peak value)
FIRST CONTROL LOOP; note 29
fo(nom)
free-running frequency
∆fnom
tolerance on free-running
frequency
note 30
−
−
±1
%
fh/cr
holding/catching range of PLL
1fH mode
±0.75
±0.8
±0.85
kHz
2fH mode
±1.5
±1.6
±1.7
kHz
maximum line time difference per
line
1fH mode
−2
−
+2
µs
2fH mode
−1
−
+1
µs
fcontr
frequency control range in
multi-sync mode
1fH mode
15
−
25
kHz
∆fcorr
maximum speed of frequency
correction in multi-sync mode
VHSEL
voltage on pin HSEL
∆tline
2000 May 08
30
−
50
kHz
−
−
100
kHz/s
1fH mode
0
−
1
V
2fH mode; pin must be left
open circuit
4
5
5.5
V
2fH mode
23
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
PARAMETER
CONDITIONS
TDA933xH series
MIN.
TYP.
MAX.
UNIT
SECOND CONTROL LOOP; PIN 14
∆ϕi/∆ϕo
control sensitivity (loop gain)
∆ti/∆t0
500
−
−
kcor
correction factor k
note 31
−
0.5
−
tcontr
control range from start of
horizontal output to mid flyback
1fH mode; note 32
0
−
23.6
µs
2fH mode; note 32
0
−
11.8
µs
tH(shift)
horizontal shift range
1fH mode; 63 steps
−
±4.5
−
µs
2fH mode; 63 steps
−
±2.25
−
µs
control sensitivity for dynamic
phase compensation
1fH mode
−
0.4
−
µs/V
2fH mode
−
0.2
−
µs/V
Vi(DP)(comp)
input voltage range for dynamic
phase compensation
pin 14; note 33
1.5
4
6.5
V
Zi
input impedance
pin 14; note 33
tpar(cor)(max)
maximum range of parallelogram
correction
1fH mode; end of field;
flyback width 11 µs;
note 34
±0.48
±0.54
±0.60
µs
2fH mode; end of field;
flyback width 5.5 µs;
note 34
±0.24
±0.27
±0.30
µs
1fH mode; end of field;
flyback width 11 µs;
note 34
±0.48
±0.54
±0.60
µs
2fH mode; end of field;
flyback width 5.5 µs;
note 34
±0.24
±0.27
±0.30
µs
∆ϕ
tbow(cor)(max)
maximum range of bow correction
100
µs/µs
kΩ
HORIZONTAL FLYBACK INPUT; PIN 13
Vsw(HBLNK)
switching level for horizontal
blanking
0.2
0.3
0.4
V
Vsw(p2)
switching level for phase detection
3.8
4.0
4.2
V
Vi(HFB)(max)
maximum input voltage
−
−
VP
V
Zi
input impedance
10
−
−
MΩ
−
−
0.3
V
−
−
10
mA
HORIZONTAL OUTPUT; PIN 8, OPEN COLLECTOR; note 35
VOL
LOW-level output voltage
Io(hor)
maximum allowed output current
Vo(max)
maximum allowed output voltage
−
−
VP
V
δ
duty factor
Vo = LOW (ton)
51.6
51.8
52.0
%
ton
switch-on time of horizontal drive
pulse
TV mode, HDTV = 0,
ESS = 0
155
159
163
ms
toff
switch-off time of horizontal drive
pulse
TV mode, HDTV = 0,
ESS = 0
48
50
52
ms
ton(ess)
switch-on time for extended slow
start
TV mode, HDTV = 0,
ESS = 1
1150
1175
1200
ms
2000 May 08
Io = 10 mA
24
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
∆t
PARAMETER
jitter (σ)
CONDITIONS
TDA933xH series
MIN.
TYP.
MAX.
UNIT
1fH mode; note 36
−
1.4
−
ns
2fH mode; note 36
−
1.0
−
ns
0
0.5
1.0
V
SANDCASTLE OUTPUT; PIN 9; note 37
VSCO(0)
zero level
Isink
sink current
Vo(SCO)
output voltage
0.5
0.7
0.9
mA
during clamp pulse
4.2
4.5
4.8
V
during blanking
2.3
2.5
2.7
V
Isource
source current
0.5
0.7
0.9
mA
Ii(grd)
guard pulse input current required
to stop the blanking after a vertical
blanking period
note 38
1.0
−
3.5
mA
tW(1)
pulse width in 1fH mode
clamp pulse, 22 LLC
pulses
−
3.2
−
µs
22/17
−
lines
tW(2)
pulse width in 2fH mode
clamp pulse, 22 LLC
pulses
−
1.6
−
µs
clamp pulse, HDTV = 1,
HDCL = 1, 18 LLC; see
Fig.11
−
1.22
−
µs
vertical blanking (50/60 Hz) −
vertical blanking;
−
depends on VWAIT setting;
see Fig.13
td(bk-HD)
delay between start HD pulse and
start of clamp pulse
−
1fH mode, 37 LLC pulses
−
5.4
−
µs
2fH mode, 37 LLC pulses
−
2.7
−
µs
2fH mode, HDCL = 1,
14 LLC pulses, see Fig.11
−
0.94
−
µs
Vertical synchronization and geometry processing
VD INPUT SIGNAL; PIN 23
VIL
LOW-level of input voltage
−
−
0.8
V
VIH
HIGH-level of input voltage
2.0
−
5.5
V
Ii(VD)
input current
−10
−
+10
µA
tr(VD)
rise time
−
−
100
ns
tf(VD)
fall time
−
−
100
ns
tW(VD)
pulse width
0.5
−
63.5
lines
1fH TV mode
244
−
511.5
lines
1fH VGA mode
175
−
450
lines
2fH; 2fV; TV mode
244
−
511.5
lines
VERTICAL DIVIDER AND RAMP GENERATOR; PINS 15 AND 16; note 39
Nh
2000 May 08
number of lines per field
(VGA mode is valid only for
TDA9331H and TDA9332H)
2fH; 1fV; TV mode
488
−
1023.5
lines
2fH VGA mode
350
−
900
lines
25
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
Nh(nom)
PARAMETER
divider value when not locked
(number of lines per field)
(VGA mode is valid only for
TDA9331H and TDA9332H)
Vsaw(p-p)
sawtooth amplitude
(peak-to-peak value)
Idch
discharge current
Ich(ext)(R)
charge current set by external
resistor
CONDITIONS
TDA933xH series
MIN.
TYP.
MAX.
UNIT
1fH or 2fH; 2fV; TV mode;
VFF = 0
−
312.5
−
lines
1fH or 2fH; 2fV; TV mode;
VFF = 1
−
262.5
−
lines
2fH; 1fV; TV mode; VFF = 0 −
625
−
lines
2fH; 1fV; TV mode; VFF = 1 −
525
−
lines
1fH; VGA mode
−
288
−
lines
2fH; VGA mode
−
576
−
lines
VS = 1FH;
C = 100 nF; R = 39 kΩ
−
3.0
−
V
−
1.2
−
mA
R = 39 kΩ; VS = 1FH;
SVF = 0
−
16
−
µA
R = 39 kΩ; VS = 1FH;
SVF = 1
−
32
−
µA
Slopevert
vertical slope
control range (63 steps)
−20
−
+20
%
∆Ich
charge current increase
60/50 Hz or 120/100 Hz
18.0
19.0
20.0
%
VrampL
LOW-voltage level of ramp
−
2.3
−
V
0.88
0.95
1.02
mA
360
400
440
µA
V
VERTICAL DRIVE OUTPUTS; PINS 1 AND 2
Io(ver)(p-p)
differential output current
(peak-to-peak value)
VA = 1FH
ICM
common mode current
Vo(VDO)
output voltage range
0
−
4.0
Linvert
vertical linearity
upper/lower ratio; note 40
0.99
1.01
1.03
first field delay
DIP = 0; note 41
−
0.5H
−
DE-INTERLACE
D1stfld
E-W WIDTH; note 42
CR
control range
63 steps
100
−
65
%
Io(eq)
equivalent output current
VGA = 0; note 42
0
−
700
µA
Vo(EW)
E-W output voltage range
1.0
−
8.0
V
Io(EW)
E-W output current range
0
−
1200
µA
E-W PARABOLA/WIDTH
CR
control range
63 steps
0
−
22
%
Io(eq)
equivalent output current
E-W = 3FH
0
−
440
µA
E-W CORNER/PARABOLA
CR
control range
63 steps
−43
−
0
%
Io(eq)
equivalent output current
PW = 3FH; E-W = 3FH
−190
−
0
µA
E-W TRAPEZIUM
CR
control range
Io(eq)
equivalent output current
2000 May 08
63 steps
26
−5
−
+5
%
−100
−
+100
µA
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
PARAMETER
CONDITIONS
TDA933xH series
MIN.
TYP.
MAX.
UNIT
E-W EHT TRACKING
Vi(EHTIN)
input voltage
1.2
−
2.8
V
mscan
scan modulation range
−7
−
+7
%
ϕEW
sensitivity
63 steps
0
−
9
%/V
63 steps; SC = 00H
80
−
120
%
760
−
1140
µA
−5
−
+5
%
−50
−
+50
µA
0
−
30
%
VERTICAL AMPLITUDE
CR
control range
Io(eq)(diff)(p-p)
equivalent differential vertical drive SC = 00H
output current (peak-to-peak value)
VERTICAL SHIFT
CR
control range
Io(eq)(diff)(p-p)
equivalent differential vertical drive
output current (peak-to-peak value)
63 steps
S-CORRECTION
CR
control range
63 steps
VERTICAL EHT TRACKING/OVERVOLTAGE PROTECTION
Vi
input voltage
1.2
−
2.8
V
mscan
scan modulation range
±4.5
±5
±5.5
%
ϕvert
vertical sensitivity
5.7
6.3
6.9
%/V
Io(eq)(EW)
EW equivalent output current
+100
−
−100
µA
Vov(det)
overvoltage detection level
3.7
3.9
4.1
V
note 43
VERTICAL ZOOM MODE (OUTPUT CURRENT VARIATION WITH RESPECT TO NOMINAL SCAN); note 44
Fzoom
vertical zoom factor
Flim
output current limiting and RGB
blanking
0.75
−
1.38
1.01
1.05
1.08
63 steps
−18
−
+19
%
23 steps
8
−
31
lines
63 steps
VERTICAL SCROLL; note 45
CR
control range (percentage of
nominal picture amplitude)
VERTICAL WAIT; note 46
td(scan)
delay of start vertical scan
FLASH DETECTION INPUT; PIN 5; note 43
Vi(FLASH)
input voltage range
0
−
VP
V
VFLASH(det)
voltage detection level
−
2
−
V
Vdet(hys)
detection level hysteresis
−
0.2
−
V
tW(FLASH)
pulse width
200
−
−
ns
2000 May 08
27
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SYMBOL
PARAMETER
CONDITIONS
TDA933xH series
MIN.
TYP.
MAX.
UNIT
I2C-bus control inputs/outputs; pins 10 and 11
−
−
VIL
LOW-level input voltage
1.5
V
VIH
HIGH-level input voltage
3.5
−
5.5
V
IIL
LOW-level input current
VIL = 0 V
−
0
−
µA
IIH
HIGH-level input current
VIH = 5.5 V
−
0
−
µA
VOL
LOW-level output voltage
SDA; IOL = 6 mA
−
−
0.6
V
V
DAC OUTPUT; PIN 25; note 47
Vo(min)
minimum output voltage
0.15
0.3
0.4
Vo(max)
maximum output voltage
3.7
4.0
4.3
Zo
output impedance
0.3
−
10
kΩ
Io
output current
−
−
2
mA
note 47
Notes
1. The normal operation of the IC is guaranteed for a supply voltage between 7.2 and 8.8 V. When the supply voltage
drops below the POR level, status bit POR is set and the horizontal output is switched off. When the supply voltage
is between 7.2 V and the POR level, the horizontal frequency is kept in the specified holding range.
2. For the low power start-up mode, a voltage of 5 V has to be supplied to pin 22. The current that is required for this
function is about 3.0 mA. After the start-up voltage is applied, the signal at the horizontal drive output will have
nominal toff, while ton grows gradually from zero to about 30% of the nominal value, resulting in a line frequency of
approximately 50 kHz (2fH) or 25 kHz (1fH). The start-up mode is continued as soon as the main supply voltage is
switched on and the I2C-bus data has been received. After status bit POR has been read out, bits STB must be set
to 1 within 24 ms, to continue slow start. If bits STB are not sent within 24 ms, the horizontal output will be
automatically switched off via slow stop. It is also possible to first set bits STB to 1, before reading bit POR. Start-up
of the horizontal output will then continue 24 ms after bit POR is read. When the main supply is present, the 5 V
supply on pin 22 can be removed. If low power start-up is not used, pin 22 should be connected to ground. More
information can be found in the application report.
3. The RGB to YUV matrix on the RGB-1 input is the inverse of the YUV to RGB matrix for PAL. For a one-on-one
transfer of all three channels from the RGB-1 input to the RGB output, the PAL colour difference matrix should be
selected (MAT = 0, MUS = 0).
4. The colorimetry that is used for high definition ATSC signals is described in document ANSI/SMPTE 274M-1995.
The formula to compute the luminance signal from the RGB primary components differs from the formula that is used
for the PAL system. The consequence is that a different matrix is needed to calculate the internal G − Y signal from
the R − Y and B − Y signals, see the formulas below:
Y
=
0.2126R + 0.7152G + 0.0722B
R–Y =
0.7874R – 0.7152G – 0.0722B
( 1.575 maximum amplitude )
B – Y = – 0.2126R – 0.7152G + 0.9278B
( 1.856 maximum amplitude )
The G − Y signal can be derived from the formula for Y:
G – Y = – 0.2973 ( R – Y ) – 0.1010 ( B – Y )
2000 May 08
28
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
ATSC signals are transmitted as YPBPR signals. The colour-difference components PB and PR are amplitude
corrected versions of B − Y and R − Y:
0.5 ( B – Y )
(B – Y)
P B = --------------------------- = -----------------1 – 0.0722
1.856
0.5 ( R – Y )
(R – Y)
P R = ---------------------------- = ------------------1 – 0.2126
1.575
Note that the “YUV” input of the TDA933xH is actually a Y, −(R − Y) and −(B − Y) input. When the TV set has an input
for a YPBPR signal with amplitudes of 0.7 V for all three components, the signals should be amplified to Y, −(B − Y)
and −(R − Y) signals as follows:
1
= 1.43Y in,TV
Y in,IC = -------- × Y in,TV
0.7
1.856
– ( B – Y ) in,IC = --------------- × P Bin, TV = – 2.65 P B in,TV
0.7
1.575
– ( R – Y ) in,IC = --------------- × P Rin, TV = – 2.25 P R in,TV
0.7
5. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
6. The inputs for RGB-1 and RGB-2 insertion (pins 33 and 38) both supply a small source current to the pins. If the pins
are left open circuit, the input voltage will rise above the insertion switching level.
7. This parameter is measured at nominal settings of the various controls.
8. The switching of the OSD (RGB-2) input has two modes, which can be selected via the I2C-bus:
a) Fast switching between the OSD signal and the internal RGB signals.
b) Blending (fading) function between the OSD signal and the internal RGB signals. The blending control curve is
given in Fig.4. The blender input is optimized for the blender output of the SAA5800 (ArtistIC).
9. The saturation, contrast and brightness controls are active on the YUV signals and on the first RGB input signals.
Nominal contrast is specified with the contrast DAC in position 32 DEC, nominal saturation with the saturation DAC
in position 22 DEC. The second RGB input (which is intended to be used for OSD and teletext display) can only be
controlled on brightness.
10. For video signals with a black level that deviates from the back-porch blanking level, the signal is ‘stretched’ to the
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.8). The black level is
detected by means of an internal capacitor. The black level stretcher can be switched on and off via bit BKS in the
I2C-bus. The values given in the specification are valid only when the luminance input signal has an amplitude of
1 V (b-w).
11. Because of the 2-point black current stabilization circuit, both the black level and the amplitude of the RGB output
signals depend on the drive characteristic of the picture tube. The system checks whether the returning measuring
currents meet the requirement and adapts the output level and gain of the circuit as necessary. Therefore, the typical
values of the black level and amplitude at the output are just given as an indication for the design of the RGB output
stage.
a) The 2-point black level system adapts the drive voltage for each cathode such that the two measuring currents
have the right value. The consequence is that a change in the gain of the output stage will be compensated by a
gain change of the RGB control circuit. Because different picture tubes may require different drive voltage
amplitudes, the ratio between the output signal amplitude and the inserted measuring pulses can be adapted via
the I2C-bus. This is indicated in the parameter ‘Adjustment range of RGB drive levels’.
b) Because of the dependence of the output signal amplitude on the application, the peak-white and soft-clipping
limiting levels have been related to the input signal amplitude.
2000 May 08
29
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
c) The signal amplitude at the RGB outputs of the TDA933xH depends on the gain of the RGB amplifiers. The gain
of the RGB amplifiers should be 35 to get the nominal signal amplitude of 2 V (b-w) at the RGB outputs for a
cathode drive level of 70 V (b-w) and the nominal setting of the drive level bits (CL3210 = 1000, see Table 15).
12. The bandwidth of the video channels depends on the capacitive load at the RGB outputs. For 2fH or VGA
applications, external (PNP) emitter followers on the RGB outputs of the TDA933xH are required, to avoid reduction
of the bandwidth by the capacitance of the wiring between the TDA933xH and the RGB power amplifiers on the
picture tube panel. If emitter followers are used, it should be possible to obtain the bandwidth figures that are
mentioned for 10 pF load capacitance.
13. The timing of the horizontal blanking pulse on the RGB outputs is illustrated in Fig.10.
a) The start of the blanking pulse is determined by an internal counter blanking that starts 40 LLC (line locked clock)
pulses before the centre of the horizontal flyback pulse. This is 5.8 µs for 1fH and 2.9 µs for 2fH TV mode. The
end of the blanking is determined by the trailing edge of the flyback pulse. If required, the start of the counter
blanking can be adjusted in 15 steps with bus bits LBL3 to LBL0. This can be useful when HDTV or VGA signals
are applied to the IC.
b) When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realized by reducing the horizontal scan
amplitude, the edges of the picture may be slightly disturbed. This effect can be prevented by adding an additional
blanking pulse to the RGB signals. This blanking pulse is derived from the horizontal oscillator and is directly
related to the incoming HD pulse (independent of the flyback pulse). The additional blanking pulse overlaps the
normal blanking signal by approximately 1 µs (1fH) or 0.5 µs (2fH) on both sides. This wide blanking is activated
by bit HBL. The phase of this blanking can be controlled in 15 steps by bits HB3 to HB0.
14. When a YUV or RGB signal is applied to the IC and no separate horizontal or vertical timing pulses are available, an
external sync separator circuit is needed. The TDA933xH has an edge triggered phase detector circuit on the HD
input that uses the start of the HD pulse as timing reference. To avoid horizontal phase disturbances during the
vertical blanking period, it is important that the sync separator does not generate extra horizontal sync pulses during
the vertical sync pulse on the video signal.
15. Start-up behaviour of the CCC loop. After the horizontal output is released via bits STB, the RGB outputs are blanked
and the CCC loop is activated. Because the picture tube is cold, the measured cathode currents are too small, and
both gain and offset are set at the maximum value so that the CCC loop gets out of range and status bit BCF is set
to 1. Once the picture tube is warm, the loop comes within range and the set signal for bit BCF is removed. Status
bit BCF is set if the voltage of at least one of the cut-off measurement lines at the RGB outputs is lower than 1.5 V
or higher than 3.5 V. The RGB outputs are unblanked as soon as bit BCF changes from 1 to 0. To avoid a bright
picture after switch-on with a warm picture tube, reset of bit BCF is disabled for 0.5 s after switch-on of the horizontal
output. If required, the blanking period of the RGB outputs can be increased by forcing the blanking level at the RGB
outputs via RBL = 1. When status bit BCF changes from 1 to 0, bit RBL can be set to 0 after a certain waiting period.
16. Voltage Vg2 of the picture tube can be aligned with the help of status bits WBC and HBC. Bit WBC becomes 1 if the
lowest of the three RGB output voltages during the cut-off measurement lines is within the alignment window of
±0.1 V around 2.5 V. Bit HBC is 0 if the lowest cut-off level is below 2.6 V, and 1 if this level is above 2.6 V.
a) Voltage Vg2 should be aligned such that bit WBC becomes 1. If bit WBC is 0, bit HBC indicates in which direction
voltage Vg2 should be adjusted. If bit HBC = 0, the DC level at the RGB outputs of the IC is too low and voltage
Vg2 should be adjusted lower until bit WBC becomes 1. If HBC = 1, the DC level is too high and voltage Vg2 should
be adjusted higher until bit WBC becomes 1.
b) It should be noted that bit WBC is only meant for factory alignment of voltage Vg2. If the value of bit WBC depends
on the video content, this is not a problem. Correct operation of the black current loop is guaranteed as long as
status bit BCF = 0, meaning that the DC level of the measurement lines at the RGB outputs of the IC is between
1.5 and 3.5 V.
17. Signal-to-noise ratio (S/N) is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 10 MHz).
18. This is a current input. When the black current feedback loop is closed (only during measurement lines or during fixed
beam current switch off), the voltage at this pin is clamped at 3.3 V. When the loop is open circuit, the input is not
2000 May 08
30
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
clamped and the maximum sink current is approximately 100 µA. The voltage on the pin must not exceed the supply
voltage.
19. The control circuit contains a PWL circuit and a soft clipper.
a) The detection level of the PWL can be adjusted via the I2C-bus in a control range between 0.65 and 1.0 V (b-w).
This amplitude is related to the Y input signal, typical amplitude 1 V (b-w), at maximum contrast setting. The
detector measures the amplitude of the RGB signals after the contrast control. The output signal of the PWL
detector is filtered by an external capacitor, so that short transients in the video signal do not activate the limiting
action. Because the capacitor is externally available at pin 34, the set maker can adapt the filter time constant as
required. The contrast reduction of the PWL is obtained by discharging the external capacitor at the beam current
limiting input (pin 43). To avoid the PWL circuit from reducing the contrast of the main picture when the amplitude
of the inserted RGB2 signal is too high, the output current of the PWL detector is disabled when the fast blanking
input (pin 38) is high. In blending mode (OBL = 1), the PWL detector is disabled when the blending voltage is
above the 50% insertion level. The soft clipper circuit will still limit the peak voltage at the RGB outputs.
b) In addition to the PWL circuit, the IC contains a soft clipper function which limits short transients that exceed the
PWL. The difference between the PWL and the soft clipping level can be adjusted between 0 and 10% in
three steps via the I2C-bus, with bus bits SC1 and SC0 (soft clipping level equal or higher than the PWL). It is
also possible to switch off the soft clipping function.
20. The above-mentioned output amplitude range at which the PWL detector is activated is valid for nominal settings of
the white point controls, and when the CCC loop is switched off or set to 1-point stabilization mode. In 2-point
stabilization mode, the mentioned range is only valid when the gain of the RGB output stages is dimensioned such
that the RGB output amplitudes are 2 V (b-w) for nominal contrast setting, see also note 11.
21. The soft clipper gain reduction is measured by applying a sawtooth signal with rising slope and 1 V (b-w) at the
luminance input. To prevent the beam current limiter from operating, a DC voltage of 3.5 V must be applied to pin 43.
The contrast is set at the maximum value, the PWL at the minimum value, and the soft clipping level is set at 0%
above the PWL (SC10 = 00). The tangents of the sawtooth waveform at one of the RGB outputs is now determined
at the beginning and end of the sawtooth. The soft clipper gain reduction is defined as the ratio of the slopes of the
tangents for black and white, see Fig.9.
22. When the blue stretch function is activated (via I2C-bus bit BLS), the gain of the red and green channels is reduced
for input signals that exceed a value of 80% of the nominal amplitude. The result is that the white point is shifted to
a higher colour temperature.
23. Switch-off behaviour of TDA933xH. For applications with an EHT generator without bleeder resistor, the picture tube
capacitance can be discharged with a fixed beam current when the set is switched off. The magnitude of the
discharge current is controlled via the black current loop. The fixed beam current mode can be activated with bit FBC.
With the fixed beam current option activated, it is still possible to have a black screen during switch-off. This is
realized by placing the vertical deflection in the overscan position. This mode is activated by bit OSO. There are two
possible situations for switch-off (see notes 24 and 25).
24. The set is switched to standby via the I2C-bus. In this situation, the procedure is as follows:
a) Vertical scan is completed.
b) Vertical flyback is completed.
c) Slow stop of the horizontal output is started, by gradually reducing the ‘on-time’ at the horizontal output from
nominal to zero.
d) At the same moment, the fixed beam current is forced via the black current loop (if FBC = 1).
e) If OSO = 1, the vertical deflection stays in overscan position; if OSO = 0, the vertical deflection keeps running.
f) The slow stop time is approximately 50 ms, the fixed beam current flows for 18.6 ms or 25 ms, depending on the
value of bit TFBC, see Fig.15.
25. The set is switched off via the mains power switch. When the mains supply is switched off, the supply voltage of the
line deflection circuit of the TV set will decrease. A detection circuit must be made that monitors this supply voltage.
2000 May 08
31
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
When the supply voltage suddenly decreases, pin FBCSO (fixed beam current switch-off) of the TDA933xH must be
pulled high. In this situation, the procedure is as follows:
a) Vertical scan is completed.
b) Vertical flyback is completed.
c) The fixed beam current is forced via the black current loop (if FBC = 1). The horizontal output keeps running.
As the supply voltage for the line transformer decreases, the EHT voltage will also decrease.
d) If OSO = 1, the vertical deflection stays in overscan position; if OSO = 0, the vertical deflection keeps running.
e) When the supply voltage of the TDA933xH drops below the POR level, horizontal output and fixed beam current
are stopped.
26. The discharge current for the picture tube can be increased with an external current division circuit on the black
current input (pin 44). The current division should only be active for high cathode currents, so that the operation of
the black current stabilization loop is not affected. When the feedback current supplied to pin 44 is less than 1mA,
the DC level at the RGB outputs will go to the maximum value of 6.0 V (2-point black current stabilization) or 5.6 V
(1-point or no black current stabilization).
27. A stable switching of the HD input is realized by using a Schmitt trigger input.
28. The simplified circuit diagram of the oscillator is given in Fig.3. To ensure that the oscillator will start-up, the ceramic
resonator must fulfil the following condition: C L2 × R i ≤ 1.1 × 10 –19 .
Example: When the resonator is loaded with 60 pF (this is a typical value for a 12 MHz resonator), the series
resistance of the resonator must be smaller than 30 Ω.
A suitable ceramic resonator for use with the TDA933xH is the Murata CST12.0MT, which has built-in load
capacitances Ca and Cb. For higher accuracy, it is also possible to use a quartz crystal, which is even less critical
with respect to start-up because of its lower load capacitance.
29. Pin HSEL must be connected to ground in a 1fH application; it must be left open circuit for a 2fH application. The
TDA9331H and TDA9332H can be switched to a multi-sync mode, in which the horizontal frequency can vary
between 15 and 25 kHz (1fH mode) or 30 and 50 kHz (2fH mode).
30. The indicated tolerance on the free-running frequency is only valid when an accurate reference frequency (obtained
with an accurate 12 MHz crystal) is used. The tolerance of the reference resonator must be added to obtain the real
tolerance on the free-running frequency.
31. The correction factor k of the phase-2 loop is defined as the amount of correction per line period of a phase error
between the horizontal flyback pulse and the internal phase-2 reference pulse. When k = 0.5, the phase error
between the flyback pulse and the internal reference is halved each line period.
32. The control range of the second control loop depends on the line frequency. The maximum control range from the
rising edge of HOUT to the centre of the flyback pulse is always 37% of one line period, for the centre position of the
dynamic phase compensation (4.0 V at pin 14).
33. The dynamic phase compensation input (pin 14) is connected to an internal reference voltage of 4.0 V via a resistor
of 100 kΩ. If dynamic phase compensation is not used, this pin should be decoupled to ground (pin 19) via a
capacitor of 100 nF.
34. The range of parallelogram and bow correction is proportional to the width of the horizontal flyback pulse. For zero
correction, use DAC setting 7 DEC or 0111 (bin). The effect of the corrections is shown in Fig.16.
35. For safe operation of the horizontal output transistor and to obtain a controlled switch-on time of the EHT, the
horizontal drive starts up in a slow start mode. The horizontal drive starts with a very short ‘on-time’ of the horizontal
output transistor (line locked clock pulse, i.e. 72 ns), the ‘off-time’ of the transistor is identical to the ‘off-time’ in normal
operation. The starting frequency during switch-on is therefore approximately twice the normal value. The ton is
slowly increased to the nominal value in approximately 160 ms (see Fig.15). When the nominal frequency is reached,
the PLL is closed such that only very small phase corrections are necessary. This ensures safe operation of the
output stage.
2000 May 08
32
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
a) For picture tubes with Dynamic Astigmatic Focusing (DAF) guns, the rise of the EHT voltage between
75 and 100% is preferred to be even slower than the rise time from 0 to 75%. This can be realized by activating
bit ESS, at which the total switch-on time of the horizontal output pulse is approximately 1175 ms.
b) During switch-off, the slow-stop function is active. This is realized by decreasing the ton of the output transistor
complementary to the start-up behaviour. The switch-off time is approximately 50 ms. The slow-stop procedure
is synchronized to the start of the first new vertical field after reception of the switch-off command. During the
slow-stop period, the fixed beam current switch-off can be activated (see also note 23). This current is active
during a part of the slow stop period, see Fig.15.
c) The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched
on during the flyback pulse. This protection is not active during the switch-on or switch-off period.
36. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
37. The rise and fall times of the blanking pulse and clamping pulse at the sandcastle output (pin 9) depend on the
capacitive load. The value of the source current during the rising edge or sink current during the falling edge is
0.7 mA (typical value).
38. The vertical guard pulse from the vertical output stage should fall within the vertical blanking period
(see Figs 12 and 13) and should have a width of at least one line period. For the detection of a missing pulse, a guard
current value of 1 mA during normal operation is sufficient. If the RGB outputs must also be blanked if the guard pulse
lasts longer than the vertical blanking period, the guard current must have a value between 2.6 mA and 3.5 mA.
39. Switching between the 1fV or the 2fV mode is realized via bit SVF.
40. The vertical linearity is measured on the differential output current at the vertical drive output (pins 1 and 2) for zero
S-correction. The linearity is defined as the ratio of the upper and lower half amplitudes at the vertical output. The
upper amplitude is measured between lines 27 and 167, the lower amplitude between lines 167 and 307 for a 50 Hz
video signal.
41. The field detection mechanism is explained in Fig.17.
a) The incoming VD pulse is synchronized with the internal clock signal CK2H that is locked to the incoming HD
pulse. If the synchronized VD pulse of a field coincides with the internally generated horizontal blanking signal
HBLNK, then this is field 1. If the synchronized VD pulse does not coincide with HBLNK, then this is field 2. Signals
CK2H and HBLNK are both output signals of the horizontal divider circuit that is part of the line-locked clock
generator. A reliable field detection is important for correct interlacing and de-interlacing and for the correct timing
of the measurement lines of the black current loop. For the best noise margin, the edges of the VD pulse should
be on approximately 1⁄4 and 3⁄4 of the line, referred to the rising edges of the HD input signal.
b) If bus bit VSR = 0, the end of the VD pulse is used as reference for both field detection and start of vertical scan.
If VSR = 1, the starting edge is used.
42. Output range percentages mentioned for E-W control parameters are based on the assumption that the E-W
modulator is dimensioned such that 400 µA variation in E-W output current of the IC is equivalent to 20% variation
in picture width. In VGA mode, the E-W output current is proportional to the applied line frequency.
43. The IC has protection inputs for flash protection and overvoltage protection.
a) The flash protection input is used to switch the horizontal drive output off immediately if a picture tube flashover
occurs, to protect the line output transistor. An external flash detection circuit is needed. When the flash input is
pulled HIGH, the horizontal output is switched off and status bit FLS is set. When the input turns LOW again, the
horizontal output is switched on immediately without I2C-bus intervention via the slow start procedure.
b) The overvoltage (X-ray) protection is combined with the EHT compensation input. When this protection is
activated, the horizontal drive can be directly switched off (via the slow stop procedure). It is also possible to
continue the horizontal drive and only set status bit XPR in output byte 01 of the I2C-bus. The choice between the
two modes of operation is made via bit PRD.
44. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason, an extra DAC
is included in the vertical amplitude control, which controls the vertical scan amplitude between 0.75 and 1.38 of the
2000 May 08
33
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
nominal scan. At an amplitude of 1.05 times the nominal scan, the output current is limited and the blanking of the
RGB outputs is activated, see Fig.14. In addition to the variation of the vertical amplitude, the picture can be vertically
shifted on the screen via the ‘scroll’ function. The nominal scan height must be adjusted at a position of 19H (25 DEC)
of the vertical ‘zoom’ DAC and 1FH (31 DEC) for the vertical ‘scroll’ DAC.
45. The vertical scroll function is active only in the expand mode of the vertical zoom, i.e. at a DAC position larger
than 10H (16 DEC).
46. With the vertical wait function, the start of the vertical scan can be delayed with respect to the incoming vertical sync
pulse. The operation is different for the various scan modes, see Table 54 and Figs 12 and 13. The minimum value
for the vertical wait is 8 line periods. If the setting is lower than 8, the wait period will remain 8 line periods.
47. In the TDA9330H and TDA9332H, the DAC output is I2C-bus controlled. In the TDA9331H, the DAC output voltage
is proportional to the centre frequency of the line-oscillator. In TV mode, the output voltage will always be at the
minimum value. In VGA mode, the output is at the minimum value for the lowest centre frequency (32 kHz) and at
the maximum value for the highest centre frequency (48 kHz). The output impedance of the DAC output depends on
the output voltage. The output consists of an emitter follower with an internal resistor of 50 kΩ to ground.
Table 54 Operation of the vertical wait function
MODE
START OF VERTICAL SCAN
1fH; TV mode
fixed; see Fig.12
2fH; TV mode; VSR = 0
end of VD plus vertical wait setting
2fH; TV mode; VSR = 1
start of VD plus vertical wait setting
1fH; multi sync mode
start of VD plus vertical wait setting
2fH; multi sync mode
start of VD plus vertical wait setting
2000 May 08
34
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
1
f osc = ------------------------------------Ci × CL
2π L i × ------------------Ci + CL
gm
handbook, halfpage
Ca × Cb
C L = C p + ------------------Ca + Cb
100 kΩ
XTALI
XTALO
Li
Cp
Ci
Ri
Ca
crystal
or
ceramic
resonator
Requirement for start-up:
2
– 19
C L × R i ≤ 1.1 × 10
Cb
MGR447
Fig.3 Simplified diagram of crystal oscillator.
MGR448
100
handbook, full pagewidth
blending
(%)
80
external
60
40
internal
20
0
0
0.2
0.4
0.31
0.6
0.8
0.725
1.0
1.2
1.14
Vinsert (V)
Fig.4 Blending characteristic (typical curve and minimum/maximum limits).
2000 May 08
35
1.4
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
MGS892
300
MGS893
200
handbook, halfpage
handbook, halfpage
(%)
(%)
160
200
120
80
100
40
0
0
0
20
40
60
80
DAC (decimal value)
0
20
Fig.5 Saturation control curve.
40
60
80
DAC (decimal value)
Fig.6 Contrast control curve.
MGS894
MGR452
100
output
(IRE)
80
handbook, halfpage
handbook, halfpage
1
(V)
0.5
60
0
40
−0.5
20
B
0
−1
0
20
40
−20
60
80
DAC (decimal value)
Conditions: settings for cathode drive and white point nominal;
gain of RGB amplifiers such that the amplitude at the RGB
outputs is 2 V (b-w); relative to cutoff level.
B
A
0
40
80
input (IRE)
120
A-to-A: maximum black level shift.
B-to-B: level shift at 15% of peak white.
Fig.7 Brightness control curve.
2000 May 08
A
Fig.8 I/O relation of black level stretch circuit.
36
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
handbook, full pagewidth
TDA933xH series
MGS895
4
Vo(RGB)(b-w)
(V)
clipper off
3
tangent
B
2
A
1
0
0
20
40
60
100
80
YIN (IRE)
PWL
input level
Fig.9 Soft clipper characteristic.
2000 May 08
PWL
output level
clipper on
37
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
reference phi1
handbook, full pagewidth
HD input pulse
(1)
wide blanking
(if HBL = 1)
101 LLC
HSHIFT
0 to 63 LLC
phase slicing level (4 V)
horizontal
flyback pulse
blanking slicing level (0.3 V)
flyback blanking
(2)
counter blanking
40 LLC
video blanking
MGS896
reference phi2
1) Position of wide blanking can be adjusted with bus bits HB3 to HB0.
2) Start of line blanking can be adjusted with bus bits LBL3 to LBL0.
Fig.10 Timing of horizontal blanking (1 line period is 440 LLC pulses).
2000 May 08
38
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
handbook, full pagewidth
TDA933xH series
5.5 µs
2f H NTSC
signal
(fH = 31.47 kHz)
0.75 µs
2.40 µs
2.35 µs
mid blank = mid flyback
HD input
HSHIFT
22 LLC = 1.59 µs
37 LLC = 2.67 µs
CLP pulse
40 LLC = 2.89 µs
counter
blanking
− 16 LLC
+ 14 LLC
(a) Timing in 2 fH TV mode (HDTV = 0, HDCL = 0)
0.592 µs 0.592 µs
HDTV
signal
(fH = 33.75 kHz)
3.784 µs
0.606 µs
1.993 µs
50 ns
mid blank = mid flyback
HD input
HSHIFT
15 LLC = 1.01 µs
18 LLC = 1.22 µs
CLP pulse
40 LLC = 2.69 µs
counter
blanking
− 16 LLC
+ 14 LLC
MGS897
(b) Timing in HDTV mode (HDTV = 1, HDCL = 1)
Video signals are shown as illustration only. All horizontal timing signals in the IC are solely related to the start of the HD pulse
that is applied to the IC.
All horizontal timing signals are generated with the help of the internal line locked clock (LLC). One line period is always divided
into 440 line locked clock pulses. Time periods depicted in the figure are only valid for line frequencies mentioned.
Fig.11 Timing of clamp pulse and line blanking in 2fH TV mode and HDTV mode.
2000 May 08
39
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
VD = VA
23
1st
field
HD = HA
Internal
2f H clock
L
R
G
B
AKB pulses
Vertical
blank
Reset vertical
sawtooth
336
Video from
HIP
312
VD = VA
2nd
field
HD = HA
L
R
G
B
AKB pulses
40
Vertical
blank
50 Hz
Philips Semiconductors
625
I2C-bus controlled TV display processors
handbook, full pagewidth
2000 May 08
RESET LINE COUNTER
Video from
HIP
VD
HD
Internal
2f H clock
L
R
G
1st
field
B
AKB pulses
Vertical
blank
VD
L
R
G
2nd
field
B
AKB pulses
Vertical
blank
60 Hz
Fig.12 Vertical timing pulses for 1fH TV mode.
MGR453
Preliminary specification
HD
TDA933xH series
Reset vertical
sawtooth
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
HD
Internal
2f H clock
1st
field
L
R
G
B
AKB pulses
Vertical
blank
VWAIT = 12
Reset vertical
sawtooth
VD
HD
L
R
G
2nd
field
B
AKB pulses
Vertical
blank
41
2fH TV mode (VSR = 0)
Philips Semiconductors
VD
I2C-bus controlled TV display processors
REFERENCE VWAIT
handbook, full pagewidth
2000 May 08
RESET LINE COUNTER
RESET LINE COUNTER = REFERENCE VWAIT
VD
HD
Internal
2f H clock
L
R
G
B
AKB pulses
Vertical sawtooth
measure pulse
2fH VGA mode
Fig.13 Vertical timing pulses for 2fH TV mode and VGA mode.
MGR454
Preliminary specification
VWAIT = 18
Reset vertical
sawtooth
TDA933xH series
Vertical
blank
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
handbook, full pagewidth
70
vertical
position
(%)
MGL475
top
picture
60
TDA933xH series
50
138%
40
30
20
100%
75%
10
t
1/2 t
0
time
−10
−20
−30
−40
−50
−60
bottom
picture
blanking for zoom 138%
Fig.14 Vertical drive waveform and blanking pulse for different zoom factors.
2000 May 08
42
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
handbook, full pagewidth
TDA933xH series
MGS898
100
normal
Ton
(% of nominal value)
ESS = 1
slow start
slow stop
50
57 ms
102 ms
32 ms
(1000 lines)
18 ms
12
t (ms)
16 ms
discharge
18.6 ms
25 ms
TFBC = 0
TFBC = 1
Fig.15 Slow start behaviour of horizontal output, and slow stop behaviour and timing of picture tube discharge
pulse when IC is switched to standby via I2C-bus.
handbook, full pagewidth
MGS899
0.54 0.54
µs µs
0.54 0.54
µs µs
(a) Parallelogram correction.
(b) Bow correction.
Fig.16 Horizontal parallelogram and bow correction (figures for 1fH mode).
2000 May 08
43
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
handbook, full pagewidth
MGS900
VD
VD
HD
HD
CLK2H
CLK2H
HBLNK
HBLNK
field 1 detection
field 1 detection
VD
VD
HD
HD
CLK2H
CLK2H
HBLNK
HBLNK
field 2 detection
field 2 detection
(b) Start of VD pulse is reference (VSR = 1)
(a) End of VD pulse is reference (VSR = 0)
See also Chapter “Characteristics”; note 41.
Fig.17 Field detection mechanism.
2000 May 08
44
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
TEST AND APPLICATION INFORMATION
RGB-1
handbook, full pagewidth
RGB-2
RGB-3
RGB-4
TUNER AGC
SAW
FILTER
IF
Y
YIN
U
UIN
V
VIN
RO
GO
BO
CVBS-1
AV-1
BCL
CVBS-2
FEATURE
BOX
TDA932xH
TDA933xH
BLKIN
AV-2
CVBS/Y-3
C-3
CVBS/Y-4
HA
HD
VA
VD
VDOA
VDOB
EWO
HOUT
C-4
HFB
MGR462
CVBS(TXT)
CVBS(PIP)
CVBS
Y
C
COMB FILTER
Fig.18 Application diagram.
2000 May 08
45
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
MGL483
600
Ivert
(µA)
(2)
400
MGL484
800
handbook, halfpage
handbook,
halfpage
(3)
I
vert
(µA)
TDA933xH series
(1)
400
200
0
0
(1)
−200
(2)
−400
(3)
−400
−600
−800
0
0.5 t
t
time
VSH = 31; SC = 0; IVERT = I2(VDOB) − I1(VDOA).
(1) VA = 0.
(2) VA = 31.
(3) VA = 63.
0
t
time
VA = 31; VHS = 31; SC = 0.
(1) VS = 0.
(2) VS = 31.
(3) VS = 63.
Fig.19 Control range of vertical amplitude.
Fig.20 Control range of vertical slope.
MGL485
600
MGL486
600
handbook,
halfpage
I
handbook,
halfpage
I
vert
(µA)
vert
(µA)
400
400
(1)
(2)
(3)
200
0
−200
−200
−400
−400
0
(3)
(2)
(1)
200
0
−600
0.5 t
0.5 t
time
−600
t
0
VA = 31; SC = 0.
(1) VSH = 0.
VA = 31; VHS = 31.
(1) SC = 0.
(2) VSH = 31.
(3) VSH = 63.
(2) SC = 31.
(3) SC = 63.
Fig.21 Control range of vertical shift.
2000 May 08
0.5 t
time
Fig.22 Control range of S-correction.
46
t
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
MGL489
1200
IEW
MGL488
900
EW
(µA)
800
handbook, halfpage
(µA)
1000
TDA933xH series
handbook,
halfpage
I
(1)
(3)
700
800
(2)
600
600
(2)
400
500
(3)
400
200
(1)
300
0
0.5 t
0
t
time
0
PW = 31; CP = 31.
(1) EW = 0.
(2) EW = 31.
(3) EW = 63.
0.5 t
t
time
EW = 31; CP = 31.
(1) PW = 0.
(2) PW = 31.
(3) PW = 63.
Fig.23 Control range of E-W width.
Fig.24 Control range of E-W parabola/width ratio.
MGL487
MGL490
1000
900
handbook, halfpage
IEW
(1)
handbook, halfpage
IEW
(µA)
(µA)
800
800
(2)
(3)
(2)
(1)
700
(1)
(2)
(3)
(3)
600
600
500
400
400
200
300
0
0.5 t
time
0
t
0.5 t
time
t
EW = 31; PW = 63.
(1) CP = 0.
EW = 31; PW = 31.
(1) TC = 0.
(2) CP = 31.
(3) CP = 63.
(2) TC = 31.
(3) TC = 63.
Fig.25 Control range of E-W corner/parabola ratio.
Fig.26 Control range of E-W trapezium correction.
2000 May 08
47
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
To adjust the vertical shift and vertical slope independently
of each other, a special service blanking mode can be
entered by setting bit SBL HIGH. In this mode, the RGB
outputs are blanked during the second half of the picture.
There are two different methods for alignment of the
picture in the vertical direction. Both methods use the
service blanking mode.
Adjustment of geometry control parameters
The deflection processor of the TDA933xH offers
15 control parameters for picture alignment, as follows:
For the vertical picture alignment;
• S-correction
• Vertical amplitude
The first method is recommended for picture tubes that
have a marking for the middle of the screen. With the
vertical shift control, the last line of the visible picture is
positioned exactly in the middle of the screen. After this
adjustment, the vertical shift should not be changed any
more. The top of the picture is positioned by adjusting the
vertical amplitude, and the bottom by adjusting the vertical
slope.
• Vertical slope
• Vertical shift
• Vertical zoom
• Vertical scroll
• Vertical wait.
For the horizontal picture alignment;
• Horizontal shift
The second method is recommended for picture tubes that
have no marking for the middle of the screen. For this
method, a video signal is required in which the middle of
the picture is indicated (e.g. the white line in the circle test
pattern). The beginning of the blanking is positioned
exactly on the middle of the picture using the vertical slope
control. The top and bottom of the picture are then
positioned symmetrically with respect to the middle of the
screen by adjusting the vertical amplitude and vertical
shift. After this adjustment, the vertical shift has the correct
setting and should not be changed any more.
• Horizontal parallelogram
• Horizontal bow
• E-W width with extended range for the zoom function
• E-W parabola/width ratio
• E-W upper corner/parabola ratio
• E-W lower corner/parabola ratio
• E-W trapezium correction.
It is important to notice that the ICs are designed for use
with a DC-coupled vertical deflection stage. This is why
a vertical linearity alignment is not necessary (and
therefore not available).
If the vertical shift alignment is not required, VSH should
be set to its mid-value, i.e. VSH = 1FH (31 DEC). The top
of the picture is then positioned by adjusting the vertical
amplitude and the bottom of the picture by adjusting the
vertical slope.
For a particular combination of picture tube type, vertical
output stage and E-W output stage, the required values for
the settings of S-correction and E-W corner/parabola ratio
must be determined. These parameters can be preset via
the I2C-bus and do not need any additional adjustment.
The rest of the parameters are preset with the mid-value of
their control range, i.e. 1FH, or with the values obtained by
previously-adjusted TV sets on the production line.
After the vertical picture alignment, the picture is
positioned in the horizontal direction by adjusting the E-W
width, E-W parabola/width ratio and horizontal shift. Finally
(if necessary), the left and right-hand sides of the picture
are aligned in parallel by adjusting the E-W trapezium
control.
The vertical shift control is intended to compensate offsets
in the external vertical output stage or in the picture tube.
It can be shown that, without compensation, these offsets
will result in a certain linearity error, especially with picture
tubes that need large S-correction. In 1st-order
approximation, the total linearity error is proportional to the
value of the offset and to the square of the S-correction
that is needed. The necessity to use the vertical shift
alignment depends on the expected offsets in the vertical
output stage and picture tube, on the required value of the
S-correction and on the demands upon vertical linearity.
2000 May 08
TDA933xH series
Additional horizontal corrections are possible using the
parallelogram and bow controls.
To obtain the correct range of the vertical zoom function,
the vertical geometry should be adjusted at a nominal
setting of the zoom DAC at position 19H (25 DEC) and the
vertical scroll DAC at 1FH (31 DEC).
48
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y
X
A
33
23
34
22
ZE
e
E HE
A A2
wM
(A 3)
A1
θ
bp
Lp
pin 1 index
L
12
44
1
detail X
11
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
2.10
0.25
0.05
1.85
1.65
0.25
0.40
0.20
0.25
0.14
10.1
9.9
10.1
9.9
0.8
12.9
12.3
12.9
12.3
1.3
0.95
0.55
0.15
0.15
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
10
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-02-04
97-08-01
SOT307-2
2000 May 08
EUROPEAN
PROJECTION
49
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
SOLDERING
TDA933xH series
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 May 08
50
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 May 08
51
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
TDA933xH series
DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 May 08
52
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
NOTES
2000 May 08
53
TDA933xH series
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
NOTES
2000 May 08
54
TDA933xH series
Philips Semiconductors
Preliminary specification
I2C-bus controlled TV display processors
NOTES
2000 May 08
55
TDA933xH series
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 69
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp56
Date of release: 2000
May 08
Document order number:
9397 750 06406