INTEGRATED CIRCUITS DATA SHEET TDA8753A YUV 8-bit analog-to-digital interface Product specification Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02 1996 Jan 12 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A FEATURES APPLICATIONS • Triple analog-to-digital converter • High-speed analog-to-digital conversion for video signal digitizing in 4 : 1 : 1 format • 8-bit resolution • 100 Hz improved definition TV for all formats (4/3, 16/9, 14/9 etc.). • Sampling rate up to 20 MHz • Power dissipation of 500 mW (typical) • Internal clamp functions GENERAL DESCRIPTION • 4 : 1 : 1 output data encoder The TDA8753A is a monolithic CMOS 8-bit video low-power analog-to-digital conversion interface for YUV signals. It converts the YUV analog input signal into 8-bit binary coded digital words in format 4 : 1 : 1 at a sampling rate of 20 MHz. All analog signal inputs are clamped. The device includes a digital sample rate converter for variable compression with a factor 1 to 2. • Y binary output • U, V two's complement outputs • Sample rate converter permits programmable horizontal compression factors from 1 to 2 • Serial microcontroller interface • TTL compatible inputs. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. VDDA analog supply voltage 4.75 5.0 VDDD digital supply voltage 4.75 5.0 5.25 V IDDA analog supply current − 55 63 mA IDDD digital supply current − 45 55 mA INL integral non-linearity fclk = 16 MHz; ramp input − ±0.75 − LSB DLE differential non-linearity fclk = 16 MHz; ramp input; Y − ±0.5 0.75 LSB fclk = 16 MHz; ramp input; U and V − ±0.6 ±0.9 LSB note 1 43 − − dB 20 − − MHz − 500 650 mW SNR signal-to-noise ratio without harmonics fclk maximum conversion rate Ptot total power dissipation note 2 5.25 UNIT V Notes 1. The signal-to-noise ratio without harmonics is measured using a 16 MHz clock frequency. This value is given for a 4.43 MHz input frequency on the Y channel (1.5 MHz on the U and V channels). 2. The external resistor (between VDDA and Iref) fixing internal static currents influences Ptot. The value of the resistor should be 5.6 kΩ (5%). ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8753A SDIP42 1996 Jan 12 DESCRIPTION plastic shrink dual in-line package; 42 leads (600 mil) 2 VERSION SOT270-1 1996 Jan 12 3 29 28 DECref(L) 32 33 31 Vref(H) INV VSSA3 VDDA3 35 36 VSSA2 INU 34 38 39 VDDA2 INY VSSA1 V DDA1 27 37 30 VSSA4 VSSA5 x 1.5 CLAMP CIRCUIT x 1.5 CLAMP CIRCUIT x 1.5 CLAMP CIRCUIT 26 20 VDDD1 25 DELAY UPDA 40 UPCL 41 22 21 DTO 23 RESET HOLD PHI H ref 19 WEI 18 MEMORY INTERFACE MIXER DELAY SIGN DELTA U AND V FORMATTER DIFF ENABLE RESET V50 MODE0 MSCAN MODE1 42 RESET SIGN DELTA DELTA HOLD Fig.1 Block diagram. VSSD1 24 SERIAL INTERFACE DELTA INTERPOLATION DOWNSAMPLING HOLD DELAY ON/OFF NOTCH ON/OFF NOTCH CORING AND PREFILTER ON/OFF NOTCH 10 V SSD2 LOW-PASS FILTER INTERPOLATION DOWNSAMPLING ON/OFF DELAY CORING AND PREFILTER PREFILTER 9 V DDD2 MBE424 17 11/13 12/14 1 8 WEO UV0 UV1 Y0 Y7 YUV 8-bit analog-to-digital interface V SSD3 15 TDA8753A 8 BIT ADC 8 BIT ADC 8 BIT ADC 16 CLK handbook, full pagewidth Iref CLAMP Philips Semiconductors Product specification TDA8753A BLOCK DIAGRAM Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION Y7 1 Y data output, bit 7 (MSB) UPCL 40 control clock input Y6 2 Y data output, bit 6 UPDA 41 serial interface data input Y5 3 Y data output, bit 5 V50 42 data execution input Y4 4 Y data output, bit 4 Y3 5 Y data output, bit 3 Y2 6 Y data output, bit 2 Y1 7 Y data output, bit 1 Y0 8 Y data output, bit 0 (LSB) VDDD2 9 digital supply voltage 2, (+5 V) VSSD2 10 digital ground 2 U1 11 U data output, bit 1 (n) Y7 1 42 V50 U0 12 U data output, bit 0 (n − 1) Y6 2 41 UPDA V1 13 V data output, bit 1 (n) Y5 3 40 UPCL V0 14 V data output, bit 0 (n − 1) Y4 4 39 VSSA1 VSSD3 15 digital ground 3 Y3 5 38 INY CLK 16 clock input WEO 17 write enable output Y2 6 37 VDDA1 WEI 18 write enable input Y1 7 36 VSSA2 Href 19 horizontal reference signal input Y0 8 35 INU CLAMP 20 clamp control input VDDD2 9 34 VDDA2 MODE1 21 test mode select VSSD2 10 33 VSSA3 MODE0 22 test mode select MSCAN 23 test pin VSSD1 24 digital ground 1 VDDD1 25 digital supply voltage 1 (+5 V) VSSA5 26 analog ground 5 Iref 27 current level reference DECref(L) 28 decoupling output from reference LOW Vref(H) 29 reference voltage input (HIGH) VSSA4 30 analog ground 4 VDDA3 31 analog supply voltage 3, (+5 V) INV 32 V analog voltage input CLAMP 20 23 MSCAN VSSA3 33 analog ground 3 MODE1 21 22 MODE0 VDDA2 34 analog supply voltage 2 (+5 V) INU 35 U analog voltage input VSSA2 36 analog ground 2 VDDA1 37 analog supply voltage 1 (+5 V) INY 38 Y analog voltage input VSSA1 39 analog ground 1 1996 Jan 12 handbook, halfpage U1 11 TDA8753A 32 INV U0 12 31 VDDA3 V1 13 30 VSSA4 V0 14 29 Vref(H) VSSD3 15 28 DEC ref(L) 27 I ref CLK 16 WEO 17 26 VSSA5 WEI 18 25 VDDD1 Href 19 24 VSSD1 MBE425 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A The TDA8753A has three addressable control registers which can be loaded via the signals UPDA and UPCL. The format of this bus is fixed according to mode 0 of the 8051 family UART at 1 Mbaud (8 bits are transmitted, LSB first). FUNCTIONAL DESCRIPTION Analog-to-digital converter The TDA8753 implements 3 independent CMOS 8-bit analog-to-digital converters. The converters use a multi-step approach with offset compensated comparators. Serial interface protocol POWER-ON STATE Clamping When powered up the SIO is in an unknown state and all data in the registers is random. When signals are applied to UPCL and UPDA in this state, the behaviour is unpredictable. The only way to exit from this state to a known state is apply a V50 signal to the TDA8753A. An internal clamping circuit is provided in each of the 3 analog channels. The analog pins INY, INV and INU are switched to on-chip clamping levels during an active pulse on the clamp input CLP.The clamping level in the Y channel is code level 16. The clamping level in the U/V channel is code level 128 (output code 0 in the 2's complement description) see Tables 3 and 4. INITIALIZATION STATE From power-on or any other state, the INIT state is entered (at the latest) one TDA8753A clock period after the end of the V50 HIGH state. In this state the F0, F1 and F2 TDA8753A registers are loaded with the values that are in the corresponding line buffers BF0, BF1 and BF2. The first time V50 is issued after power-on, this data is unknown. After a rising UPCL edge has been detected, the address reception state is entered. Sample rate converter A sample rate converter is integrated in the TDA8753A to facilitate programming of the horizontal aspect ratio which can be varied from a factor 1 to 2. This includes conversion from 16/9 to 14/9 and 4/3. In the U/V channel a linear interpolation is sufficient because of the four times oversampling. ADDRESS RECEPTION STATE Discrete time oscillator (DTO) Bits are counted at each rising UPCL edge. The next 8 bits received on UPDA line are considered as address bits. The address reception is illustrated in Fig.3. A discrete time oscillator is used to calculate for every sample of the phase delay that is needed for a given compression factor. Serial interface (SIO) All controls are sent to the TDA8753A via a serial microprocessor interface. Data from this interface will be made active at the vertical input pulse V50. incoming stream handbook, halfpage 1 1 1 1 0 0 first data bit of data value for address F2 register last address bit received 1 0 first bit received MBE426 (in this example address received is F2 hex) Fig.3 Address reception. 1996 Jan 12 5 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A The TDA8753A registers have address F0, F1 and F2 hexadecimal notation. Whenever the received address (decoded on the first 8 bits received) is one of these, the event is recorded in such a way that the next data received by the TDA8753A will be captured in the line buffer BF0, BF1 and BF2 respectively. DATA RECEPTION STATE The next 8 bits are considered as data bits according to the format of Fig.4. When 8 data bits have been received, the data is recorded in the BF0, BF1 or BF2 line buffers if the previous address recorded was F0 hex, F1 hex or F2 hex respectively. The bit count is then reset to zero and the address reception state is entered. This state may be ended any time when V50 goes HIGH but in that condition F0, F1 and F2 registers may not be loaded properly. When 8 bits have been received, the data reception state is entered. The address reception state can also be exited at any time when V50 goes HIGH. The F0, F1 and F2 registers may not be loaded properly if there is some activity in progress on the incoming line. last address bit received incoming stream handbook, halfpage 1 1 0 X X first bit of next address stream Data value is F2 X X X first data bit of value (e.g. for address F2 register) 0:2 = 110(DEL 0:2 ) MBE427 Fig.4 Data reception. Table 1 Data allocation ADDRESS PARAMETER FUNCTION NUMBER OF BITS BIT POSITION F0H CF compression factor value will be (1 + cf/255) which results in a range from 1 to 2 8 7:0 F1H UV_CORING coring definition in U and V channels; see Table 5 2 1:0 UV_FILTER_TYPE notch filter selection in U and V channels (0 = 4 MHz; 1 = 2 MHz) 1 2 F2H PRE_ON luminance prefilter active 1 3 NOTCH_ON notch prefilter active 1 4 DTO_ON DTO control 1 5 SEL_DTO_RES select DTO reset (0 = WE; 1 = Href) 1 6 WEO_DEL_SEL select delay in WEO Y_VAR_DELAY luminance delay compression (see Table 5) 5 7:2 not used; load 0 1996 Jan 12 6 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage −0.3 6.5 V VDDA analog supply voltage −0.3 6.5 V VDDA − VDDD supply voltage difference −0.5 +0.5 V VI input voltage referenced to AGND − VDDA V Vclk(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VDDD V Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 +70 °C THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE UNIT 45 K/W HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. CHARACTERISTICS VDDA = VDDD = 4.75 to 5.25 V; VSSA and VSSD shorted together; VDDA − VDDD = −0.1 to +0.1 V (see note 1); Vref(H) = 2.38 V; fclk = 20 MHz with 50% duty cycle; 5.6 kΩ (5%) connected between Iref and VDDA; CL = 15 pF; Tamb = 0 to 70 °C; typical values measured at VDDA = VDDD = 5 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDA analog supply voltage 4.75 5.0 5.25 V VDDD digital supply voltage 4.75 5.0 5.25 V IDDA analog supply current − 55 63 mA IDDD digital supply current − 45 55 mA Digital inputs and clock input (WE, Href, CLAMP, MODE1, MODE0, SCCL, UPCL, UPDA and V50) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VDDD V CI input capacitance − 7 15 pF ILI input leakage current − +10 µA 1996 Jan 12 VI = 0 V; VDDD = 5 V −10 7 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface SYMBOL PARAMETER TDA8753A CONDITIONS MIN. TYP. MAX. UNIT Clamp and references [Iref, DECref(L) and Vref(H)] −4 Y − ACL clamping accuracy −1 − +1 LSB Cclamp serial clamp capacitor 10 22 − nF ZADC internal impedance between pin 29 and VSSA − 420 − Ω Vref(H) converter reference HIGH, applied to pin 29 − 2.38 − V VDECref(L) converter reference voltage LOW, applied to pin 28 − 0.39 − V U and V Vref(H) = 2.38 V +1 LSB Y analog input (INY); Vref(H) = 2.38 V, Vref(L) = 0.39 V; see Table 4 Vi(p-p) input voltage, full range (peak-to-peak value) ramp input − 1.26 − V Ii input current clamp non-active − 5 100 nA CI input capacitance − − 15 pF U,V analog inputs (INU and INV); Vref(H) = 2.38 V, Vref(L) = 0.39 V; see Table 4 Vi(p-p) input voltage (peak-to-peak value) ramp input − 1.26 − V Ii input current − 5 100 nA CI input capacitance − − 15 pF crosstalk between INY, INU and INV − − −50 dB clamp non-active Inputs isolation αact Digital outputs (Y0 to Y7, U1, U0, V1 and V0); see Table 3 VOL LOW level output voltage IOL = 1.6 mA 0 − 0.5 V VOH HIGH level output voltage IOH = 0.4 mA 2.4 − VDDD V note 2 − 1.5 − % Analog signal processing (fCLK = 20 MHz) Gdiff differential gain Φdiff differential phase note 2 − 1.0 − deg fall harmonics (full scale) all components note 3; Y − −53 − dB U and V − −55 − dB SVR supply voltage ripple rejection note 4 − 2 − %/V B bandwidth −1 dB; note 5 − 6 − MHz Transfer function (fclk = 16 MHz) INL integral non-linearity ramp input − ±0.75 − LSB DNL differential non-linearity ramp input; Y − ±0.5 ±0.75 LSB ramp input; U and V − ±0.6 ±0.9 LSB note 6; Y 41 44.5 − dB U and V 42 46 − dB SNR 1996 Jan 12 signal-to-noise ratio without harmonics 8 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface SYMBOL PARAMETER TDA8753A CONDITIONS MIN. TYP. MAX. UNIT Timing (fclk = 20 MHz; CL = 15 pF); see Figs 7 and 10; note 7 fclk maximum input clock frequency 20 − − MHz tCP(H) clock pulse width HIGH 22 − − ns tCP(L) clock pulse width LOW 22 − − ns tds sampling delay − 4 − ns thd output hold time 7 − − ns td output delay time − − 32 ns tCLKr clock rise time 3 5 − ns tCLKf clock fall time 3 5 − ns tsu;Href HREF set-up time 7 − − ns thd;Href HREF hold time 3 − − ns tr data output rise time − 10 − ns tf data output fall time − 10 − ns tCLP minimum time for active clamp pulse width 2.3 2.5 − µs tsu;WE WE set-up time 7 − − ns thd;WE WE hold time 3 − − ns tXLXL serial port clock cycle time 1 − − µs tQVXH output data set-up to rising edge of clock 700 − − ns tXHQH output data hold time after rising edge of clock 50 − − ns tW V50 pulse duration 2 − − ms tVC V50 to clock time 2 − − ms fxtal = 12 MHz Sample rate converter (fclk = 20 MHz) ΦY Y phase accuracy fiY = 0 to 5 MHz − ±1 − ns FUV UV phase accuracy fiUV = 0 to 1.5 MHz − ±4 − ns Yfr Y frequency response fiY = 0 to 5 MHz − ±0.5 − dB UVfr UV frequency response fiUV = 0 to 1.5 MHz − ±0.5 − dB Ystep Y step size − 1 − ns UVstep UV step size − 4 − ns 1996 Jan 12 9 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A Notes to the Characteristics 1. VDDA and VDDD should be supplied from the same power supply and decoupled separately. 2. Measurement carried out using video amplifier type VM700A, where the video analog signal (Y channel) is reconstructed via the DAC. 3. The input conditions are related as follows: Y − Vi(p-p) = 1.26 V, fi = 4.43 MHz U and V − Vi(p-p) = 1.26 V, fi = 1.5 MHz. 4. Supply voltage ripple rejection: SVR; relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V. SVR = [∆ (VI(0) − VI(255)]/[VI(o) − VI(255)]/∆VDDA. 5. The −1 dB bandwidth is the frequency value for which the analog reconstructed (glitch-free) output signal is compressed in term of number of codes, by −1 dB (respectively for −3 dB bandwidth). 6. The signal-to-noise ratio without harmonics is measured under a 16 MHz clock frequency. This value is given for a 4.43 MHz input frequency on the Y channel (1.5 MHz on the U and V channels). 7. Output data acquisition: Output data is available after the maximum delay of td. Table 2 Table 3 Mode selection MODE1 MODE0 0 0 MODE normal configuration Output data coding OUTPUT PORT BIT Y Y7 Y0 7 Y17 Y27 Y37 Y6 Y06 Y16 Y26 Y36 Y5 Y05 Y15 Y25 Y35 Y4 Y04 Y14 Y24 Y34 Y3 Y03 Y13 Y23 Y33 Y2 Y02 Y12 Y22 Y32 Y1 Y01 Y11 Y21 Y31 U V 1996 Jan 12 OUTPUT DATA Y0 Y00 Y10 Y20 Y30 U1 U07 U05 U03 U01 U0 U06 U04 U02 U00 V1 V07 V05 V03 V01 V0 V06 V04 V02 V00 10 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface Table 4 TDA8753A Internal ADC data coding as a function of the analog input STEP INPUT VOLTAGE INTERNAL BINARY OUTPUTS Underflow <0.26 00000000 0 0.26 00000000 1 - 00000001 .... .... ........ 16 0.34 00010000 .... .... ........ 128 0.89 10000000 .... .... ........ 254 − 11111110 255 1.52 11111111 Overflow >1.52 11111111 Table 5 REMARKS VDECref(L) /1.5 clamp level of Y channel clamp level of U and V channels Vref(H) − 0.1 V/1.5 Coring and luminance delay UV_CORING F1:1 F1:0 0 0 0 INTERNAL CORING CORRECTION IN U AND V CHANNELS (AROUND CODE 128 LEVEL) Y_VAR_DELAY INTERNAL DELAY FOR Y PATH AT PREFILTER INPUT (CLOCK PULSE) F2:1 F2:0 coring off 0 0 0 1 +1/−1 0 1 1 1 0 +1/−0 1 0 2 1 1 +2/−1 1 1 3 1996 Jan 12 11 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A t CPL 1/1 page = 296 mm (Datasheet) t CPH 27 mm 1.4 V CLK sample N sample N + 1 sample N + 2 Vl t dS t HD 2.4 V DATA D0 - D7 DATA N-D DATA N-D+1 DATA N-D+2 DATA N-D+2 1.4 V 0.4 V td MSB269 The value D is equal to 15. Fig.5 Timing diagram. TIMING handbook, full pagewidthdigital MSA645 output level 255 black-level clamping Y : 16 U,V : 128 0 time t CLP CLP Fig.6 Clamp control timing. 1996 Jan 12 12 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A handbook, full pagewidth CLK 1 2 3 15 WE output data valid t su t hd data MBE430 The output data is valid 15 clock periods after WE goes HIGH. Fig.7 Set-up and hold time definition; WE signal. K x 15 x periods handbook, full pagewidth CLK WE output data valid t su data MBE431 When the WE period is a whole multiple of 15 clock periods, the output data is valid without any clock delay. The internal circuit always gives an internal 15 clock period as illustrated in Fig.7. Fig.8 Timing diagram; WE signal. 1996 Jan 12 13 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A td handbook, full pagewidth V50 t XLXL UPCL t XHQX t QVXH MBE432 Fig.9 Timing of the asynchronous interface. handbook, full pagewidth CLK t hd WEO YUV outputs MBE428 Fig.10 Outputs hold time. 1996 Jan 12 14 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface handbook, full pagewidth TDA8753A CLK t su;X t hd;X MBE429 Fig.11 Digital inputs WE and HREF; set-up and hold time. INTERNAL PIN CONFIGURATION handbook, full pagewidth DIGITAL INPUTS DIGITAL OUTPUTS VDDD VDDD 1 to 8, 11 to 14, 17 16, 18 to 23, 40 to 42 VSSD VSSD ANALOG INPUTS VDDA I 27 29 32, 35, 38 30 I VSSA VSSA VSSA Fig.12 Internal pin configuration. 1996 Jan 12 I 15 MBE419 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A APPLICATION INFORMATION 5V 5V 1 42 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 10 33 5.6 µH 4.7 µF 22 nF Y 100 nF 5.6 µH 100 nF 11 4.7 µF TDA8753A 22 nF U 22 nF V 32 12 31 13 30 14 29 220 Ω 5V 22 nF 15 28 16 27 17 26 18 25 19 24 20 23 21 22 220 µF 220 Ω 5.6 kΩ 220 uF 22 nF 100 nF MBE433 Analog and digital supplies should be separated and decoupled. Test pins MODE1, MODE0 and MSCAN must be connected to digital ground. Fig.13 Application diagram. 1996 Jan 12 16 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A PACKAGE OUTLINE seating plane SDIP42: plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1 ME D A2 L A A1 c e Z b1 (e 1) w M MH b 22 42 pin 1 index E 1 21 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.08 0.51 4.0 1.3 0.8 0.53 0.40 0.32 0.23 38.9 38.4 14.0 13.7 1.778 15.24 3.2 2.9 15.80 15.24 17.15 15.90 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-02-13 95-02-04 SOT270-1 1996 Jan 12 EUROPEAN PROJECTION 17 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Jan 12 18 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A NOTES 1996 Jan 12 19 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. 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(02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 © Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1100/02/pp20 Document order number: Date of release: 1996 Jan 12 9397 750 00564