74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state Rev. 09 — 18 March 2010 Product data sheet 1. General description The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with 3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels High-impedance when VCC = 0 V All data inputs have bus hold. (74LVCH16244A only) Complies with JEDEC standard JESD8-B / JESD36 ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from −40 °C to +85 °C and −40 °C to +125 °C 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 3. Ordering information Table 1. Ordering information Type number 74LVC16244ADL Temperature range Package Name Description Version −40 °C to +125 °C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 −40 °C to +125 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 −40 °C to +125 °C VFBGA56 plastic very thin fine-pitch ball grid array package; SOT702-1 56 balls; body 4.5 × 7 × 0.65 mm −40 °C to +125 °C HXQFN60U plastic thermal enhanced extremely thin quad flat SOT1134-1 package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm 74LVCH16244ADL 74LVC16244ADGG 74LVCH16244ADGG 74LVC16244AEV 74LVCH16244AEV 74LVC16244ABQ 74LVCH16244ABQ 4. Functional diagram 47 46 44 43 1A0 1Y0 1A1 1Y1 1A2 1Y2 1A3 1Y3 2 36 3 35 5 33 6 32 3A0 3Y0 3A1 3Y1 3A2 3Y2 3A3 3Y3 1 1OE 48 2OE 25 3OE 24 4OE 13 14 16 1A0 1A1 17 1A2 1A3 1 1OE 25 3OE 2A0 2A1 41 2A0 2Y0 8 30 4A0 4Y0 2A2 19 2A3 40 2A1 2Y1 9 29 4A1 4Y1 3A0 20 3A1 38 37 48 2A2 2A3 2Y2 2Y3 2OE 11 12 27 26 24 4A2 4A3 4Y2 4Y3 3A2 22 3A3 4A0 23 4A1 4A2 4OE 4A3 EN1 EN2 EN3 EN4 47 46 Fig 1. Logic symbol 74LVC_LVCH16244A_9 Product data sheet 1 2 3 44 5 43 6 41 40 1 2 8 9 38 11 37 12 36 35 1 3 13 14 33 16 32 17 30 29 1 4 19 20 27 22 26 23 001aae506 Pin numbers are shown for SSOP48 and TSSOP48 packages only. 1 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3 001aae231 Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 2 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state VCC data input to internal circuit mna705 Fig 3. Bus hold circuit 5. Pinning information 5.1 Pinning 1OE 1 48 2OE 1Y0 2 47 1A0 1Y1 3 46 1A1 GND 4 45 GND 1Y2 5 44 1A2 1Y3 6 43 1A3 VCC 7 42 VCC 2Y0 8 41 2A0 2Y1 9 40 2A1 GND 10 39 GND 2Y2 11 38 2A2 2Y3 12 3Y0 13 37 2A3 74LVC16244A 74LVCH16244A 36 3A0 3Y1 14 35 3A1 GND 15 34 GND 3Y2 16 33 3A2 3Y3 17 32 3A3 VCC 18 31 VCC 4Y0 19 30 4A0 4Y1 20 29 4A1 GND 21 28 GND 4Y2 22 27 4A2 4Y3 23 26 4A3 4OE 24 74LVC16244A ball A1 74LVCH16244A index area 1 2 3 4 5 6 A B C D E F G H J K 25 3OE 001aaj053 Transparent top view 001aaj052 Fig 4. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) 74LVC_LVCH16244A_9 Product data sheet Fig 5. Pin configuration SOT702-1 (VFBGA56) All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 3 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state terminal 1 index area D1 A32 A1 D5 A31 A30 B20 A29 B19 A28 B18 A27 D4 D8 A26 A2 A25 B1 B17 B2 B16 A3 A24 A4 A23 B15 B3 A5 A22 74LVC16244A 74LVCH16244A B4 A6 B14 A21 B5 B13 B6 B12 A7 A20 A8 A19 B7 B11 GND(1) A9 A10 D6 D2 A11 B9 B8 A12 A13 A18 B10 A14 A15 D7 A17 A16 D3 001aaj054 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 6. Pin configuration SOT1134-1 (HXQFN60U) 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 4 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description SOT370-1 and SOT362-1 SOT702-1 SOT1134-1 1, 48, 25, 24 A1, A6, K6, K1 A30, A29, A14, A13 output enable input (active LOW) 1Y0 to 1Y3 2, 3, 5, 6 B2, B1, C2, C1 B20, A31, D5, D1 data output 2Y0 to 2Y3 8, 9, 11, 12 D2, D1, E2, E1 A2, B2, B3, A5 data output 1OE, 2OE, 3OE, 4OE 3Y0 to 3Y3 13, 14, 16, 17 F1, F2, G1, G2 A6, B5, B6, A9 data output 4Y0 to 4Y3 19, 20, 22, 23 H1, H2, J1, J2 D2, D6, A12, B8 data output GND 4, 10, 15, 21, 28, 34, 39, 45 B3, B4, D3, D4, G3, G4, J3, J4 A32, A3, A8, A11, A16, A19, A24, A27 ground (0 V) VCC 7, 18, 31, 42 C3, C4, H3, H4 A1, A10, A17, A26 supply voltage 1A0 to 1A3 47, 46, 44, 43 B5, B6, C5, C6 B18, A28, D8, D4 data input 2A0 to 2A3 41, 40, 38, 37 D5, D6, E5, E6 A25, B16, B15, A22 data input 3A0 to 3A3 36, 35, 33, 32 F6, F5, G6, G5 A21, B13, B12, A18 data input 4A0 to 4A3 30, 29, 27, 26 H6, H5, J6, J5 D3, D7, A15, B10 data input n.c. A2, A3, A4, A5, K2, K3, K4, K5 A4, A7, A20, A23, B1, B4, B7, B9, B11, B14, B17, B19 not connected - 6. Functional description Table 3. Function table[1] Control Input Output nOE nAn nYn L L L L H H H X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 5 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] Max Unit −0.5 +6.5 V −50 - mA −0.5 +6.5 V - ±50 mA output HIGH or LOW [2] −0.5 VCC + 0.5 V output 3-state [2] −0.5 +6.5 V - ±50 mA VO > VCC or VO < 0 V output voltage VO Min IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C; (T)SSOP48 package [3] - 500 mW VFBGA56 package [4] - 1000 mW HXQFN60U package [4] - 1000 mW [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. [4] Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage maximum speed performance 2.7 - 3.6 V functional 1.2 - 3.6 V 0 - 5.5 V VI input voltage VO output voltage output HIGH or LOW 0 - VCC V output 3-state 0 - 5.5 V Tamb ambient temperature in free air −40 - +125 °C Δt/ΔV input transition rise and fall rate VCC = 1.2 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 6 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max HIGH-level input voltage VCC = 1.2 V VCC - - VCC - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V LOW-level input voltage VCC = 1.2 V - - 0 - 0 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC − 0.2 VCC - VCC − 0.3 - V IO = −12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = −18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = −24 mA; VCC = 3.0 V 2.2 - - 2.0 - V - 0 0.20 - 0.3 V - - 0.40 - 0.6 V HIGH-level output VI = VIH or VIL voltage IO = −100 μA; VCC = 2.7 V to 3.6 V LOW-level output VI = VIH or VIL voltage IO = 100 μA; VCC = 2.7 V to 3.6 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V [2] - ±0.1 ±5 - ±20 μA [2][3] - ±0.1 ±5 - ±20 μA II input leakage current VI = 5.5 V or GND; VCC = 3.6 V IOZ OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V IOFF power-off leakage VI or VO = 5.5 V; VCC = 0.0 V current - ±0.1 ±10 - ±20 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - 0.1 20 - 80 μA ΔICC additional supply current per input pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V - 5 500 - 5000 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF IBHL bus hold LOW current VCC = 3.0 V; VI = 0.8 V [4][5] 75 - - 60 - μA IBHH bus hold HIGH current VCC = 3.0 V; VI = 2.0 V [4][5] −75 - - −60 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V [4][6] 500 - - 500 - μA 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 7 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHHO −40 °C to +85 °C Conditions bus hold HIGH overdrive current [4][6] VCC = 3.6 V −40 °C to +125 °C Unit Min Typ[1] Max Min Max −500 - - −500 - [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. [3] For I/O ports the parameter IOZ includes the input leakage current. [4] Valid for data inputs of bus hold parts only (74LVCH16244A). Note that control inputs do not have a bus hold circuit. [5] The specified sustaining current at the data input holds the input below the specified VI level. [6] The specified overdrive current at the data input forces the data input to the opposite input state. μA 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tpd propagation delay −40 °C to +85 °C Conditions nAn to nYn; see Figure 7 Min Typ Max Min Max - 11.0 - - - ns 1.0 - 4.7 1.0 6.0 ns 1.1 3.0 4.1 1.1 5.5 ns - 15.0 - - - ns 1.0 - 5.8 1.0 7.5 ns 1.0 3.5 4.6 1.0 6.0 ns - 10.0 - - - ns 1.0 - 6.2 1.0 8.0 ns 1.8 3.7 5.2 1.8 6.5 ns [1] VCC = 1.2 V VCC = 2.7 V ten enable time VCC = 3.0 V to 3.6 V [2] nOE to nYn; see Figure 8 [1] VCC = 1.2 V VCC = 2.7 V tdis disable time VCC = 3.0 V to 3.6 V [2] nOE to nYn; see Figure 8 [1] VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V 74LVC_LVCH16244A_9 Product data sheet −40 °C to +125 °C Unit [2] All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 8 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter −40 °C to +85 °C Conditions Min CPD [1] power dissipation capacitance per buffer; VI = GND to VCC; VCC = 3.3 V Typ Max −40 °C to +125 °C Unit Min Max [3] outputs enabled - 12 - - - pF outputs disabled - 4.0 - - - pF tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [2] Typical values are measured at Tamb = 25 °C and VCC = 3.3 V. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs. 11. Waveforms VI nAn input VM VM GND tPLH tPHL VOH nYn output VM VOL VM mna171 Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The input (nAn) to output (nYn) propagation delays 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 9 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs enabled outputs disabled mna362 Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 8. 3-state enable and disable times. Measurement points Supply voltage Input VCC VI VM VM VX VY 1.2 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.1 V VOH − 0.1 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74LVC_LVCH16244A_9 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 10 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 9. Load circuit for measuring switching times Test data Supply voltage Input VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2.5 ns 50 pF 500 Ω[1] open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND [1] Load VEXT The circuit performs better when RL = 1 kΩ. 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 11 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) θ pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Fig 10. Package outline SOT370-1 (SSOP48) 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 12 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 11. Package outline SOT362-1 (TSSOP48) 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 13 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm B D SOT702-1 A ball A1 index area A2 A E A1 detail X e1 1/2 C ∅v M C A B ∅w M C b e y1 C e y K J H e G F e2 E D 1/2 e C X B A ball A1 index area 1 2 3 4 5 6 DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1 0.3 0.2 0.7 0.6 0.45 0.35 4.6 4.4 7.1 6.9 0.65 3.25 5.85 0.15 0.08 0.08 0.1 OUTLINE VERSION SOT702-1 REFERENCES IEC JEDEC JEITA 0 2.5 5 mm scale EUROPEAN PROJECTION ISSUE DATE 02-08-08 03-07-01 MO-225 Fig 12. Package outline SOT702-1 (VFBGA56) 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 14 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm B D SOT1134-1 A terminal 1 index area E A A1 detail X e2 e1 1/2 e e C A B C v w L1 D2 D6 A11 eR y D7 B10 A10 L y1 C D3 A16 B8 C C A B C v w b A17 e B11 B7 e3 Eh e4 1/2 e B1 B17 A1 terminal 1 index area A26 D5 D1 B20 B18 A32 D8 A27 X D4 Dh k 0 2.5 Dimensions Unit mm 5 mm scale A A1 b max 0.50 0.05 0.35 nom 0.48 0.02 0.30 min 0.46 0.00 0.25 D Dh E Eh e e1 e2 e3 e4 eR 4.1 4.0 3.9 1.90 1.85 1.80 6.1 6.0 5.9 3.90 3.85 3.80 0.5 1 2.5 3 4.5 0.5 k L 0.25 0.35 0.20 0.30 0.15 0.25 L1 0.125 0.075 0.025 v w y 0.07 0.05 0.08 y1 0.1 sot1134-1_po References Outline version IEC JEDEC JEITA SOT1134-1 --- --- --- European projection Issue date 08-12-17 09-01-22 Fig 13. Package outline SOT1134-1 (HXQFN60U) 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 15 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC_LVCH16244A_9 20100318 Product data sheet - 74LVC_LVCH16244A_8 • Modifications: 74LVC16244ABQ and 74LVCH16244ABQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package. 74LVC_LVCH16244A_8 20081117 Product data sheet - 74LVC_LVCH16244A_7 74LVC_LVCH16244A_7 20031208 Product specification - 74LVC_LVCH16244A_6 74LVC_LVCH16244A_6 20030130 Product specification - 74LVC_LVCH16244A_5 74LVC_LVCH16244A_5 20021030 Product specification - 74LVC_H16244A_4 74LVC_H16244A_4 19971028 Product specification - 74LVC16244A_ 74LVCH16244A_3 74LVC16244A_ 74LVCH16244A_3 19971028 Product specification - 74LVC16244A_2 74LVC16244A_2 19970630 Product specification - 74LVC16244A_1 74LVC16244A_1 - - - - 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 16 of 19 74LVC16244A; 74LVCH16244A NXP Semiconductors 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVC_LVCH16244A_9 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 17 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC_LVCH16244A_9 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 09 — 18 March 2010 © NXP B.V. 2010. All rights reserved. 18 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 18 March 2010 Document identifier: 74LVC_LVCH16244A_9