ADC1410S series Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 03 — 12 April 2010 Preliminary data sheet 1. General description The ADC1410S is a single-channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1410S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, because of a separate digital output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1410S is ideal for use in communications, imaging and medical applications. 2. Features and benefits SNR, 72 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps 14-bit pipelined ADC core Clock input divider by 2 for less jitter contribution Single 3 V supply Flexible input voltage range: 1 V to 2 V (peak-to-peak). CMOS or LVDS DDR digital outputs Pin compatible with the ADC1210S series and the ADC1010S series HVQFN40 package Input bandwidth, 600 MHz Power dissipation, 430 mW at 80 Msps Serial Peripheral Interface (SPI) Duty cycle stabilizer Fast OuT of Range (OTR) detection INL ±1.5 LSB, DNL ±0.5 LSB Offset binary, two’s complement, gray code Power-down and Sleep modes 3. Applications Wireless and wired broadband communications Spectral analysis Ultrasound equipment Portable instrumentation Imaging systems Software define radio ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 4. Ordering information Table 1. Ordering information Type number fs (Msps) Package Name Description Version ADC1410S125HN/C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-6 ADC1410S105HN/C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-6 ADC1410S080HN/C1 80 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-6 ADC1410S065HN/C1 65 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-6 5. Block diagram SDIO/ODS SCLK/DFS CS ADC1410S ERROR CORRECTION AND DIGITAL PROCESSING SPI INTERFACE OTR INP T/H INPUT STAGE ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS INM OUTPUT DRIVERS CLOCK INPUT STAGE AND DUTY CYCLE CONTROL CLKP CLKM SYSTEM REFERENCE AND POWER MANAGEMENT CMOS: D13 to D0 or LVDS/DDR: D13_M to D0_M D13_P to D0_P CMOS: DAV or LVDS/DDR: DAVP DAVM PWD OE VCM SENSE REFT VREF REFB 005aaa036 Fig 1. Block diagram ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 2 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 6. Pinning information 5 AGND 6 INM 7 INP 8 23 D7 AGND 9 22 D8 VDDA 10 21 D9 26 D4 D10 20 D11 19 D12 18 D13 17 PWD 16 OE 15 DEC 14 CLKM 13 CLKP 12 VDDA 11 31 DAVM 32 DAVP 33 VDDO INM 7 24 D6_D7_P INP 8 23 D6_D7_M AGND 9 22 D8_D9_P VDDA 10 21 D8_D9_M 005aaa037 Transparent top view Fig 2. 34 OGND 6 25 D5 24 D6 35 OTR AGND 27 D2_D3_M 26 D4_D5_P ADC1410S HVQFN40 25 D4_D5_M D10_D11_P 20 VDDA 36 SCLK/DFS 5 D10_D11_M 19 27 D3 37 SDIO/ODS VDDA D12_D13_P 18 4 38 CS 4 D12_D13_M 17 VCM 39 SENSE 28 D2_D3_P VCM 28 D2 ADC1410S HVQFN40 40 VREF 31 DAV 32 n.c. 33 VDDO 34 OGND 35 OTR 36 SCLK/DFS 37 SDIO/ODS 3 PWD 16 3 29 D0_D1_M AGND OE 15 AGND 29 D1 30 D0_D1_P 2 DEC 14 2 1 REFT CLKM 13 REFT 30 D0 REFB CLKP 12 1 terminal 1 index area VDDA 11 REFB 38 CS terminal 1 index area 39 SENSE 40 VREF 6.1 Pinning 005aaa038 Transparent top view Pin configuration with CMOS digital outputs selected Fig 3. Pin configuration with LVDS/DDR digital outputs selected 6.2 Pin description Table 2. ADC1410S_SER_3 Preliminary data sheet Pin description (CMOS digital outputs) Symbol Pin Type [1] Description REFB 1 O bottom reference REFT 2 O top reference AGND 3 G analog ground VCM 4 O common-mode output voltage VDDA 5 P analog power supply AGND 6 G analog ground INM 7 I complementary analog input INP 8 I analog input AGND 9 G analog ground VDDA 10 P analog power supply VDDA 11 P analog power supply CLKP 12 I clock input CLKM 13 I complementary clock input DEC 14 O regulator decoupling node OE 15 I output enable, active LOW PWD 16 I power down, active HIGH All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 3 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 2. Pin description (CMOS digital outputs) …continued Symbol Pin Type [1] Description D13 17 O data output bit 13 (MSB) D12 18 O data output bit 12 D11 19 O data output bit 11 D10 20 O data output bit 10 D9 21 O data output bit 9 D8 22 O data output bit 8 D7 23 O data output bit 7 D6 24 O data output bit 6 D5 25 O data output bit 5 D4 26 O data output bit 4 D3 27 O data output bit 3 D2 28 O data output bit 2 D1 29 O data output bit 1 D0 30 O data output bit 0 (LSB) DAV 31 O data valid output clock n.c. 32 - not connected VDDO 33 P output power supply OGND 34 G output ground OTR 35 O out of range SCLK/DFS 36 I SPI clock data format select SDIO/ODS 37 I/O SPI data IO output data standard CS 38 I SPI chip select SENSE 39 I reference programming pin VREF 40 I/O voltage reference input/output [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. ADC1410S_SER_3 Preliminary data sheet Pin description (LVDS/DDR) digital outputs) Symbol Pin [1] Type [2] Description D12_D13_M 17 O differential output data D12 and D13 multiplexed, complement D12_D13_P 18 O differential output data D12 and D13 multiplexed, true D10_D11_M 19 O differential output data D10 and D11 multiplexed, complement D10_D11_P 20 O differential output data D10 and D11 multiplexed, true D8_D9_M 21 O differential output data D8 and D9 multiplexed, complement D8_D9_P 22 O differential output data D8 and D9 multiplexed, true D6_D7_M 23 O differential output data D6 and D7 multiplexed, complement D6_D7_P 24 O differential output data D6 and D7 multiplexed, true D4_D5_M 25 O differential output data D4 and D5 multiplexed, complement D4_D5_P 26 O differential output data D4 and D5 multiplexed, true D2_D3_M 27 O differential output data D2 and D3 multiplexed, complement D2_D3_P 28 O differential output data D2 and D3 multiplexed, true D0_D1_M 29 O differential output data D0 and D1 multiplexed, complement All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 4 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 3. Pin description (LVDS/DDR) digital outputs) …continued Symbol Pin [1] Type [2] Description D0_D1_P 30 O differential output data D0 and D1 multiplexed, true DAVM 31 O data valid output clock, complement DAVP 32 O data valid output clock, true [1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2) [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VO output voltage pins D13 to D0 or pins D13P to D0P and D13M to D0M −0.4 +3.9 V VDDA analog supply voltage −0.4 +3.9 V VDDO output supply voltage −0.4 +3.9 V Tstg storage temperature −55 +125 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 125 °C 8. Thermal characteristics Table 5. Symbol Preliminary data sheet Parameter Conditions Rth(j-a) thermal resistance from junction to ambient [1] Rth(j-c) thermal resistance from junction to case [1] [1] ADC1410S_SER_3 Thermal characteristics Typ Unit 22.5 K/W 11.7 K/W Value for six layers board in still air with a minimum of 25 thermal vias. All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 5 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 9. Static characteristics Table 6. Symbol Static characteristics[1] Parameter Conditions Min Typ Max Unit 2.85 3.0 3.4 V Supplies VDDA analog supply voltage VDDO output supply voltage CMOS mode 1.65 1.8 3.6 V LVDS DDR mode 2.85 3.0 3.6 V IDDA analog supply current fclk = 125 Msps; fi =70 MHz - 210 - mA IDDO output supply current CMOS mode; fclk = 125 Msps; fi =70 MHz - 14 - mA LVDS DDR mode: fclk = 125 Msps; fi =70 MHz - 43 - mA ADC1410S125; analog supply only - 630 - mW ADC1410S105; analog supply only - 550 - mW ADC1410S080; analog supply only - 430 - mW ADC1410S065; analog supply only - 380 - mW power-down mode - 2 - mW sleep mode - 40 - mW differential clock input voltage peak-to-peak - ±0.8 - V differential clock input voltage peak-to-peak - ±0.70 - V differential clock input voltage peak-to-peak ±0.8 ±3.0 - V P power dissipation Clock inputs: pins CLKP and CLKM LVPECL Vi(clk)dif LVDS Vi(clk)dif SINE wave Vi(clk)dif LVCMOS VIL LOW-level input voltage - - 0.3VDDA V VIH HIGH-level input voltage 0.7VDDA - - V Logic inputs: pins PWD and OE VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2 - VDDA V IIL LOW-level input current <tbd> - <tbd> μA IIH HIGH-level input current −10 - +10 μA Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS VIL LOW-level input voltage 0 - 0.3VDDA V VIH HIGH-level input voltage 0.7VDDA - VDDA V IIL LOW-level input current −10 - +10 μA IIH HIGH-level input current −50 - +50 μA CI input capacitance - 4 - pF ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 6 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 6. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit 0.2VDDO V Digital outputs: CMOS mode - pins D13 to D0, OTR, DAV Output levels, VDDO = 3 V VOL LOW-level output voltage IOL = <tbd> OGND - VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO - VDDO V IOL LOW-level output current 3-state; output level = 0 V - <tbd> - μA IOH HIGH-level output current 3-state; output level = VDDA - <tbd> - μA CO output capacitance high impedance; OE = HIGH - 3 - pF Output levels, VDDO = 1.8 V VOL LOW-level output voltage IOL = <tbd> OGND - 0.2VDDO V VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO - VDDO V Digital outputs, LVDS mode - pins D13P to D0P, D13M to D0M, DAVP and DAVM Output levels, VDDO = 3 V only, RL = 100 Ω VO(offset) output offset voltage output buffer current set to 3.5 mA - 1.2 - V VO(dif) differential output voltage output buffer current set to 3.5 mA - 350 - mV CO output capacitance - <tbd> - pF −5 - +5 μA Analog inputs: pins INP and INM II input current RI input resistance - <tbd> - Ω CI input capacitance - 5 - pF VI(cm) common-mode input voltage 0.9 1.5 2 V Bi input bandwidth - 600 - MHz VI(dif) differential input voltage 1 2 V VINP = VINM peak-to-peak Common mode output voltage: pin VCM VO(cm) common-mode output voltage - VDDA / 2 - V IO(cm) common-mode output current - <tbd> - μA output 0.5 - 1 V input 0.5 - 1 V −5 ±1 +5 LSB −0.95 ±0.5 +0.95 LSB - ±2 - mV I/O reference voltage: pin VREF VVREF voltage on pin VREF Accuracy INL integral non-linearity DNL differential non-linearity Eoffset offset error EG gain error full-scale power supply rejection ratio 100 mV (p-p) on VDDA guaranteed no missing codes ±0.5 % Supply PSRR [1] - 35 - dBc Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 7 of 37 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors ADC1410S_SER_3 Preliminary data sheet 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Symbol Dynamic characteristics[1] Parameter Conditions ADC1410S065 Min Typ ADC1410S080 Max Min Typ ADC1410S105 Max Min Typ ADC1410S125 Max Min Typ Unit Max Analog signal processing α2H THD ENOB 8 of 37 © NXP B.V. 2010. All rights reserved. SFDR total harmonic distortion 87 - - 87 - - 86 - - 88 - dBc - 86 - - 86 - - 86 - - 87 - dBc fi = 70 MHz - 85 - - 85 - - 84 - - 85 - dBc fi = 170 MHz - 82 - - 82 - - 81 - - 83 - dBc fi = 3 MHz - 86 - - 86 - - 85 - - 87 - dBc fi = 30 MHz - 85 - - 85 - - 85 - - 86 - dBc fi = 70 MHz - 84 - - 84 - - 83 - - 84 - dBc fi = 170 MHz - 81 - - 81 - - 80 - - 82 - dBc fi = 3 MHz - 85 - - 85 - - 84 - - 86 - dBc fi = 30 MHz - 84 - - 84 - - 84 - - 85 - dBc fi = 70 MHz - 83 - - 83 - - 82 - - 83 - dBc fi = 170 MHz - 80 - - 80 - - 79 - - 81 - dBc effective number fi = 3 MHz of bits fi = 30 MHz - 11.7 - - 11.7 - - 11.6 - - 11.6 - bits - 11.6 - - 11.5 - - 11.5 - - 11.5 - bits fi = 70 MHz - 11.5 - - 11.5 - - 11.4 - - 11.4 - bits fi = 170 MHz - 11.4 - - 11.4 - - 11.3 - - 11.3 - bits fi = 3 MHz - 72.1 - - 72.0 - - 71.8 - - 71.4 - dBFS fi = 30 MHz - 71.3 - - 71.2 - - 71.8 - - 71.4 - dBFS signal-to-noise ratio spurious-free dynamic range fi = 70 MHz - 70.7 - - 70.7 - - 70.6 - - 70.5 - dBFS fi = 170 MHz - 70.2 - - 70.1 - - 70.0 - - 69.9 - dBFS fi = 3 MHz - 86 - - 86 - - 85 - - 87 - dBc fi = 30 MHz - 85 - - 85 - - 85 - - 86 - dBc fi = 70 MHz - 84 - - 84 - - 83 - - 84 - dBc fi = 170 MHz - 81 - - 81 - - 80 - - 82 - dBc ADC1410S series SNR third harmonic level - ADC1410S series; CMOS or LVDS DDR digital output Rev. 03 — 12 April 2010 All information provided in this document is subject to legal disclaimers. α3H second harmonic fi = 3 MHz level fi = 30 MHz xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Symbol Dynamic characteristics[1] …continued Parameter Conditions ADC1410S065 Min IMD [1] Intermodulation distortion Typ ADC1410S080 Max Min Typ ADC1410S105 Max Min Typ ADC1410S125 Max Min Typ NXP Semiconductors ADC1410S_SER_3 Preliminary data sheet Table 7. Unit Max fi = 3 MHz - 89 - - 89 - - 88 - - 89 - dBc fi = 30 MHz - 88 - - 88 - - 88 - - 88 - dBc fi = 70 MHz - 87 - - 87 - - 86 - - 86 - dBc fi = 170 MHz - 84 - - 85 - - 83 - - 84 - dBc Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1410S series 9 of 37 © NXP B.V. 2010. All rights reserved. ADC1410S series; CMOS or LVDS DDR digital output Rev. 03 — 12 April 2010 All information provided in this document is subject to legal disclaimers. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 8. Symbol NXP Semiconductors ADC1410S_SER_3 Preliminary data sheet 10.2 Clock and digital output timing Clock and digital output timing characteristics[1] Parameter Conditions ADC1410S065 Min Typ ADC1410S080 Max Min Typ ADC1410S105 Max Min Typ ADC1410S125 Max Min Typ Unit Max Clock timing input: pins CLKP and CLKM fclk clock frequency 20 tlat(data) data latency time δclk clock duty cycle DCS_EN = 1 30 50 70 30 50 70 30 50 70 30 50 70 % DCS_EN = 0 45 50 55 45 50 55 45 50 55 45 50 55 % clock cycles - - 14 65 60 - - 14 80 75 - - 14 105 100 - 125 MHz - - 14 - clock cycle sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns twake wake-up time - <tbd> - - <tbd> - - <tbd> - - <tbd> - ns CMOS Mode Timing output: pins D13 to D0 and DAV tPD propagation delay DATA - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns DAV - 4.2 - - 4.2 - - 4.2 - - 4.2 - ns tsu set-up time - 7.7 - - 6.5 - - 4.7 - - 4.3 - ns th hold time - 6.7 - - 5.5 - - 3.8 - - 3.5 - ns tr rise time[2] DATA 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns DAV 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns DATA 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns tf fall time[2] LVDS DDR mode timing output: pins D13P to D0P, D13M to D0M, DAVP and DAVM propagation delay DATA - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns DAV - 4.2 - - 4.2 - - 4.2 - - 4.2 - ns 10 of 37 © NXP B.V. 2010. All rights reserved. tsu set-up time - 5.1 - - 3.5 - - 2.1 - - 1.4 - ns th hold time - 2.0 - - 2.0 - - 2.0 - - 2.0 - ns tr rise time[3] DATA 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns DAV 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns DATA 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns tf fall time[3] [1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. [2] Measured between 20 % to 80 % of VDDO. [3] Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV. ADC1410S series tPD ADC1410S series; CMOS or LVDS DDR digital output Rev. 03 — 12 April 2010 All information provided in this document is subject to legal disclaimers. td(s) ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tsu tPD th DAV tclk 005aaa060 Fig 4. CMOS mode timing N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) Dx_Dx + 1_P Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx_Dx + 1_M tsu th tsu th tPD DAVP DAVM tclk Fig 5. ADC1410S_SER_3 Preliminary data sheet 005aaa061 LDVS DDR mode timing All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 11 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 10.3 SPI timings Table 9. SPI timings characteristics[1] Symbol Parameter tw(SCLK) Conditions Min Typ Max Unit SCLK pulse width 40 - - ns tw(SCLKH) SCLK HIGH pulse width 16 - - ns tw(SCLKL) SCLK LOW pulse width tsu set-up time th hold time fclk(max) maximum clock frequency 16 - - ns data to SCLK HIGH 5 - - ns CS to SCLK HIGH 5 - - ns data to SCLK HIGH 2 - - ns CS to SCLK HIGH [1] 2 - - ns - - 25 MHz Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V tsu tsu th CS tw(SCLKL) th tw(SCLKH) tw(SCLK) SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 6. ADC1410S_SER_3 Preliminary data sheet SPI timing All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 12 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 11. Application information 11.1 Device control The ADC1410S can be controlled via SPI or directly via the I/O pins (PIN control mode). 11.1.1 SPI and PIN control modes The device enters PIN control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In PIN control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device will remain in this mode. The transition from PIN control mode to SPI control mode is illustrated in Figure 7. CS Pin control mode SCLK/DFS Data format two's complement SDIO/ODS SPI control mode Data format offset binary LVDS DDR CMOS R/W W1 W0 A12 005aaa039 Fig 7. Control mode selection When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO as soon as a transition is triggered by a falling edge on CS. 11.1.2 Operating mode selection The active ADC1410S operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 20) or using pins PWD and OE in PIN control mode, as described in Table 10. Table 10. Operating mode selection via pin PWD and OE Pin PWD Pin OE Operating mode Output high-Z 0 0 Power-up no 0 1 Power-up yes 1 0 Sleep yes 1 1 Power-down yes 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 23) or using pin ODS in PIN control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 13 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 23) or using pin DFS in PIN control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1410S supports differential or single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INP and INM set to 0.5VDDA. The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 22 further details). The equivalent circuit of the sample and hold input stage, including Electrostatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 8. Package ESD Parasitics Switch Ron = 15 Ω 8 INP Internal clock 4 pF Sampling capacitor Switch INM Ron = 15 Ω 7 Internal clock 4 pF Sampling capacitor 005aaa043 Fig 8. Input sampling circuit The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 14 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 11.2.2 Anti-kickback circuitry Anti-kickback circuitry (R-C filter in Figure 9) is needed to counteract the effects of a charge injection generated by the sampling capacitance. The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. R INP C R INM 005aaa073 Fig 9. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. RC coupling versus input frequency, typical values Input frequency Resistance Capacitance 3 MHz 25 Ω 12 pF 70 MHz 12 Ω 8 pF 170 MHz 12 Ω 8 pF 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 10 would be suitable for a baseband application. ADT1-1WT 100 nF Analog input 25 Ω 100 nF INP 25 Ω 12 pF 100 nF 100 nF 25 Ω 25 Ω INM VCM 100 nF 100 nF 005aaa044 Fig 10. Single transformer configuration suitable for baseband applications ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 15 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output The configuration shown in Figure 11 is recommended for high frequency applications. In both cases, the choice of transformer will be a compromise between cost and performance. ADT1-1WT Analog input 100 nF ADT1-1WT 50 Ω 12 Ω INP 50 Ω 8.2 pF 50 Ω 100 nF 50 Ω 12 Ω INM VCM 100 nF 100 nF 005aaa045 Fig 11. Dual transformer configuration suitable for high intermediate frequency application 11.3 System reference and power management 11.3.1 Internal/external references The ADC1410S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and −6 dB via control bits INTREF[2:0] when bit INTREF_EN = 1; see Table 22). See Figure 13, Figure 14, Figure 15, Figure 16. The equivalent reference circuit is shown in Figure 12. External reference is also possible by providing a voltage on pin VREF as described in Figure 15. ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 16 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output REFT REFERENCE AMP REFB VREF EXT_ref EXT_ref BUFFER BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 005aaa164 Fig 12. Reference equivalent schematic If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or externally as detailed in Table 12. Table 12. Selection SPI bit INTREF_EN SENSE pin VREF pin full-scale (p-p) internal (Figure 13) 0 AGND 330 pF capacitor to AGND 2V internal (Figure 14) 0 pin VREF connected to pin SENSE and via 1 V a 330 pF capacitor to AGND external (Figure 15) 0 VDDA internal via SPI (Figure 16) 1 pin VREF connected to pin SENSE and via 1 V to 2 V 330 pF capacitor to AGND [1] ADC1410S_SER_3 Preliminary data sheet Reference selection external voltage between 0.5 V and 1 V[1] 1 V to 2 V The voltage on pin VREF is doubled internally to generate the internal reference voltage. All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 17 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output VREF VREF 330 pF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa116 005aaa117 Fig 13. Internal reference, 2 V (p-p) full-scale Fig 14. Internal reference, 1 V (p-p) full-scale VREF VREF V 0.1 μF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE VDDA 005aaa119 005aaa118 Fig 15. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 16. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale Figure 13 to Figure 16 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. 11.3.2 Reference gain control The reference gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see Table 22). The corresponding full-scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 13: Table 13. ADC1410S_SER_3 Preliminary data sheet Reference SPI gain control INTREF[2:0] Gain (dB) Full-scale (V (p-p)) 000 0 dB 2V 001 −1 dB 1.78 V 010 −2 dB 1.59 V 011 −3 dB 1.42 V 100 −4 dB 1.26 V 101 −5 dB 1.12 V 110 −6 dB 1V 111 reserved x All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 18 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 μF filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. PACKAGE ESD PARASITICS COMMON MODE REFERENCE 1.5 V VCM 0.1 μF ADC CORE 005aaa051 Fig 17. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V. 11.4 Clock input 11.4.1 Drive modes The ADC1410S can be driven differentially (SINE, LVPECL or LVDS) with little or no degradation on dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor). LVCMOS clock input CLKP CLKP CLKM LVCMOS clock input 005aaa174 a. Rising edge LVCMOS CLKM 005aaa053 b. Falling edge LVCMOS Fig 18. LVCMOS single-ended clock input ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 19 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Sine clock input CLKP Sine clock input CLKP CLKM CLKM 005aaa054 005aaa173 a. Sine clock input b. Sine clock input (with transformer) CLKP CLKP LVPECL clock input LVDS clock input CLKM CLKM 005aaa172 005aaa055 c. LVDS clock input d. LVPECL clock input Fig 19. Differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 20. The common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. PACKAGE ESD PARASITICS CLKP Vcm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ CLKM 005aaa056 Fig 20. Equivalent input circuit ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 20 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Single-ended or differential clock inputs can be selected via the SPI interface (see Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performances of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 21), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and 55 %. 11.4.4 Clock input divider The ADC1410S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see Table 21). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see Table 23). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 21. The buffer is powered by a separate power supply, pins OGND and VDDO, to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO PARASITICS LOGIC DRIVER ESD PACKAGE 50 Ω Dx OGND 005aaa057 Fig 21. CMOS digital output buffer ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 21 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output The output resistance is 50 Ω and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 30): 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table 23). VCCO 3.5 mA typ − + DnP/Dn + 1P 100 Ω RECEIVER DnM/Dn + 1M − + OGND 005aaa058 Fig 22. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver side (Figure 22) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 23 and Table 32). VCCO 3.5 mA typ − + DxP/Dx + 1P 100 Ω RECEIVER DxM/Dx + 1M + − OGND 005aaa059 Fig 23. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic voltage levels. ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 22 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 14. LVDS DDR output register 2 LVDS_INT_TER[2:0] Resistor value (Ω) 000 no internal termination 001 300 010 180 011 110 100 150 101 100 110 81 111 60 11.5.3 Data valid (DAV) output clock A data valid output clock signal (DAV) can be used to capture the data delivered by the ADC1410S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in Figure 4 and Figure 5 respectively. 11.5.4 Out-of-Range (OTR) An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1; see Table 29). In this mode, the latency of OTR is reduced to only four clock cycles. The Fast OTR detection threshold (below full-scale) can be programmed via bits FASTOTR_DET[2:0]. Table 15. Fast OTR register FASTOTR_DET[2:0] Detection level (dB) 000 −20.56 001 −16.12 010 −11.02 011 −7.82 100 −5.49 101 −3.66 110 −2.14 111 −0.86 11.5.5 Digital offset By default, the ADC1410S delivers output code that corresponds to the analog input. However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET[5:0]; see Table 25). 11.5.6 Test patterns For test purposes, the ADC1410S can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected when TESTPAT_SEL[2:0] = 101. The selected test pattern will be transmitted regardless of the analog input. ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 23 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 11.5.7 Output codes versus input voltage Table 16. Output codes VINP − VINM Offset binary Two’s complement OTR pin < −1 00 0000 0000 0000 10 0000 0000 0000 1 −1 00 0000 0000 0000 10 0000 0000 0000 0 −0.9998779 00 0000 0000 0001 10 0000 0000 0001 0 −0.9997559 00 0000 0000 0010 10 0000 0000 0010 0 −0.9996338 00 0000 0000 0011 10 0000 0000 0011 0 −0.9995117 00 0000 0000 0100 10 0000 0000 0100 0 .... .... .... 0 −0.0002441 01 1111 1111 1110 11 1111 1111 1110 0 −0.0001221 01 1111 1111 1111 11 1111 1111 1111 0 0 10 0000 0000 0000 00 0000 0000 0000 0 +0.0001221 10 0000 0000 0001 00 0000 0000 0001 0 +0.0002441 10 0000 0000 0010 00 0000 0000 0010 0 .... .... .... 0 +0.9995117 11 1111 1111 1011 01 1111 1111 1011 0 +0.9996338 11 1111 1111 1100 01 1111 1111 1100 0 +0.9997559 11 1111 1111 1101 01 1111 1111 1101 0 +0.9998779 11 1111 1111 1110 01 1111 1111 1110 0 +1 11 1111 1111 1111 01 1111 1111 1111 0 > +1 11 1111 1111 1111 01 1111 1111 1111 1 11.6 Serial peripheral interface 11.6.1 Register description The ADC1410S serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will be transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 18). Table 17. Instruction bytes for the SPI MSB ADC1410S_SER_3 Preliminary data sheet LSB Bit 7 6 5 4 3 2 1 0 Description R/W[1] W1[2] W0[2] A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 [1] Bit R/W indicates whether it is a read (1) or a write (0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18). All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 24 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 18. Number of data bytes to be transferred after the instruction bytes W1 W0 Number of bytes transmitted 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes or more Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end on data transmission. CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Instruction bytes A1 A0 D7 D6 D5 D4 D3 D2 Register N (data) D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register N + 1 (data) 005aaa062 Fig 24. SPI mode timing 11.6.2 Default modes at start-up During circuit initialization, it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on CS will trigger a transition to SPI control mode. When the ADC1410S enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 25). Once in SPI control mode, the output data standard can be changed via bit LVDS/CMOS in Table 23. When the ADC1410S enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] in Table 23. ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 25 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 25. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 26. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 26 of 37 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 19. NXP Semiconductors ADC1410S_SER_3 Preliminary data sheet 11.6.3 Register allocation map Register allocation map R/W Bit definition 0005 Reset and operating mode R/W SW_RST 0006 Clock R/W - - - SE_SEL 0008 Internal reference R/W - - - - INTREF_EN 0011 Output data standard R/W - - - LVDS_CMOS OUTBUF 0012 Output clock R/W - - - - DAVINV 0013 Offset R/W - - 0014 Test pattern 1 R/W - - - - - 0015 Test pattern 2 R/W 0016 Test pattern 3 R/W Bit 7 Default Bit 6 Bit 5 Bit 4 RESERVED[2:0] Bit 3 Bit 2 - - DIFF_SE - Bit 1 Bit 0 Bin OP_MODE[1:0] CLKDIV DCS_EN INTREF[2:0] OUTBUS_SWAP 0000 1110 TESTPAT_SEL[2:0] 0000 0000 0000 0000 0000 0000 TESTPAT_USER[5:0] Fast OTR R/W - - - - CMOS output R/W - - - - 0021 LVDS DDR O/P 1 R/W - - DAVI_x2_EN 0022 LVDS DDR O/P 2 R/W - - - - FASTOTR - - FASTOTR_DET[2:0] DAV_DRV[1:0] DAVI[1:0] BIT_BYTE_ WISE 0000 0000 DAVPHASE[2:0] TESTPAT_USER[13:6] 0020 0000 0001 0000 0000 DATA_FORMAT[1:0] DIG_OFFSET[5:0] 0017 0000 0000 DATAI_x2_EN 0000 0000 0000 0000 DATA_DRV[1:0] 0000 1110 DATAI[1:0] 0000 0000 LVDS_INT_TER[2:0] 0000 0000 ADC1410S series 27 of 37 © NXP B.V. 2010. All rights reserved. ADC1410S series; CMOS or LVDS DDR digital output Rev. 03 — 12 April 2010 All information provided in this document is subject to legal disclaimers. AddrH Register name ex ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 20. Reset and operating mode control register (address 0005h) bit description Bit Symbol Access 7 SW_RST R/W Value Description reset digital section 0 no reset 1 performs a reset on SPI registers 6 to 4 RESERVED[2:0] 000 reserved 3 to 2 - 00 not used 1 to 0 OP_MODE[1:0] Table 21. Symbol 7 to 5 - 4 SE_SEL DIF_SE 2 - 1 CLKDIV 0 operating mode 00 normal (power-up) 01 power-down 10 sleep 11 normal (power-up) Clock control register (address 0006h) bit description Bit 3 R/W DCS_EN ADC1410S_SER_3 Preliminary data sheet Access Value Description 000 not used R/W single-ended clock input pin select 0 CLKM 1 CLKP R/W differential/single ended clock input select 0 fully differential 1 single-ended 0 R/W not used clock input divide by 2 0 disabled 1 enabled R/W duty cycle stabilizer 0 disabled 1 enabled All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 28 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 22. Internal reference control register (address 0008h) bit description Bit Symbol 7 to 4 - 3 INTREF_EN 2 to 0 INTREF[2:0] Table 23. Value Description 0 not used R/W programmable internal reference enable 0 disable 1 active R/W programmable internal reference 000 0 dB (FS = 2 V) 001 −1 dB (FS = 1.78 V) 010 −2 dB (FS = 1.59 V) 011 −3 dB (FS = 1.42 V) 100 −4 dB (FS = 1.26 V) 101 −5 dB (FS = 1.12 V) 110 −6 dB (FS = 1 V) 111 reserved Output data standard control register (address 0011h) bit description Bit Symbol 7 to 5 - 4 LVDS_CMOS 3 Access OUTBUF Access Value Description 000 not used R/W output data standard: LVDS DDR or CMOS 0 CMOS 1 LVDS DDR R/W output buffers enable 0 1 2 1 to 0 OUTBUS_SWAP DATA_FORMAT[1:0] ADC1410S_SER_3 Preliminary data sheet output enabled output disabled (high Z) 0 outbus swapping 0 no swapping 1 output bus is swapping (MSB becomes LSB and vice versa) R/W output data format 00 offset binary 01 two’s complement 10 gray code 11 offset binary All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 29 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 24. Output clock register (address 0012h) bit description Bit Symbol 7 to 4 - 3 DAVINV 2 to 0 DAVPHASE[2:0] Table 25. Access Value Description 0000 not used R/W output clock data valid (DAV) polarity 0 normal 1 inverted R/W DAV phase select 000 output clock shifted (ahead) by 3 ns 001 output clock shifted (ahead) by 2.5 ns 010 output clock shifted (ahead) by 2 ns 011 output clock shifted (ahead) by 1.5 ns 100 output clock shifted (ahead) by 1 ns 101 output clock shifted (ahead) by 0.5 ns 110 default value as defined in timing section 111 output clock shifted (delayed) by 0.5 ns Offset register (address 0013h) bit description Bit Symbol 7 to 6 - 5 to 0 DIG_OFFSET[5:0] Access Value Description 00 not used R/W digital offset adjustment 011111 ... 000000 0 ... ... 100000 Table 26. +31 LSB ... −32 LSB Test pattern register 1 (address 0014h) bit description Bit Symbol 7 to 3 - 2 to 0 TESTPAT_SEL[2:0] Table 27. Access Value Description 00000 not used R/W digital test pattern select 000 off 001 mid scale 010 −FS 011 +FS 100 toggle ‘1111..1111’/’0000..0000’ 101 custom test pattern 110 ‘1010..1010.’ 111 ‘010..1010’ Test pattern register 2 (address 0015h) bit description Bit Symbol Access Value 7 to 0 TESTPAT_USER[13:6] R/W 00000000 custom digital test pattern (bits 13 to 6) ADC1410S_SER_3 Preliminary data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 30 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 28. Test pattern register 3 (address 0016h) bit description Bit Symbol Access Value Description 7 to 2 TESTPAT_USER[5:0] R/W 000000 custom digital test pattern (bits 5 to 0) 1 to 0 - 00 not used Table 29. Fast OTR register (address 0017h) bit description Bit Symbol 7 to 4 - 3 FASTOTR 2 to 0 Value Description 0000 not used R/W FASTOTR_DET[2:0] Table 30. fast Out-of-Range (OTR) detection 0 disabled 1 enabled R/W set fast OTR detect level 000 −20.56 dB 001 −16.12 dB 010 −11.02 dB 011 −7.82 dB 100 −5.49 dB 101 −3.66 dB 110 −2.14 dB 111 −0.86 dB CMOS output register (address 0020h) bit description Bit Symbol 7 to 4 - 3 to 2 DAV_DRV[1:0] 1 to 0 Access DATA_DRV[1:0] ADC1410S_SER_3 Preliminary data sheet Access Value Description 0000 not used R/W drive strength for DAV CMOS output buffer 00 low 01 medium 10 high 11 very high R/W drive strength for DATA CMOS output buffer 00 low 01 medium 10 high 11 very high All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 31 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Table 31. LVDS DDR output register 1 (address 0021h) bit description Bit Symbol 7 to 6 - 5 DAVI_x2_EN 4 to 3 2 1 to 0 DAVI[1:0] DATAI_x2_EN DATAI[1:0] Table 32. Value Description 00 not used R/W double LVDS current for DAV LVDS buffer 0 disabled 1 enabled R/W LVDS current for DAV LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA R/W double LVDS current for DATA LVDS buffer 0 disabled 1 enabled R/W LVDS current for DATA LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA LVDS DDR output register 2 (address 0022h) bit description Bit Symbol 7 to 4 - 3 BIT_BYTE_WISE 2 to 0 Access LVDS_INT_TER[2:0] ADC1410S_SER_3 Preliminary data sheet Access Value Description 0000 not used R/W DDR mode for LVDS output 0 bit wise (even data bits output on DAV rising edge/odd data bits output on DAV falling edge) 1 byte wise (MSB data bits output on DAV rising edge/LSB data bits output on DAV falling edge) R/W internal termination for LVDS buffer (DAV and DATA) 000 no internal termination 001 300 Ω 010 180 Ω 011 110 Ω 100 150 Ω 101 100 Ω 110 81 Ω 111 60 Ω All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 32 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A B D SOT618-6 terminal 1 index area E A A1 c detail X e1 1/2 e e 11 20 C C A B C v w b y1 C y L 21 10 e e2 Eh 1/2 e 1 terminal 1 index area 30 40 31 X Dh 0 2.5 scale Dimensions Unit mm 5 mm A(1) A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh 0.2 6.1 6.0 5.9 4.55 4.40 4.25 6.1 6.0 5.9 4.55 4.40 4.25 e e1 0.5 4.5 e2 L v 4.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT618-6 References IEC JEDEC JEITA MO-220 --- sot618-6_po European projection Issue date 09-02-23 09-03-04 Fig 27. Package outline SOT618-6 (HVQFN40) ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 33 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 13. Revision history Table 33. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1410S_SER_3 20100412 Preliminary data sheet - ADC1410S065_080_105_125_2 Modifications: • Figure 12 “Reference equivalent schematic” has been updated. ADC1410S065_080_105_125_2 20090604 Objective data sheet - ADC1410S065_080_105_125_1 ADC1410S065_080_105_125_1 20090528 Objective data sheet - - ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 34 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 14.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 35 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ADC1410S_SER_3 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 36 of 37 ADC1410S series NXP Semiconductors ADC1410S series; CMOS or LVDS DDR digital output 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics . . . . . . . . . . . . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Clock and digital output timing . . . . . . . . . . . . 10 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information. . . . . . . . . . . . . . . . . . 13 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPI and PIN control modes . . . . . . . . . . . . . . 13 Operating mode selection. . . . . . . . . . . . . . . . 13 Selecting the output data standard . . . . . . . . . 13 Selecting the output data format. . . . . . . . . . . 14 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 15 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 15 System reference and power management . . 16 Internal/external references . . . . . . . . . . . . . . 16 Reference gain control . . . . . . . . . . . . . . . . . . 18 Common-mode output voltage (VO(cm)) . . . . . 19 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 19 Equivalent input circuit . . . . . . . . . . . . . . . . . . 20 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 21 Clock input divider . . . . . . . . . . . . . . . . . . . . . 21 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 21 Digital output buffers: CMOS mode . . . . . . . . 21 Digital output buffers: LVDS DDR mode . . . . . 22 Data valid (DAV) output clock . . . . . . . . . . . . . 23 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 23 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output codes versus input voltage . . . . . . . . . 24 Serial peripheral interface. . . . . . . . . . . . . . . . 24 Register description . . . . . . . . . . . . . . . . . . . . 24 Default modes at start-up . . . . . . . . . . . . . . . . 25 11.6.3 12 13 14 14.1 14.2 14.3 14.4 15 16 Register allocation map . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 33 34 35 35 35 35 36 36 37 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 April 2010 Document identifier: ADC1410S_SER_3