IRF IRU3073

Data Sheet No. PD94699
IRU3073
SYNCHRONOUS PWM CONTROLLER WITH
OVER-CURRENT PROTECTION / LDO CONTROLLER
FEATURES
DESCRIPTION
Synchronous Controller plus one LDO controller
Current Limit using MOSFET Sensing
Single 5V/12V Supply Operation
Programmable Switching Frequency up to
400KHz
Soft-Start Function
Fixed Frequency Voltage Mode
Precision Reference Voltage Available
Uncommitted Error Amplifier available for DDR
voltage tracking application
The IRU3073 controller IC is designed to provide a low
cost synchronous Buck regulator for on-board DC to DC
converter for multiple output applications.
The outputs can be programmed as low as 0.8V for low
voltage applications.
Selectable over-current protection is provided by using
external MOSFET's on-resistance for optimum cost and
performance.
This device features a programmable frequency set from
200KHz to 400KHz, under-voltage lockout for all input
supplies, an external programmable soft-start function
as well as output under-voltage detection that latches
off the device when an output short is detected.
APPLICATIONS
DDR memory source sink VTT application
Low cost on-board DC to DC such as
12V/5V to output voltages as low as 0.8V
Graphic Card
Hard Disk Drive
Multi-Output Applications
TYPICAL APPLICATION
3.3V
Vcc
Q1
Drv2
Fb2
R1
VOUT2
C2
12V
VcH
R2
L1
C1
+5V
U1 VcL
IRU3073
VP1
C3
0.1uF
C6
HDrv
Q4
D1
VREF
C4
R8
C7
C9
L2
R7
OCSet
VOUT1
Comp
LDrv
R9
Q5
C10
Rt
SS/SD
C11
Gnd
R10
Fb1
PGnd
R11
Figure 1 - Typical application of IRU3073.
PACKAGE ORDER INFORMATION
TA (°C)
0 To 70
Rev. 1.0
09/17/03
DEVICE
IRU3073CQ
PACKAGE
16-Pin Plastic QSOP NB (Q)
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1
IRU3073
ABSOLUTE MAXIMUM RATINGS
Vcc Supply Voltage ...................................................
VcL, VcH Supply Voltage ..........................................
Storage Temperature Range ......................................
Operating Junction Temperature Range .....................
-0.5 - 25V
-0.5 - 25V
-65°C To 150°C
0°C To 125°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device.
PACKAGE INFORMATION
16-PIN PLASTIC QSOP NB (Q)
Fb2 1
16 OCSet
Drv2 2
15 VcH
14 HDrv
Rt 3
SS/SD 4
13 Gnd
Comp 5
12 PGnd
Fb1 6
11 LDrv
VP1 7
10 VcL
VREF 8
9 Vcc
uJA=1128C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=5V, VcL=VcH=12V and TA=0°C to 70°C. Low duty
cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
PARAMETER
Feedback Voltage
Fb Voltage
Fb Voltage Line Regulation
Reference Voltage
Ref Voltage Initial Accuracy
Drive Current
UVLO
UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - VcH
UVLO Hysteresis - VcH
UVLO Threshold - Fb1
UVLO Hysteresis - Fb1
Supply Current
Vcc Dynamic Supply Current
Vc Dynamic Supply Current
Vcc Static Supply Current
Vc Static Supply Current
Soft-Start Section
Charge Current
2
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
0.784
0.8
0.2
0.816
0.625
V
%
0.784
0.8
2
0.816
V
mA
UVLO VCC Supply Ramping Up
3.9
4.8
UVLO VCH Supply Ramping Up
3.3
UVLO Fb1 Fb Ramping Down
0.3
4.4
0.25
3.5
0.2
0.4
0.1
V
V
V
V
V
V
5
5
3.5
3
10
15
10
5
mA
mA
mA
mA
25
30
mA
VFB
LREG
5<Vcc<12
VREF
IREF
Note 1
Dyn ICC
Dyn IC
ICCQ
ICQ
SS IB
Freq=200KHz, CL=1500pF
Freq=200KHz, CL=1500pF
SS=0V
SS=0V
SS=0V
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3.7
0.5
Rev. 1.0
09/17/03
IRU3073
PARAMETER
Error Amp
Fb Voltage Input Bias Current
Fb Voltage Input Bias Current
VP Voltage Range
Transconductance
Oscillator
Frequency
SYM
Ramp Amplitude
Output Drivers
Rise Time
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
LDO Controller Section
Drive Current
Fb Voltage
Input Bias Current
Thermal Shutdown
Current Limit
OC Threshold Set Current
OC Comp Off-Set Voltage
VRAMP
IFB1
IFB2
VP
TEST CONDITION
SS=3V
SS=0V
Note 1
MIN
TYP
MAX UNITS
-5
35
0.8
-0.1
55
+5
75
1.5
mA
mA
V
mmho
210
400
1.25
240
460
KHz
50
50
100
90
100
100
700
Freq
Tr
Tf
TDB
DMAX
DMIN
Rt=100K
Rt=50K
Note 1
180
340
CLOAD =1500pF
CLOAD =1500pF
Fb=0.7V, Freq=200KHz
Fb=0.9V
Drv1
85
0
ns
ns
ns
%
%
40
0.784
-1
65
0.8
-0.1
150
0.816
+1
mA
V
mA
8C
20
-5
30
0
40
+5
mA
mV
Note 1
IOCSET
VOC(OFFSET)
VPP
Note 1: Guaranteed by design but not tested in production.
PIN DESCRIPTIONS
PIN#
1
2
3
PIN SYMBOL
PIN DESCRIPTION
Fb2
These pins provide feedback for the linear regulator controllers.
Drv2
Outputs of the linear regulator controllers.
Rt
A resistor should be connected from this pin to ground for setting the switching frequency.
4
SS / SD
5
Comp
6
Fb1
7
8
9
VP1
VREF
Vcc
10
VcL
11
LDrv
Rev. 1.0
09/17/03
This pin provides soft-start for the switching regulator. An internal current source charges
an external capacitor that is connected from this pin to ground which ramps up the output
of the switching regulator, preventing it from overshooting as well as limiting the input
current. The converter can be shutdown by pulling this pin down below 0.4V.
Compensation pin of the error amplifier. An external resistor and capacitor network is
typically connected from this pin to ground to provide loop compensation.
This pin is connected directly to the output of the switching regulator via resistor divider to
provide feedback to the Error amplifier.
Non-inverting input of error amplifier.
Reference voltage.
This pin provides biasing for the internal blocks of the IC as well as powers the LDO
controller. A minimum of 1mF, high frequency capacitor must be connected from this pin
to ground to provide peak drive current capability.
This pin powers the low side output driver and can be connected either to Vcc or separate
supply. A minimum of 1mF, high frequency capacitor must be connected from this pin to
ground to provide peak drive current capability.
Output driver for the synchronous power MOSFET.
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IRU3073
PIN#
12
PIN SYMBOL
PIN DESCRIPTION
PGnd
This pin serves as the separate ground for MOSFET's driver and should be connected to
system's ground plane.
Gnd
This pin serves as analog ground for internal reference and control circuitry. A high frequency capacitor must be connected from Vcc pin to this pin for noise free operation.
HDrv
Output driver for the high side power MOSFET. This pin should not go negative (below
ground), this may cause problem for the gate drive circuit. It can happen when the inductor
current goes negative (Source/Sink), soft-start at no load and for the fast load transient
from full load to no load. To prevent negative voltage at gate drive, a low forward voltage
drop diode might be connected between this pin and ground.
VcH
This pin is connected to a voltage that must be at least 4V higher than the bus voltage of
the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A
minimum of 1mF, high frequency capacitor must be connected from this pin to ground to
provide peak drive current capability.
OCSet
This pin is connected to the Drain of the lower MOSFET via an external resister and it
provides the positive sensing for the internal current sensing circuitry. The external resistor programs the current limit threshold depending on the RDS(ON) of the power MOSFET.
An external capacitor can be placed in parallel with the programming resistor to provide
high frequency noise filtering.
13
14
15
16
BLOCK DIAGRAM
Vcc 9
Bias
Generator
3V
1.25V
3V
0.8V
8 VREF
1.25V
20uA
POR
Vcc
VcH
SS/SD 4
3V
3 Rt
15 VcH
3.5V / 3.3V
Rt
Ct
Oscillator
En
14 HDrv
S
Error Comp
Comp 5
Fb1 6
UVLO
64uA
Max
POR
VP1 7
4.2V / 4.0V
25K
Q
Error Amp
R
10 VcL
Reset Dom
25K
11 LDrv
0.4V
20uA
CS Comp
POR
OCSet 16
12 PGnd
FbLo Comp
Vcc
0.8V
TSD
2 Drv2
Fb2 1
13 Gnd
Figure 2 - Simplified block diagram of the IRU3073.
4
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Rev. 1.0
09/17/03
IRU3073
THEORY OF OPERATION
Introduction
The IRU3073 is designed for a two output application
and it includes one synchronous buck controller and a
linear regulator controller. The PWM section is a fixed
frequency, voltage mode and consists of a precision reference voltage, an uncommitted error amplifier, an internal oscillator, a PWM comparator, an internal regulator,
a comparator for current limit, gate drivers, soft-start and
shutdown circuits (see Block Diagram).
The output voltage of the synchronous converter is set
and controlled by the output of the error amplifier; this is
the amplified error signal from the sensed output voltage
and the voltage on non-inverting input of error amplifier(V P).
This voltage is compared to a fixed frequency linear
sawtooth ramp and generates fixed frequency pulses of
variable duty-cycle, which drives the two N-channel external MOSFETs.
The timing of the IC is provided through an internal oscillator circuit which uses on-chip capacitor. The oscillation frequency is programmable between 200KHz to
400KHz by using an external resistor. Figure 14 shows
switching frequency vs. external resistor (Rt).
Soft-Start
The IRU3073 has a programmable soft-start to control
the output voltage rise and limit the current surge at the
start-up. To ensure correct start-up, the soft-start sequence initiates when the input supplies rise above their
threshold and generates the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal
current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the E/A’s output of
the PWM converter and disables the short circuit protection. During the power up of the buck converter, the
output starts at zero and voltage at Fb1 is below 0.4V.
The feedback UVLO is disabled during this time by injecting a current (64mA) into the Fb1. This generates a
voltage about 1.6V (64mA325K) across the negative
input of E/A and positive input of the feedback UVLO
comparator (see Fig3).
3V
20uA
HDrv
SS/SD
64uA
Max
POR
Comp
0.8V
Fb1
25K
Error Amp
LDrv
25K
0.4V
64uA325K=1.6V
When SS=0
POR
Feeback
UVLO Comp
Figure 3 - IRU3073 soft-start diagram.
The magnitude of this current is inversely proportional to
the voltage at soft-start pin.
The 20mA current source starts to charge up the external capacitor. In the mean time, the soft-start voltage
ramps up, the current flowing into Fb1 pin starts to decrease linearly and so does the voltage at the positive
pin of feedback UVLO comparator and the voltage negative input of E/A.
When the soft-start capacitor is around 1V, the current
flowing into the Fb1 pin is approximately 32mA. The voltage at the positive input of the E/A is approximately:
32mA325K = 0.8V
The E/A will start to operate and the output voltage starts
to increase. As the soft-start capacitor voltage continues to go up, the current flowing into the Fb1 pin will
keep decreasing. Because the voltage at pin of E/A is
regulated to reference voltage 0.8V, the voltage at the
Fb1 is:
VFB1 = 0.8-25K3(Injected Current)
Rev. 1.0
09/17/03
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IRU3073
The feedback voltage increases linearly as the injecting
current goes down. The injecting current drops to zero
when soft-start voltage is around 2V and the output voltage goes into steady state.
As shown in Figure 4, the positive pin of feedback UVLO
comparator is always higher than 0.4V, therefore, feedback UVLO is not functional during soft-start.
Output of UVLO
POR
3V
≅2V
Soft-Start
Voltage
Current flowing
into Fb1 pin
Supply Voltage Under-Voltage Lockout
The under-voltage lockout circuit assures that the
MOSFET driver outputs, remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if Vcc or VcH fall below 4.0V and 3.3V respectively. Normal operation resumes once these voltages rise above the set values.
≅1V
0V
Shutdown
The PWM section can be shutdown by pulling the softstart pin below 0.4V. The control MOSFET turns off and
the synchronous MOSFET turns on during shutdown.
64uA
0uA
Voltage at negative input ≅1.6V
of Error Amp and Feedback
UVLO comparator
Over-Current Protection
Over-current protection is achieved with a cycle by cycle
scheme and it is performed by sensing current through
the RDS(ON) of low side MOSFET. As shown in Figure 5,
an external resistor (RSET) is connected between OCSet
pin and the drain of low side MOSFET (Q2) and sets the
current limit set point. The internal current source develops a voltage across RSET. When the low side switch is
turned on, the inductor current flows through the Q2 and
results a voltage which is given by:
0.8V
0.8V
Voltage at Fb1 pin
LDO Controller
The LDO section is powered directly from Vcc. The output of LDO can be set as low as 0.8V and can be programmed to higher voltages by using two external resistors.
0V
Figure 4 - Theoretical operation waveforms
during Soft-Start.
From this analysis, the output start-up time is defined
as when soft-start capacitor voltage increases from 1V
to 2V. The start-up time will be dependent on the size of
the external soft-start capacitor and can be estimated
by:
VOCSET = IOCSET3RSET-RDS(ON)3iL
I OCSET
IRU3073
Q1
L1
OCSet RSET
20mA3TSTART/CSS = 2V-1V
For a given start up time, the soft-start capacitor can be
calculated as:
CSS = 20mA3TSTART/1V
VOUT
Q2
Osc
Figure 5 - Diagram of the over current sensing.
MOSFET Drivers
The driver capabilities of both high and low side drivers
are optimized to maintain fast switching transitions. They
are sized to drive a MOSFET that can deliver up to 20A
output current.
The low side MOSFET diver is supplied directly by VCC
while the high side driver is supplied by VC.
An internal dead time control is implemented to prevent
cross-conduction and allows the use of several kinds of
MOSFETs.
6
---(1)
When voltage VOCSET is below zero, the current sensing
comparator flips and disables the oscillator. The high
side MOSFET is turned off and the low side MOSFET is
turned on until the inductor current reduces to below
current set value. The critical inductor current can be
calculated by setting:
VOCSET = IOCSET3RSET - RDS(ON)3IL = 0
ISET = IL(CRITICAL) =
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RSET3IOCSET
RDS(ON)
---(2)
Rev. 1.0
09/17/03
IRU3073
If the over-current condition is temporary and goes away
quickly, the IRU3073 will resume its normal operation.
If output is shorted or over-current condition persists,
the output voltage will keep going down until it is below
0.4V. Then the output under-voltage lock out comparator
goes high and turns off both MOSFETs. The operation
waveforms are shown in Figure 6.
Inductor i L(PEAK)
iL(AVG)
Current
ISET=iL(VALLEY)
Current Limit
Comparator Output
HDrv
Feedback VREF
voltage 0.4V
Switching
frequency
High Side MOSFET
turn on time (t ON)
tOFF
tON
FS(NOM)
IOUT
IOUT
DMAX/FS(NOM)
VOUT
FS(NOM)3 VIN
IOUT
<IL>=IOUT
Normal
operation
From Figure 7, the average inductor current during the
current limit mode is:
DIPK-PK(LIM)
IO(LIM) = ISET +
---(4)
2
The inductor's ripple current can be expressed as:
DIPK-PK(LIM) =
(V IN - VOUT)3VOUT
VIN3L3fS
Combination of above equation and (4) results in:
Average Inductor
Current
IO(LIM)
Figure 7 - Operation waveforms during current limit.
IO(MAX)
IOUT
Over Current Shutdown
Limit Mode by UVLO
ISET = IO(LIM) -
RSET =
During over-current mode, the valley inductor current is:
iL(VALLEY) = ISET
IN
OUT
OUT
S
IN
---(5)
Combination of equations (5) and (2) results in the relationship between RSET and output current limit:
Figure 6 - Diagram of over-current operation.
Operation in current limit is shown in Figure 7, the high
side MOSFET is turned off and inductor current starts to
decrease. Because the output inductor current is higher
than the current limit setpoint (ISET), the over-current comparator keeps high until the inductor current decreases
to be below ISET. Then another cycle starts.
)3V
((V23f-V 3L3V
)
[
(
)]
RDS(ON)
(V IN-V OUT)3VOUT
3 IO(LIM) IOCSET
23fS3L3VIN
---(6)
Where:
IO(LIM) = The Output Current Limit -typical is 50%
higher than nominal output current.
VIN = Maximum Input Voltage
VOUT = Output Voltage
fS = Switching Frequency
L = Output Inductor
RDS(ON) = RDS(ON) of Low Side MOSFET
IOCSET = OC Threshold Set Current
The peak inductor current is given as:
IL(PEAK) = ISET+(V IN-V OUT)3tON/L
---(3)
To avoid undesirable trigger of over-current protection,
this relationship must be satisfied:
ISET / IO(NOM) - DIPK-PK(NOM)
2
Rev. 1.0
09/17/03
From the above analysis, the current limit is not only
dependent on the current setting resistor RSET and RDS(ON)
of low side MOSFET but it is also dependent on the
input voltage, output voltage, inductance and switching
frequency as well.
The cycle-by-cycle over-current limit will hold for a certain amount of time, until the output voltage drops below
0.4V, the under-voltage lock out activates and latches
off the output driver. The operation waveform is shown in
Figure 4. Normal operation will resume after IRU3073 is
powered up again.
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IRU3073
APPLICATION INFORMATION
Design Example:
The following example is a typical application for IRU3073,
the schematic is Figure 17 on page 16.
Supply Voltage
VCC=VCL=VCH=12V
Switcher
VIN = 5V
VOUT = 2.5V
IOUT = 8A
DVOUT = 50mV
fS = 200KHz
Linear Regulator
VIN = 2.5V
VOUT = 1.6V
IOUT = 2A
Output Voltage Programming
Output voltage is programmed by reference voltage and
external voltage divider. The Fb pin is the inverting input
of the error amplifier, which is referenced to the voltage
on non-inverting pin of error amplifier. For this application, this pin (V P) is connected to reference voltage (V REF).
The output voltage is defined by using the following equation:
R6
VOUT = VP 3 1 +
---(7)
R5
(
)
VP = VREF = 0.8V
When an external resistor divider is connected to the
output as shown in Figure 8.
VREF
R6
Fb
Figure 8 - Typical application of the IRU3039 for
programming the output voltage.
Equation (7) can be rewritten as:
R6 = R5 3
( VV
OUT
P
)
-1
Choose R5 = 1K. This will result to R6 = 2.15K
If the high value feedback resistors are used, the input
bias current of the Fb pin could cause a slight increase
in output voltage. The output voltage set point can be
more accurate by using precision resistor.
Soft-Start Programming
The soft-start timing can be programmed by selecting
the soft-start capacitance value. The start-up time of the
converter can be calculated by using:
Css ≅ 203tSTART (mF)
Where
8
---(8)
tSTART is the desirable start-up time (s)
Input Capacitor Selection
The input filter capacitor should be based on how much
ripple the supply can tolerate on the DC input line. The
ripple current generated during the on time of upper
MOSFET should be provided by input capacitor. The RMS
value of this ripple is expressed by:
IRMS = IOUT
D3(1-D)
---(9)
Where:
D is the Duty Cycle, D=VOUT/VIN.
IRMS is the RMS value of the input capacitor current.
IOUT is the output current for each channel.
For VIN=5V, IOUT=8A and D=0.5, the IRMS=4A
Inductor Selection
The inductor is selected based on operating frequency,
transient performance and allowable output voltage ripple.
R5
VP
Supply VcL and VcH
To drive the high side switch, it is necessary to supply a
gate voltage at least 4V greater than the Bus voltage.
For this application, VcL and VcH are biased with a separate 12V supply.
For higher efficiency, a low ESR capacitor is recommended. Choose two Poscap from Sanyo 6TPB47M
(16V, 47mF) with a max allowable ripple current of 5.2A.
VOUT
IRU3073
For a start-up time of 5ms, the soft-start capacitor will
be 0.1mF. Choose a ceramic capacitor at 0.1mF.
Low inductor value results to faster response to step
load (high di/dt) and smaller size but will cause larger
output ripple due to increase of inductor ripple current.
As a rule of thumb, select an inductor that produces a
ripple current of 10-40% of full load DC.
For the buck converter, the inductor value for desired
operating ripple current can be determined using the following relation:
Di
1
VOUT
; Dt = D3
;D=
Dt
fS
VIN
VOUT
L = (V IN - VOUT)3
---(11)
VIN3Di3fS
Where:
VIN = Maximum Input Voltage
VOUT = Output Voltage
∆i = Inductor Ripple Current
fS = Switching Frequency
∆t = Turn On Time
D = Duty Cycle
VIN - VOUT = L3
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Rev. 1.0
09/17/03
IRU3073
If Di = 25%(IO), then the output inductor will be:
L = 3.125mH
The Coilcraft DO5022HC series provides a range of inductors in different values, low profile suitable for large
currents. 3.3mH is a good choice for this application.
This will result to a ripple approximately 23% of output
current.
The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter,
the average inductor current is equal to the DC load current. The conduction loss is defined as:
2
PCOND(Upper Switch) = ILOAD 3RDS(ON)3D3q
2
PCOND(Lower Switch) = ILOAD 3RDS(ON)3(1 - D)3q
q = RDS(ON) Temperature Dependency
Output Capacitor Selection
The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
(ESR). In general, the output capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is
calculated by the following relationship:
DVO
ESR [
---(10)
DIO
Where:
DVO = Output Voltage Ripple
Di = Inductor Ripple Current
DVO = 50mV and DI ≅ 23% of 8A = 1.89A
This results to: ESR=26.5mV
The Sanyo TPC series, Poscap capacitor is a good choice.
The 6TPC330M, 330mF, 6.3V has an ESR 40mV. Selecting two of these capacitors in parallel, results to an
ESR of ≅ 20mV which achieves our low ESR goal.
The capacitor value must be high enough to absorb the
inductor's ripple current. The larger the value of capacitor, the lower will be the output ripple voltage.
Power MOSFET Selection
The IRU3073 uses two N-Channel MOSFETs. The selections criteria to meet power transfer requirements is
based on maximum drain-source voltage (V DSS), gatesource drive voltage (V GS), maximum output current, Onresistance RDS(ON) and thermal management.
The MOSFET must have a maximum operating voltage
(V DSS) exceeding the maximum input voltage (V IN).
The gate drive requirement is almost the same for both
MOSFETs. Logic-level transistor can be used and caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET,
which results a shoot-through current.
The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
Choose IRF7832 for both control MOSFET and synchronous MOSFET. This device provides low on-resistance
in a compact SOIC 8-Pin package.
The MOSFETs have the following data:
IRF7832
VDSS = 30V
ID = 16A @ 708C
RDS(ON) = 4mV
The total conduction losses will be:
PCON(TOTAL) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL) = 0.38W
The switching loss is more difficult to calculate, even
though the switching transition is well understood. The
reason is the effect of the parasitic components and
switching times during the switching procedures such
as turn-on / turnoff delays and rise and fall times. The
control MOSFET contributes to the majority of the switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions,
therefore, the turn on losses for synchronous MOSFET
can be neglected. With a linear approximation, the total
switching loss can be expressed as:
VDS(OFF) tr + tf
3
3 ILOAD
---(12)
2
T
Where:
VDS(OFF) = Drain to Source Voltage at off time
tr = Rise Time
tf = Fall Time
T = Switching Period
ILOAD = Load Current
PSW =
The switching time waveform is shown in Figure 9.
Rev. 1.0
09/17/03
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9
IRU3073
VDS
90%
The output LC filter introduces a double pole, –40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 1808 (see Figure 10). The Resonant frequency of the LC filter is expressed as follows:
1
FLC =
---(13)
2p3 LO3CO
10%
VGS
td(ON)
tr
td(OFF)
Figure 10 shows gain and phase of the LC filter. Since
we already have 1808 phase shift just from the output
filter, the system risks being unstable.
tf
Figure 9 - Switching time waveforms.
Gain
From IRF7832 data sheet we obtain:
Phase
08
0dB
-40dB/decade
IRF7832
tr = 12.3ns
tf = 21ns
These values are taken under a certain condition test.
For more details please refer to the IRF7832 datasheet.
FLC Frequency
-1808
F LC
Frequency
Figure 10 - Gain and phase of LC filter.
By using equation (12), we can calculate the total switching losses.
PSW(TOTAL) = 133mW
Programming the Over-Current Limit
The over-current threshold can be set by connecting a
resistor (RSET) from drain of low side MOSFET to the
OCSet pin. The resistor can be calculated by using equation (2).
The RDS(ON) has a positive temperature coefficient and it
should be considered for the worse case operation.
The E/A can be compensated with or without the use of
local feedback. When operated without local feedback,
the transconductance properties of the E/A become evident and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC circuit
from Comp pin to ground as shown in Figure 11.
Note that this method requires that the output capacitor
should have enough ESR to satisfy stability requirements.
In general, the output capacitor’s ESR generates a zero
typically at 5KHz to 50KHz which is essential for an
acceptable phase margin.
RDS(ON) = 4mV31.5 = 6mV
ISET ≅ IO(LIM) = 8A31.5 = 12A
(50% over nominal output current)
This results to: RSET ≅ 4.8KV
Select: RSET = 5KV
Feedback Compensation
The IRU3073 is a voltage mode controller; the control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast transient
response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation
network is to provide a closed loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin (greater than 458).
10
The IRU3073’s error amplifier is a differential-input
transconductance amplifier. The output is available for
DC gain control or AC phase compensation.
The ESR zero of the output capacitor expressed as follows:
FESR =
www.irf.com
1
2p3ESR3Co
---(14)
Rev. 1.0
09/17/03
IRU3073
VOUT
R6
For:
VIN = 5V
VOSC = 1.25V
Fo = 20KHz
FESR = 12KHz
Fb
R5
Vp=VREF
E/A
Comp
Ve
C9
R4
FLC = 3.41KHz
R5 = 1K
R6 = 2.15K
gm = 700mmho
This results to R4=23.14K
Choose R4=24K
CPOLE
Gain(dB)
To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole:
H(s) dB
FZ ≅ 75%FLC
Frequency
FZ
Figure 11 - Compensation network without local
feedback and its asymptotic gain plot.
FZ ≅ 0.753
1
LO 3 CO
2p
For:
Lo = 3.3mH
Co = 660mF
---(19)
FZ = 2.5KHz
R4 = 24K
The transfer function (Ve / VOUT) is given by:
(
H(s) = gm3
R5
1 + sR4C9
3
R6 + R5
sC9
)
Using equations (17) and (19) to calculate C9, we get:
---(15)
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain
and zero, expressed by:
R5
|H(s=j32p3FO)| = gm3
3R4
---(16)
R63R5
FZ =
1
2p3R43C9
Fo > FESR and FO [ (1/5 ~ 1/10)3fS
---(18)
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 and R6 = Resistor Dividers for Output Voltage
Programming
gm = Error Amplifier Transconductance
C93CPOLE
C9 + CPOLE
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
CPOLE =
Use the following equation to calculate R4:
1
VOSC Fo3FESR
R5 + R6
3
3
3
2
g
m
VIN
FLC
R5
1
FP =
2p3R43
First select the desired zero-crossover frequency (Fo):
Rev. 1.0
09/17/03
One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to suppress the switching noise. The additional
pole is given by:
---(17)
|H(s)| is the gain at zero cross frequency.
R4 =
C9 ≅ 2590pF; Choose C9 =2200pF
1
≅
1
p3R43fS
p3R43fS - 1
C9
fS
for FP <<
2
For a general solution for unconditionally stability for
ceramic capacitor with very low ESR and any type of
output capacitors, in a wide range of ESR values we
should implement local feedback with a compensation
network. The typically used compensation network for
voltage-mode controller is shown in Figure 12.
www.irf.com
11
IRU3073
VOUT
ZIN
C10
R7
R8
FZ1 =
C12
C11
R6
Zf
1
2p3R73C11
1
1
FZ2 = 2p3C103(R6 + R8) ≅
2p3C103R6
Cross Over Frequency:
Fb
E/A
R5
Comp
Ve
Gain(dB)
H(s) dB
FZ2
FP2
FP3
Frequency
Figure 12 - Compensation network with local
feedback and its asymptotic gain plot.
In such configuration, the transfer function is given by:
Ve
1 - gmZf
=
VOUT
1 + gmZIN
The error amplifier gain is independent of the transconductance under the following condition:
gmZf >> 1
and
gmZIN >>1
---(20)
By replacing ZIN and Zf according to Figure 7, the transformer function can be expressed as:
H(s) =
(1+sR7C11)3[1+sC10(R6+R8)]
1
3
sR6(C12+C11)
C12C11
1+sR7 C12+C11 3(1+sR8C10)
[
(
)]
As known, transconductance amplifier has high impedance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the
necessary range.
The compensation network has three poles and two zeros and they are expressed as follows:
FP1 = 0
FP2 =
FP3 =
1
2p3R83C10
12
---(21)
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (20) regarding transconductance error amplifier.
These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to
provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 458 for
overall stability.
Based on the frequency of the zero generated by ESR
versus crossover frequency, the compensation type can
be different. The table below shows the compensation
type and location of crossover frequency.
Compensator
Location of Zero
Typical
Type
Crossover Frequency
Output
(FO)
Capacitor
Type II (PI)
FPO < FZO < FO < fS/2
Electrolytic,
Tantalum
Type III (PID)
FPO < FO < FZO < fS/2
Tantalum,
Method A
Ceramic
Type III (PID)
FPO < FO < fS/2 < FZO
Ceramic
Method B
Table - The compensation type and location of zero
crossover frequency.
Detail information is dicussed in application Note AN1043 which can be downloaded from the IR Web-Site.
1
( CC 3C
+C )
2p3R73
VIN
1
3
VOSC 2p3Lo3Co
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
Co = Total Output Capacitors
Vp=VREF
FZ1
FO = R73C103
12
12
11
≅
1
2p3R73C12
11
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Rev. 1.0
09/17/03
IRU3073
LDO Section
Output Voltage Programming
Output voltage for LDO is programmed by reference voltage and external voltage divider. The Fb2 pin is the inverting input of the error amplifier, which is internally referenced to 0.8V. The divider is ratioed to provide 0.8V at
the Fb2 pin when the output is at its desired value. The
output voltage is defined by using the following equation
(
VOUT2 = VREF3 1+
R7
R10
)
For:
VOUT2 = 1.6V
VREF = 0.8V
R10 = 1KV
Results to R7=1KV
VOUT2
IRU3073
R7
Fb2
R10
Layout Consideration
The layout is very important when designing high frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start to place the power components. Make all the connections in the top layer with wide, copper filled areas.
The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET. To reduce
the ESR, replace the single input capacitor with two parallel units. The feedback part of the system should be
kept away from the inductor and other noise sources
and be placed close to the IC. In multilayer PCB, use
one layer as power ground plane and have a separate
control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with
the more sensitive analog control function. These two
grounds must be connected together on the PC board
layout at a single point.
500
Figure 13 - Programming the output voltage for LDO.
450
RDS(ON) =
Frequency (KHz)
400
LDO Power MOSFET Selection
The first step in selecting the power MOSFET for the
linear regulator is to select the maximum RDS(ON) based
on the input to the dropout voltage and the maximum
load current.
350
300
250
200
150
100
50
VIN(LDO) - VOUT2
IOUT2
0
0
50
100
150
200
250
300
350
400
450
500
550
Rt (K V)
For:
VIN(LDO) = 2.5V
VOUT2 = 1.6V
IOUT2 = 2A
Figure 14 - Switching Frequency vs. Rt.
Results to: RDS(ON)(MAX) = 0.45V
Note that since the MOSFET RDS(ON) increases with temperature, this number must be divided by ~1.5 in order
to find the RDS(ON)(MAX) at room temperature. The IRLR2703
has a maximum of 0.065V RDS(ON) at room temperature,
which meets our requirements.
Rev. 1.0
09/17/03
www.irf.com
13
IRU3073
TYPICAL APPLICATION
2.5V
Vcc
Q3
IRLR2703
C13
150uF
C16
1uF
Drv2
VcL
1.6V
@ 2A
R2
U1 VcH
IRU3073
VP1
C10
0.1uF
R7
24K
D2
BAT54
VREF
C2
33pF
C7
2200pF
C11
1uF
HDrv
OCSet
Comp
3.3uH
5.1K
Q2
IRF7832
SS/SD
Gnd
Fb1
PGnd
C1
47uF
L2
Rt
C6
0.1uF
+5V
C3
0.1uF
Q1
IRF7832
R4
LDrv
L1
1uH
D3
BAT54
C19
1uF
Fb2
1K
C14
R14
150uF
1K
C2A,B,C=47uF
C9B C9C C12
330uF 330uF 1uF
2.5V
@ 8A
R9
R10
1K
2.15K
Figure 15 - Typical application of IRU3073 for single 5V.
14
www.irf.com
Rev. 1.0
09/17/03
IRU3073
TYPICAL APPLICATION
3.3V
VcH
Q3
IRLR2703
C13
150uF
12V
C11
1uF
Drv2
Vcc
1.6V
@ 1A
R2
1K
C14
R14
150uF
1K
24K
Fb2
VcL
U1
IRU3073
VP1
C10
0.1uF
R7
C16
1uF
HDrv
D2
BAT54
VREF
C2
33pF
C7
2200pF
C19
1uF
OCSet
Comp
C2A,B,C=47uF
1uH
L2
3.3uH
5.1K
Q2
IRF7832
Rt
SS/SD
C6
0.1uF
Gnd
Fb1
PGnd
+5V
C1
47uF
Q1
IRF7832
R4
LDrv
L1
C9B C9C C12
330uF 330uF 1uF
2.5V
@ 8A
R9
R10
1K
2.15K
Figure 16 - Typical application of IRU3073.
Rev. 1.0
09/17/03
www.irf.com
15
IRU3073
DEMO-BOARD APPLICATION
2.5V
Vcc
Q3
IRLR2703
C13
150uF
12V
C11
1uF
Drv2
L1
VcH
1.6V
@ 2A
R2
C15
1uF
1K
C14 R14
150uF 1K
C10
0.1uF
C2
33pF
R7
C7
2200pF
24K
C16
1uF
Fb2
U1 VcL
IRU3073
VP1
C19
1uF
HDrv
D2
BAT54
VREF
OCSet
Comp
1uH
C2C C2B C2A
47uF 47uF 47uF
Q1
IRF7832
L2
R4
3.3uH
5.1K
LDrv
Q2
IRF7832
Rt
SS/SD
C6
0.1uF
Gnd
Fb1
PGnd
+5V
C1
47uF
C9B C9C C12
330uF 330uF 1uF
2.5V
@ 8A
R9
R10
1K
2.15K
Figure 17 - Typical application of IRU3073.
16
www.irf.com
Rev. 1.0
09/17/03
IRU3073
DEMO-BOARD APPLICATION
PARTS LIST
Ref Desig Description
Q1,Q2
MOSFET
Q3
MOSFET
U1
Controller
D2
Schottky Diode
L1
Inductor
L2
Inductor
C1,C2A,B,C Cap, Poscap
C2
Cap, Ceramic
C6,C10
Cap, Ceramic
C7
Cap, Ceramic
C8
Cap, Ceramic
C9B,C9C Cap, Poscap
C11,12,15, Cap, Ceramic
16,19,20,21
C13,C14
Cap, Poscap
R1
Resistor
R2,10,14
Resistor
R4
Resistor
R6
Resistor
R7
Resistor
R8
Resistor
R9
Resistor
Rev. 1.0
09/17/03
Value
30V, 4mV
30V, 45mV
1mH, 5.6A
3.3mH, 17A
47mF, 16V
33pF, NPO, 5%
0.1mF, Y5V, 25V
2200pF, X7R, 50V
470pF, X7R, 50V
330mF, 40mV
1mF, Y5V, 16V
150mF, 6.3V
10V
1K, 1%
5.1K, 1%
100K
24K, 1%
4.7V, 1%
2.15K, 1%
Qty
2
1
1
1
1
1
4
1
2
1
1
2
7
2
1
3
1
1
1
1
1
Part#
IRF7832
IRLR2703
IRU3073CQ
BAT54
DO3316P-102
DO5022P-332HC
16TPB47M
ECU-V1H330JCV
ECJ-2VF1E104
ECU-V1H222KBV
ECJ-2VC1H471J
6TPB330M
ECJ-2VF1C1O5Z
Manuf
IR
IR
IR
IR
Coilcraft
Coilcraft
Sanyo
Panasonic
Panasonic
Panasonic
Panasonic
Sanyo
Panasonic
Web site (www.)
irf.com
6TPB150M
Sanyo
Any
Any
Any
Any
Any
Any
Any
sanyo.com
www.irf.com
coilcraft.com
sanyo.com
maco.panasonic.co.jp
sanyo.com
maco.panasonic.co.jp
17
IRU3073
APPLICATION EXPERIMENTAL WAVEFORMS
Figure 18 - Normal condition at no load.
Ch1: HDrv
Ch2: LDrv
Ch4: Inductor Current
Figure 19 - Gate signals when SS pin pulls low.
Ch1: HDrv
Ch2: LDrv
Figure 20 - Soft-Start.
Ch1: VIN (5V)
Ch2: Bias Voltage (12V)
Ch3: VOUT1 (PWM)
Ch4: VOUT2 (LDO)
18
www.irf.com
Rev. 1.0
09/17/03
IRU3073
APPLICATION EXPERIMENTAL WAVEFORMS
Figure 21 - Output Shorted at start-up.
Ch1: VOUT
Ch4: IOUT
Figure 22 - Load Transient Response (PWM Section).
Ch1: VOUT1
Ch4: IOUT1 (0-8A)
Figure 23 - Load Transient Response (LDO Section).
Ch2: VOUT2
Ch4: IOUT2 (0-2A)
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.0
09/17/03
www.irf.com
19
IRU3073
(Q) QSOP Package, Narrow Body
16-Pin
H
A
M
B
D E
DETAIL-A
PIN NO. 1
L
C
0.366 0.13 x 458
K
G1 F
DETAIL-A
J
G
SYMBOL
A
B
C
D
E
F
G
G1
H
J
K
L
M
16-PIN
MIN
MAX
4.80
4.98
0.635 BSC
0.20
0.30
3.81
3.99
5.79
6.20
1.35
1.75
0.10
0.25
1.37
1.50
98 BSC
0.19
0.25
08
88
0.40
1.27
78638
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
20
www.irf.com
Rev. 1.0
09/17/03
IRU3073
PACKAGE SHIPMENT METHOD
PKG
DESIG
Q
PACKAGE
DESCRIPTION
PIN
COUNT
PARTS
PER REEL
TAPE & REEL
Orientation
16
2500
Fig A
QSOP Plastic, Narrow Body
1
1
1
Feed Direction
Figure A
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.0
09/17/03
www.irf.com
21