INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT299 8-bit universal shift register; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 The 74HC/HCT299 contain eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the mode select inputs (S0 and S1), as shown in the mode select table. All flip-flop outputs have 3-state buffers to separate these outputs (I/O0 to I/O7) such, that they can serve as data inputs in the parallel load mode. The serial outputs (Q0 and Q7) are used for expansion in serial shifting of longer words. FEATURES • Multiplexed inputs/outputs provide improved bit density • Four operating modes: – shift left – shift right – hold (store) – load data • Operates with output enable or at high-impedance OFF-state (Z) • 3-state outputs drive bus lines directly A LOW signal on the asynchronous master reset input (MR) overrides the Sn and clock (CP) inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is either state, provided that the recommended set-up and hold times, relative to the rising edge of CP, are observed. • Can be cascaded for n-bits word length • Output capability: bus driver (parallel I/Os), standard (serial outputs) • ICC category: MSI A HIGH signal on the 3-state output enable inputs (OE1 or OE2) disables the 3-state buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1, when in preparation for a parallel load operation. GENERAL DESCRIPTION The 74HC/HCT299 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER CONDITIONS UNIT HC HCT CP to Q0, Q7 20 19 ns propagation delay CL = 15 pF; VCC = 5 V CP to I/On 20 19 ns tPHL MR to Q0, Q7 or I/On 20 23 ns fmax maximum clock frequency 50 46 MHz CI input capacitance 3.5 3.5 pF CI/O input/output capacitance 10 10 pF CPD power dissipation capacitance per package 120 125 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz ORDERING INFORMATION fo = output frequency in MHz See “74HC/HCT/HCU/HCMOS Logic Package Information”. ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V December 1990 2 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 19 S0, S1 mode select inputs 2, 3 OE1, OE2 3-state output enable inputs (active LOW) 7, 13, 6, 14, 5, 15, 4, 16 I/O0 to I/O7 parallel data inputs or 3-state parallel outputs (bus driver) 8, 17 Q0, Q7 serial outputs (standard output) 9 MR asynchronous master reset input (active LOW) 10 GND ground (0 V) 11 DSR serial data shift-right input 12 CP clock input (LOW-to-HIGH, edge-triggered) 18 DSL serial data shift-left input 20 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 Fig.4 Functional diagram. MODE SELECT TABLE INPUTS RESPONSE MR S1 S0 CP L X X X asynchronous reset; Q0−Q7 = LOW H H H H H L H L H H L L ↑ ↑ ↑ X parallel load; I/On → Qn shift right; DSR → Q0, Q0 → Q1 etc. shift left; DSL → Q7, Q7 → Q6 etc. hold Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH CP transition December 1990 4 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 Fig.5 Logic diagram. December 1990 5 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver (parallel I/Os) standard (serial outputs) ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. min. typ. max. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay CP to Q0, Q7 66 24 19 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay CP to I/On 66 24 19 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 Fig.6 tPHL/ propagation delay MR to Q0, Q7 or I/On 66 24 19 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 Fig.7 tPZH 3-state output enable time OEn to I/On 50 18 14 155 31 26 195 39 33 235 47 40 ns 2.0 4.5 6.0 Fig.9 tPZL 3-state output enable time OEn to I/On 41 15 12 130 26 22 165 33 28 195 39 33 ns 2.0 4.5 6.0 Fig.9 tPHZ 3-state output disable time OEn to I/On 66 24 19 185 37 31 230 46 39 280 56 48 ns 2.0 4.5 6.0 Fig.9 tPLZ 3-state output disable time OEn to I/On 55 20 16 155 31 26 195 39 33 235 47 40 ns 2.0 4.5 6.0 Fig.9 tTHL/ tTLH output transition time bus driver (I/On) 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time standard (Q0, Q7) 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 tW clock pulse width HIGH or LOW 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tW master reset pulse width LOW 80 16 14 19 7 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 December 1990 6 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. min. typ. max. max. −40 to +125 min. WAVEFORMS UNIT V CC (V) max. trem removal time MR to CP 5 5 5 −14 −5 −4 5 5 5 5 5 5 ns 2.0 4.5 6.0 Fig.7 tsu set-up time DSR, DSL to CP 100 20 17 33 12 10 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.6 tsu set-up time S0, S1 to CP 100 20 17 33 12 10 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.8 tsu set-up time I/On to CP 125 25 21 39 14 11 155 31 26 190 38 32 ns 2.0 4.5 6.0 Fig.6 th hold time I/On, DSR, DSL to CP 0 0 0 −14 −5 −4 0 0 0 0 0 0 ns 2.0 4.5 6.0 Fig.6 th hold time S0, S1 to CP 0 0 0 −28 −10 −8 0 0 0 0 0 0 ns 2.0 4.5 6.0 Fig.8 fmax maximum clock pulse frequency 5.0 25 29 15 45 54 4.0 20 24 3.4 17 20 MHz 2.0 4.5 6.0 Fig.6 December 1990 7 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver (parallel I/Os) standard (serial outputs) ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT I/On DSR, DSL CP, S0 MR, S1 OEn 0.25 0.25 0.60 0.25 0.30 December 1990 8 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay CP to Q0, Q7 22 37 46 56 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CP to I/On 22 37 46 56 ns 4.5 Fig.6 tPHL propagation delay MR to Q0, Q7 or I/On 27 46 58 69 ns 4.5 Fig.7 tPZH/ tPZL 3-state output enable time OEn to I/On 19 30 38 45 ns 4.5 Fig.9 tPHZ 3-state output disable time OEn to I/On 24 37 46 56 ns 4.5 Fig.9 tPLZ 3-state output disable time OEn to I/On 20 32 40 48 ns 4.5 Fig.9 tTHL/ tTLH output transition time bus driver (I/On) 5 12 15 18 ns 4.5 Fig.6 tTHL/ tTLH output transition time standard (Q0, Q7) 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 20 10 25 30 ns 4.5 Fig.6 tW master reset pulse width LOW 20 11 25 30 ns 4.5 Fig.7 trem removal time MR to CP 10 2 9 11 ns 4.5 Fig.7 tsu set-up time I/On, DSR, DSL to CP 25 14 31 38 ns 4.5 Fig.6 tsu set-up time S0, S1 to CP 32 18 40 48 ns 4.5 Fig.8 th hold time I/On, DSR, DSL to CP 0 −11 0 0 ns 4.5 Fig.6 th hold time S0, S1 to CP 0 −17 0 0 ns 4.5 Fig.8 fmax maximum clock pulse frequency 25 42 20 17 MHz 4.5 Fig.6 December 1990 9 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 AC WAVEFORMS handbook, full pagewidth I/O n ,DSR,DSL VM INPUTS (1) t su t su th th 1/ f max V M (1) CP INPUT tW t PLH t PHL The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. I/O n,Q 0 ,Q 7 VM OUTPUTS t THL MBA335 Fig.6 (1) t TLH Waveforms showing the clock (CP) to output (I/On, Q0, Q7) propagation delays, the clock pulse width, the I/On, DSR and DSL to CP set-up and hold times, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the master reset (MR) pulse width (LOW), the master reset to output (I/On, Q0, Q7) propagation delays and the master reset to clock (CP) removal time. December 1990 10 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the set-up and hold times from the mode control inputs (S0, S1) to the clock (CP). (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the 3-state enable and disable times for OEn inputs. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 11