PHILIPS SAA7182A

INTEGRATED CIRCUITS
DATA SHEET
SAA7182A; SAA7183A
Digital Video Encoder
(EURO-DENC2)
Preliminary specification
Supersedes data of 1996 Sep 11
File under Integrated Circuits, IC22
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
FEATURES
• Monolithic CMOS 3.3 V device with 5 V input stages
• Digital PAL/NTSC/SECAM encoder
• System pixel frequency 13.5 MHz
• Accepts MPEG decoded data on 8-bit wide input port.
Input data format Cb, Y, Cr etc. “(CCIR 656) ” or
Y and Cb, Cr on 16 lines
This applies to SAA7183A only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Please contact your nearest Philips Semiconductor
sales office for more information
• Three DACs for CVBS, Y and C operating at 27 MHz
with 10 bit resolution
• Three DACs for RGB operating at 27 MHz with 9 bit
resolution, RGB sync on CVBS and Y
• Analog multiplexing between internal RGB and external
RGB on-chip
• CVBS, Y, C and RGB output simultaneously
• Controlled rise/fall times of output syncs and blanking
• Closed captioning and teletext encoding including
sequencer and filter
• Down-mode of DACs
• PQFP80 or PLCC84 package.
• Line 23 wide screen signalling encoding
• On-chip Cr, Y, Cb to RGB dematrix, including gain
adjustment for Y and Cr, Cb, optionally to be by-passed
for Cr, Y, Cb output on RGB DACs
GENERAL DESCRIPTION
The SAA7182A; SAA7183A encodes digital YUV video
data to an NTSC, PAL, SECAM CVBS or S-Video signal
and also RGB.
• Fast I2C-bus control port (400 kHz)
• Encoder can be master or slave
Optionally, the YUV to RGB dematrix can be by-passed
providing the digital-to-analog converted Cb, Y, Cr signals
instead of RGB.
• Programmable horizontal and vertical input
synchronization phase
• Programmable horizontal sync output phase
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip Digital-to-Analog Converters
(DACs).
• Internal Colour Bar Generator (CBG)
• Overlay with Look-Up Tables (LUTs) 8 × 3 bytes
• Macrovision Pay-per-View copy protection system as
option, also used for RGB output.
The circuit is compatible to the DIG-TV2 chip family.
ORDERING INFORMATION
TYPE
NUMBER
SAA7182AWP;
SAA7183AWP
1996 Oct 02
PACKAGE
NAME
PLCC84
QFP80
DESCRIPTION
VERSION
plastic leaded chip carrier; 84 leads
SOT189-2
plastic quad flat package; 80 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
SOT318-2
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDA3
3.3 V analog supply voltage
3.1
3.3
3.5
V
VDDD3
3.3 V digital supply voltage
3.0
3.3
3.6
V
VDDD5
5 V digital supply voltage
4.75
5.0
5.25
V
IDDA
analog supply current
−
−
110
mA
IDDD3
3.3 V digital supply current
−
−
80
mA
IDDD5
5 V digital supply current
−
−
10
mA
Vi
input signal voltage levels
Vo(p-p)
analog output signal voltages Y, C, CVBS and RGB without load −
(peak-to-peak value)
1.4
−
V
RL
load resistance
75
−
300
Ω
ILE
LF integral linearity error
−
−
±2
LSB
TTL compatible
DLE
LF differential linearity error
−
−
±1
LSB
Tamb
operating ambient temperature
0
−
+70
°C
1996 Oct 02
3
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
BLOCK DIAGRAM
RTCI
handbook, full pagewidth
TTXRQ XTALO
RCV2
CREF
84
83
4
I2C-BUS
INTERFACE
8
10 to 13
16 to 19
8
25 to 28
31 to 34
8
6 to 8
3
63, 64,
68, 70,
72, 74
SYNC
CLOCK
clock
and timing
DbDr
Y
DATA
MANAGER
75
8
SECAM
PROCESSOR
I2C-bus
control
VDDA4 to VDDA9
TESTB
50 35 36 20 47 45 44 48
37
I2C-bus
control
LLC
XTALI
CDIR
1
DP0
to
DP7
MP7
to
MP0
OVL2
to
OVL0
KEY
RCV1
RESET SDA SCL SA
8
I2C-bus
control
73
Y
ENCODER
CbCr
C
9
8
I2C-bus
control
D
OUTPUT
INTERFACE
I2C-bus
control
internal
control bus
8
71
A
I2C-bus
control
69
52, 67, 76
53
65
TTX
21
8
SAA7182A
SAA7183A
3
61
CbCr
VSSD1
to
VSSD9
5, 14, 22,
29, 38, 46,
49, 80, 82
VDDD1
to
VDDD9
2, 23, 40, 41,
43, 66
n.c.
78
SP
77
AP
D
59
58
A
55
56
54,
57, 60
GI
BI
Fig.1 Block diagram; PLCC84.
1996 Oct 02
62
RGB
PROCESSOR
Y
3, 15, 24,
30, 39, 42,
51, 79, 81
I2C-bus
control
4
VDDA1
to
VDDA3
CVBS
Y
CHROMA
VSSA1
to
VSSA3
TESTC
SELI
RI
RED
GREEN
BLUE
MGD668
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
RTCI
handbook, full pagewidth
RCV1
TTXRQ XTALO
RCV2
RESET SDA SCL SA
CREF
72
71
75
I2C-BUS
INTERFACE
8
1 to 4
7 to 10
8
15 to 18
21 to 24
8
DATA
MANAGER
52, 53,
56, 58,
60, 62
SYNC
CLOCK
clock
and timing
DbDr
Y
77 to 79
3
63
8
SECAM
PROCESSOR
I2C-bus
control
VDDA4 to VDDA9
TESTB
38 25 26 11 35 33 32 36
27
I2C-bus
control
LLC
XTALI
CDIR
73
DP0
to
DP7
MP7
to
MP0
OVL2
to
OVL0
KEY
SAA7182A; SAA7183A
8
I2C-bus
control
61
Y
OUTPUT
INTERFACE
ENCODER
CbCr
C
80
8
I2C-bus
control
D
I2C-bus
control
internal
control bus
8
59
A
I2C-bus
control
57
41, 55, 64
42
54
TTX
12
8
SAA7182A
SAA7183A
3
50
CbCr
VSSD1
to
VSSD9
5, 13, 19,
28, 34, 37,
68, 70, 76
VDDD1
to
VDDD9
30, 40
n.c.
66
SP
65
AP
D
48
47
A
44
45
43,
46, 49
GI
BI
Fig.2 Block diagram; QFP80.
1996 Oct 02
51
RGB
PROCESSOR
Y
6, 14, 20,
29, 31, 39,
67, 69, 74
I2C-bus
control
5
VDDA1
to
VDDA3
CVBS
Y
CHROMA
VSSA1
to
VSSA3
TESTC
SELI
RI
RED
GREEN
BLUE
MGD670
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PINNING
PIN
SYMBOL
DESCRIPTION
PLCC84
QFP80
RESET
1
73
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode.
The I2C-bus receiver waits for the START condition.
n.c.
2
−
not connected
VSSD1
3
6
digital ground 1
SA
4
75
The I2C-bus slave address select input pin. LOW: slave address = 88H,
HIGH = 8CH.
VDDD1
5
13
digital supply voltage 1 (3.3 V)
OVL2
6
77
OVL1
7
78
OVL0
8
79
KEY
9
80
DP0
10
1
DP1
11
2
DP2
12
3
DP3
13
4
VDDD2
14
5
digital supply voltage 2 (5 V)
VSSD2
15
14
digital ground 2
DP4
16
7
DP5
17
8
DP6
18
9
DP7
19
10
TTXRQ
20
11
Teletext request output, indicating when bit stream is valid.
TTX
21
12
Teletext bit stream input.
VDDD3
22
28
digital supply voltage 3 (3.3 V)
n.c.
23
−
not connected
VSSD3
24
20
digital ground 1
3-bit overlay data input. This is the index for the internal look-up table.
Key input for OVL. When HIGH it selects OVL input.
Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
MP7
25
15
MP6
26
16
MP5
27
17
MP4
28
18
VDDD4
29
19
digital supply voltage 4 (5 V)
VSSD4
30
29
digital ground 4
Upper 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
MP3
31
21
MP2
32
22
MP1
33
23
MP0
34
24
RCV1
35
25
Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.
RCV2
36
26
Raster Control 2 for video port. This pin provides an HS pulse of programmable
length or receives an HS pulse.
1996 Oct 02
Lower 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
6
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PIN
SYMBOL
DESCRIPTION
PLCC84
QFP80
RTCI
37
27
Real Time Control input. If the LLC clock is provided by an SAA7111 or SAA7151B,
RTCI should be connected to the RTCO pin of the respective decoder to improve
the signal quality.
VDDD5
38
68
digital supply voltage 5 (3.3 V)
VSSD5
39
39
digital ground 5
n.c.
40
40
not connected
n.c.
41
−
not connected
VSSD6
42
31
digital ground 6 for oscillator
n.c.
43
30
not connected
XTALI
44
32
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be
connected to ground.
XTALO
45
33
Crystal oscillator output (to crystal).
VDDD6
46
34
digital supply voltage 6 for oscillator (3.3 V)
CREF
47
35
Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
LLC
48
36
Line-Locked Clock. This is the 27 MHz master clock for the encoder. The I/O
direction is set by the CDIR pin.
VDDD7
49
37
digital supply voltage 7 (5 V)
CDIR
50
38
Clock direction. If CDIR input is HIGH, the circuit receives a clock and optional
CREF signal, otherwise if CDIR is LOW, CREF and LLC are generated by the
internal crystal oscillator.
VSSD7
51
67
digital ground 7
VSSA1
52
41
Analog ground 1 for the DACs.
TESTC
53
42
Analog test pin. Leave open-circuit for normal operation.
VDDA1
54
43
Analog supply voltage 1 for the RGB DACs (3.3 V).
BLUE
55
44
Analog output of the BLUE component.
BI
56
45
Analog input that can be switched to BLUE when SELI = HIGH.
VDDA2
57
46
Analog supply voltage 2 for RGB DACs (3.3 V).
GREEN
58
47
Analog output of GREEN component.
GI
59
48
Analog input that can be switched to GREEN when SELI = HIGH.
VDDA3
60
49
Analog supply voltage 3 for RGB DACs (3.3 V).
RED
61
50
Analog output of RED component.
RI
62
51
Analog input that can be switched to RED when SELI = HIGH.
VDDA4
63
52
Analog supply voltage 4 for DACs (3.3 V).
VDDA5
64
53
Analog supply voltage 5 for DACs (3.3 V).
SELI
65
54
Select analog input. Digital-to-analog converted RGB output when SELI = LOW;
RI, GI and BI output when SELI = HIGH.
n.c.
66
−
not connected
VSSA2
67
55
Analog ground 2 for the DACs.
VDDA6
68
56
Analog supply voltage 6 for DACs (3.3 V).
CHROMA
69
57
Analog output of the chrominance signal.
VDDA7
70
58
Analog supply voltage 7 for the Y/C/CVBS DACs (3.3 V).
1996 Oct 02
7
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PIN
SYMBOL
DESCRIPTION
PLCC84
QFP80
Y
71
59
Analog output of VBS signal.
VDDA8
72
60
Analog supply voltage 8 for the Y/C/CVBS DACs.
CVBS
73
61
Analog output of the CVBS signal.
VDDA9
74
62
Analog supply voltage 9 for the Y/C/CVBS DACs.
TESTB
75
63
Analog test pin. Leave open-circuit for normal operation.
VSSA3
76
64
Analog ground 3 for the DACs.
AP
77
65
Test pin. Connected to digital ground for normal operation.
SP
78
66
Test pin. Connected to digital ground for normal operation.
VSSD8
79
69
digital ground 8
VDDD8
80
76
digital supply voltage 8 (3.3 V)
VSSD9
81
74
digital ground 9
VDDD9
82
70
digital supply voltage 9 (5 V)
SCL
83
71
I2C-bus serial clock input.
SDA
84
72
I2C-bus serial data input/output.
1996 Oct 02
8
Philips Semiconductors
Preliminary specification
75 TESTB
76 VSSA3
77 AP
78 SP
79 VSSD8
80 VDDD8
81 VSSD9
82 VDDD9
83 SCL
SAA7182A; SAA7183A
84 SDA
1 RESET
2 n.c.
3 VSSD1
4 SA
5 VDDD1
6 OVL2
7 OVL1
9 KEY
10 DP0
11 DP1
handbook, full pagewidth
8 OVL0
Digital Video Encoder (EURO-DENC2)
DP2 12
74 VDDA9
DP3 13
73 CVBS
VDDD2 14
72 VDDA8
VSSD2 15
71 Y
DP4 16
70 VDDA7
DP5 17
69 CHROMA
DP6 18
68 VDDA6
DP7 19
67 VSSA2
TTXRQ 20
66 n.c.
TTX 21
65 SELI
SAA7182A
SAA7183A
VDDD3 22
64 VDDA5
n.c. 23
63 VDDA4
VSSD3 24
62 RI
MP7 25
61 RED
MP6 26
60 VDDA3
MP5 27
59 GI
MP4 28
58 GREEN
VDDD4 29
57 VDDA2
VSSD4 30
56 BI
Fig.3 Pin configuration; PLCC84.
1996 Oct 02
9
TESTC 53
VSSA1 52
VSSD7 51
CDIR 50
VDDD7 49
LLC 48
CREF 47
VDDD6 46
XTALO 45
XTALI 44
n.c. 43
VSSD6 42
n.c. 41
n.c. 40
VSSD5 39
VDDD5 38
RTCI 37
RCV2 36
54 VDDA1
RCV1 35
MP2 32
MP0 34
55 BLUE
MP1 33
MP3 31
MGD669
Philips Semiconductors
Preliminary specification
65 AP
66 SP
67 VSSD7
68 VDDD5
69 VSSD8
70 VDDD9
71 SCL
SAA7182A; SAA7183A
72 SDA
73 RESET
74 VSSD9
75 SA
76 VDDD8
77 OVL2
78 OVL1
handbook, full pagewidth
79 OVL0
80 KEY
Digital Video Encoder (EURO-DENC2)
DP0 1
64 VSSA3
DP1 2
63 TESTB
DP2 3
62 VDDA9
DP3 4
61 CVBS
VDDD2 5
60 VDDA8
VSSD1 6
59 Y
DP4 7
58 VDDA7
DP5 8
57 CHROMA
DP6 9
56 VDDA6
DP7 10
55 VSSA2
TTXRQ 11
54 SELI
TTX 12
53 VDDA5
SAA7182A
SAA7183A
VDDD1 13
52 VDDA4
VSSD2 14
51 RI
MP7 15
50 RED
MP6 16
49 VDDA3
MP5 17
48 GI
MP4 18
47 GREEN
VDDD4 19
46 VDDA2
VSSD3 20
45 BI
Fig.4 Pin configuration; QFP80.
1996 Oct 02
10
n.c. 40
VSSD5 39
CDIR 38
VDDD7 37
LLC 36
CREF 35
VDDD6 34
XTALO 33
XTALI 32
41 VSSA1
VSSD6 31
MP0 24
n.c. 30
42 TESTC
VSSD4 29
MP1 23
VDDD3 28
43 VDDA1
RTCI 27
MP2 22
RCV2 26
44 BLUE
RCV1 25
MP3 21
MGD671
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
actual subcarrier, PAL-ID, and if connected to SAA7111,
definite subcarrier phase can be inserted.
FUNCTIONAL DESCRIPTION
The digital video encoder (EURO-DENC2) encodes digital
luminance and colour difference signals into analog CVBS
and simultaneously S-Video signals. NTSC-M, PAL B/G,
SECAM standards and sub-standards are supported.
The EURO-DENC2 synthesizes all necessary internal
signals, colour subcarrier frequency, and synchronization
signals, from that clock.
Both interlaced and non-interlaced operation is possible
for all standards.
European teletext encoding is supported if an appropriate
teletext bitstream is applied to the TTX pin.
In addition, the de-matrixed Y, Cb, and Cr input is
available on three separate analog outputs as RED,
GREEN and BLUE. Under software control the dematrix
can be by-passed to output digital-to-analog converted Cr,
Y, and Cb signals on RGB outputs. Separate digital gain
adjustment for luminance and colour difference signals is
available.
Wide screen signalling data can be loaded via the I2C-bus,
and is inserted into line 23 for standards using 50 Hz field
rate.
The IC also contains Closed Caption and Extended Data
Services Encoding (Line 21), and supports anti-taping
signal generation in accordance with Macrovision; it also
supports overlay via KEY and three control bits by a
24 × 8 LUT.
Analog on-chip multiplexing between internal
digital-to-analog converted RGB and external RI, GI and
BI signals is also supported.
A number of possibilities are provided for setting different
video parameters such as:
The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of “RS-170-A” and “CCIR 624”.
Black and blanking level control
Colour subcarrier frequency
Variable burst amplitude etc.
During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the I2C-bus interface to abort any running bus transfer and
sets register 3A to 03H, register 61 to 06H and
registers 6BH and 6EH to 00H. All other control registers
are not influenced by a reset.
For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.
For total filter transfer characteristics see
Figs 5, 6, 7, 8, 9 and 10. The DACs for Y, C, and CVBS
are realized with full 10-bit resolution, DACs for RGB are
with 9-bit resolution.
Data manager
In the data manager, real time arbitration on the data
stream to be encoded is performed.
The MPEG port (MP) accept 8 line multiplexed Cb, Y, Cr
data.
Depending on the polarity of pin KEY, the MP input
(or MP/DP input) or OVL input are selected to be encoded
to CVBS and Y/C signals, and output as RGB.
The 8-bit multiplexed Cb-Y-Cr formats are “CCIR 656”
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is to operate in
slave mode.
KEY controls OVL entries of a programmable LUT for
encoded signals and for RGB output. The common KEY
switching signal can be disabled by software for the
signals to be encoded (Y, C and CVBS), such that OVL will
appear on RGB outputs, but not on Y, C and CVBS.
Alternatively, 8-bits Y on MP port and 8-bit multiplexed Cb,
Cr on DP port can be chosen as input.
A crystal-stable master clock (LLC) of 27 MHz, which is
twice the CCIR line-locked pixel clock of 13.5 MHz, needs
to be supplied externally. Optionally, a crystal oscillator
input/output pair of pins and an on-chip clock driver is
provided.
OVL input under control of KEY can be also used to insert
decoded teletext information or other on-screen data.
Optionally, the OVL colour LUTs located in this block, can
be read out in a pre-defined sequence (8 steps per active
video line), achieving, for example, a colour bar test
pattern generator without need for an external data
source. The colour bar function is only under software
control.
It is also possible to connect a Philips Digital Video
Decoder (SAA7111 or SAA7151B) in conjunction with a
CREF clock qualifier to EURO-DENC2. Via the RTCI pin,
connected to RTCO of a decoder, information concerning
1996 Oct 02
11
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Encoder
CLOSED CAPTION ENCODER
VIDEO PATH
Using this circuit, data in accordance with the specification
of Closed Caption or Extended Data Service, delivered by
the control interface, can be encoded (Line 21).
Two dedicated pairs of bytes (two bytes per field), each
pair preceded by run-in clocks and framing code, are
possible.
The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.
Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). After having been inserted a fixed
synchronization level, in accordance with standard
composite synchronization schemes, and blanking level,
programmable also in a certain range to allow for
manipulations with Macrovision anti-taping, additional
insertion of AGC super-white pulses, programmable in
height, is supported.
The actual line number where data is to be encoded in, can
be modified in a certain range.
Data clock frequency is in accordance with definition for
NTSC-M standard 32 times horizontal line frequency.
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
In order to enable easy analog post filtering, luminance is
interpolated from 13.5 MHz data rate to 27 MHz data rate,
providing luminance in 10-bit resolution. This filter is also
used to define smoothed transients for synchronization
pulses and blanking period. For transfer characteristic of
the luminance interpolation filter see Figs 7 and 8.
It is also possible to encode Closed Caption Data for 50 Hz
field frequencies at 32 times horizontal line frequency.
ANTI-TAPING (SAA7183A ONLY)
For more information contact your nearest Philips
Semiconductors sales office.
Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from 6.75 MHz data rate to 27 MHz data rate. One of the
interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. For transfer characteristics of the
chrominance interpolation filter see Figs 5 and 6.
RGB processor
This block contains a dematrix in order to produce RED,
GREEN and BLUE signals to be fed to a SCART plug.
Before Y, Cb and Cr signals are de-matrixed, individual
gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
For transfer curves of luminance and colour difference
components of RGB see Figs 9 and 10.
The amplitude of inserted burst is programmable in a
certain range, suitable for standard signals and for special
effects. Behind the succeeding quadrature modulator,
colour in 10-bit resolution is provided on subcarrier.
SECAM processor
The numeric ratio between Y and C outputs is in
accordance with set standards.
SECAM specific pre-processing is achieved in this block
by a pre-emphasis of colour difference signals (for gain
and phase see Figs 11 and 12).
TELETEXT INSERTION AND ENCODING
Pin TTX receives a teletext bitstream sampled at the LLC
clock, each teletext bit is carried by four or three LLC
samples.
A baseband frequency modulator with a reference
frequency shifted from 4.286 MHz to DC carries out
SECAM modulation in accordance with appropriate
standard or optionally wide clipping limits.
Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.
After the HF pre-emphasis, also applied on a DC reference
carrier (anti-Cloche filter; see Figs 13 and 14), line-by-line
sequential carriers with black reference of 4.25 MHz (Db)
and 4.40625 MHz (Dr) are generated using specified
values for FSC programming bytes.
TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines selectable independently for both fields.
The internal insertion window for text is set to 360 teletext
bits including clock run-in bits. For protocol and timing
see Fig.19.
1996 Oct 02
Alternating phase reset in accordance with SECAM
standard is carried out automatically. During vertical
blanking the so-called bottle pulses are not provided.
12
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
• A Vertical Sync signal (VS) with 3 or 2.5 lines duration,
or;
Output interface/DACs
In the output interface encoded both Y and C signals are
converted from digital-to-analog in 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.
• An ODD/EVEN signal which is LOW in odd fields, or;
• A field sequence signal (FSEQ) which is HIGH in the first
of 4, 8, 12 fields respectively.
The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitudes at the input
of the DAC for CVBS is reduced by 15⁄16 with respect to
Y and C DACs to make maximum use of conversion
ranges.
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
The polarity of both RCV1 and RCV2 is selectable by
software control.
RED, GREEN and BLUE signals are also converted from
digital-to-analog, each providing a 9-bit resolution. It is
also possible to feed through three external analog RGB
signals at pins RI, BI and GI when pin SELI = HIGH
The length of a field and the start and end of its active part
can be programmed. The active part of a field always
starts at the beginning of a line.
Outputs of the DACs can be set together in two groups via
software control to minimum output voltage for either
purpose.
I2C-bus interface
The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.
Synchronization
Synchronization of the EURO-DENC2 is able to operate in
two modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour related to RCV1 can be influenced by
programming the polarity and on-chip delay of RCV1.
Active slope of RCV1 defines the vertical phase and
optionally the odd/even and colour frame phase to be
initialized, it can be also used to set the horizontal phase.
Two I2C-bus slave addresses are selected:
88H: LOW at pin SA
8CH: HIGH at pin SA.
Input levels and formats
EURO-DENC2 expects digital Y, Cb, Cr data with levels
(digital codes) in accordance with “CCIR 601”.
If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be supplied at the RCV2 pin.
Timing and trigger behaviour can also be influenced for
RCV2.
For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.
If there are missing pulses at RCV1 and/or RCV2, the time
base of EURO-DENC2 runs free, thus an arbitrary number
of synchronization slopes may miss, but no additional
pulses (with the incorrect phase) must occur.
For RGB outputs variable amplification of the Y, Cb and Cr
components is provided, enabling adjustment of contrast
and colour saturation in certain range.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
Alternatively, the device can be triggered by auxiliary
codes in a CCIR 656 data stream at the MP port
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the IC can
output:
1996 Oct 02
SAA7182A; SAA7183A
13
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 1
SAA7182A; SAA7183A
“CCIR 601” signal component levels
SIGNALS(1)
COLOUR
White
Y
Cb
Cr
R(2)
G(2)
B(2)
235
128
128
235
235
235
Yellow
210
16
146
235
235
16
Cyan
170
166
16
16
235
235
Green
145
54
34
16
235
16
Magenta
106
202
222
235
16
235
Red
81
90
240
235
16
16
Blue
41
240
110
16
16
235
Black
16
128
128
16
16
16
Notes
1. Transformation:
a) R = Y + 1.3707 × (Cr − 128)
b) G = Y − 0.3365 × (Cb − 128) − 0.6982 × (Cr − 128)
c) B = Y + 1.7324 × (Cb − 128).
2. Representation of R, G and B (or Cr, Y and Cb) at the output is 9 bits at 27 MHz.
Table 2
8-bit multiplexed format (similar to “CCIR 601” )
BITS
TIME
Sample
0
1
2
2
4
5
6
7
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Luminance pixel number
0
1
Colour pixel number
Table 3
2
3
0
2
16-bit multiplexed format (DTV2 format)
BITS
TIME
0
Sample Y line
Sample UV line
Luminance pixel number
Colour pixel number
1996 Oct 02
1
2
3
4
5
6
7
Y0
Y1
Y2
Y3
Cb0
Cr0
Cb2
Cr2
1
2
0
0
3
2
14
1996 Oct 02
38
Gain Y for RGB
15
5D
5E
5F
60
61
62
63
Gain V MSB, blanking level,
decoder type
CCR, blanking level VBI
Null
Standard control
Burst amplitude
Subcarrier 0
5A
Chrominance phase
Gain U MSB, black level
59
OVL_LUT_V7
5B
58
OVL LUT U7
5C
57
OVL LUT Y7
Gain V
44
OVL LUT V0
FSC07
RTCE
DOWNB
0
CCRS1
GAINV8
GAINU8
GAINV7
GAINU7
CHPS7
OVLV77
OVLU77
OVLY77
OVLV07
OVLU07
OVLY07
CBENB
0
0
0
0
WSSON
WSS7
0
0
D7
FSC06
BSTA6
DOWNA
0
CCRS0
DECTYP
0
GAINV6
GAINU6
CHPS6
OVLV76
OVLU76
OVLY76
OVLV06
OVLU06
OVLY06
DISKEY
0
0
0
0
0
WSS6
0
0
D6
PCREF
0
0
0
0
WSS13
WSS5
0
0
FSC05
BSTA5
INPI
0
BLNVB5
BLNNL5
BLCKL5
GAINV5
GAINU5
CHPS5
OVLV75
OVLU75
OVLY75
↓
OVLV05
OVLU05
OVLY05
↓
↓
D5
FSC04
BSTA4
YGS
0
BLNVB4
BLNNL4
BLCKL4
GAINV4
GAINU4
CHPS4
OVLV74
OVLU74
OVLY74
OVLV04
OVLU04
OVLY04
SYMP
GCD4
GY4
0
0
WSS12
WSS4
0
0
D4
FSC03
BSTA3
SECAM
0
BLNVB3
BLNNL3
BLCKL3
GAINV3
GAINU3
CHPS3
OVLV73
OVLU73
OVLY73
OVLV03
OVLU03
OVLY03
DEMOFF
GCD3
GY3
0
0
WSS11
WSS3
0
0
D3
DATA BYTE
FSC02
BSTA2
SCBW
0
BLNVB2
BLNNL2
BLCKL2
GAINV2
GAINU2
CHPS2
OVLV72
OVLU72
OVLY72
OVLV02
OVLU02
OVLY02
FMT16
GCD2
GY2
0
0
WSS10
WSS2
0
0
D2
FSC01
BSTA1
PAL
0
BLNVB1
BLNNL1
BLCKL1
GAINV1
GAINU1
CHPS1
OVLV71
OVLU71
OVLY71
OVLV01
OVLU01
OVLY01
Y2C
GCD1
GY1
0
0
WSS9
WSS1
0
0
D1
FSC00
BSTA0
FISE
0
BLNVB0
BLNNL0
BLCKL0
GAINV0
GAINU0
CHPS0
OVLV70
OVLU70
OVLY70
OVLV00
OVLU00
OVLY00
UV2C
GCD0
GY0
0
0
WSS8
WSS0
0
0
D0
Digital Video Encoder (EURO-DENC2)
Gain U
43
OVL LUT U0
42
37
Null
OVL LUT Y0
28
Null
39
27
Wide screen signal
3A
26
Wide screen signal
Input port control
25
Null
Gain CD for RGB
00
Null
SUB
ADDRESS
Slave receiver (slave address 88H or 8CH)
REGISTER FUNCTION
Table 4
Bit allocation map
Philips Semiconductors
Preliminary specification
SAA7182A; SAA7183A
1996 Oct 02
78
79
7A
7B
7C
7D
7E
7F
TTX even request V E
First active line
Last active line
MSB vertical
Null
Disable TTX line
Disable TTX line
71
RCV2 output end
77
70
RCV2 output start
TTX even request V S
6F
Closed caption/teletext control
TTX odd request V E
6E
Multi control
76
6D
Trigger control
TTX odd request V S
6C
Trigger control
75
6B
RCV port control
74
6A
Line 21 even 1
MSBs TTX request H
69
Line 21 even 0
TTX request H end
68
Line 21 odd 1
73
67
Line 21 odd 0
TTX request H start
66
Subcarrier 3
72
65
MSBs RCV2 output
64
Subcarrier 2
SUB
ADDRESS
Subcarrier 1
REGISTER FUNCTION
16
LINE23
LINE15
0
0
LAL7
FAL7
TTXEVE7
LINE22
LINE14
0
LAL8
LAL6
FAL6
TTXEVE6
TTXEVS6
TTXOVE6
TTXOVS6
TTXHE10
TTXHE6
TTXHS6
RCV2E10
RCV2E6
RCV2S6
CCEN0
0
HTRIG9
HTRIG6
SRCV10
L21E16
L21E06
L21O16
L21O06
FSC30
FSC22
FSC14
D6
LINE21
LINE13
0
0
LAL5
FAL5
TTXEVE5
TTXEVS5
TTXOVE5
TTXOVS5
TTXHE9
TTXHE5
TTXHS5
RCV2E9
RCV2E5
RCV2S5
TTXEN
PHRES1
HTRIG8
HTRIG5
TRCV2
L21E15
L21E05
L21O15
L21O05
FSC29
FSC21
FSC13
D5
LINE20
LINE12
0
FAL8
LAL4
FAL4
TTXEVE4
TTXEVS4
TTXOVE4
TTXOVS4
TTXHE8
TTXHE4
TTXHS4
RCV2E8
RCV2E4
RCV2S4
CCLN4
PHRES0
VTRIG4
HTRIG4
ORCV1
L21E14
L21E04
L21O14
L21O04
FSC28
FSC20
FSC12
D4
LINE19
LINE11
0
TTXEVE8
LAL3
FAL3
TTXEVE3
TTXEVS3
TTXOVE3
TTXOVS3
0
TTXHE3
TTXHS3
0
RCV2E3
RCV2S3
CCLN3
0
VTRIG3
HTRIG3
PRCV1
L21E13
L21E03
L21O13
L21O03
FSC27
FSC19
FSC11
D3
LINE18
LINE10
0
TTXOVE8
LAL2
FAL2
TTXEVE2
TTXEVS2
TTXOVE2
TTXOVS2
TTXHS10
TTXHE2
TTXHS2
RCV2S10
RCV2E2
RCV2S2
CCLN2
0
VTRIG2
HTRIG2
CBLF
L21E12
L21E02
L21O12
L21O02
FSC26
FSC18
FSC10
D2
LINE17
LINE9
0
TTXEVS8
LAL1
FAL1
TTXEVE1
TTXEVS1
TTXOVE1
TTXOVS1
TTXHS9
TTXHE1
TTXHS1
RCV2S9
RCV2E1
RCV2S1
CCLN1
FLC1
VTRIG1
HTRIG1
ORCV2
L21E11
L21E01
L21O11
L21O01
FSC25
FSC17
FSC09
D1
LINE16
LINE8
0
TTXOVS8
LAL0
FAL0
TTXEVE0
TTXEVS0
TTXOVE0
TTXOVS0
TTXHS8
TTXHE0
TTXHS0
RCV2S8
RCV2E0
RCV2S0
CCLN0
FLCO
VTRIG0
HTRIG0
PRCV2
L21E10
L21E00
L21O10
L21O00
FSC24
FSC16
FSC08
D0
Digital Video Encoder (EURO-DENC2)
TTXEVS7
TTXOVE7
TTXOVS7
0
TTXHE7
TTXHS7
0
RCV2E7
RCV2S7
CCEN1
SBLBN
HTRIG10
HTRIG7
SRCV11
L21E17
L21E07
L21O17
L21O07
FSC31
FSC23
FSC15
D7
DATA BYTE
Philips Semiconductors
Preliminary specification
SAA7182A; SAA7183A
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
I2C-bus format
I2C-bus address; see Table 6
Table 5
S
SLAVE ADDRESS
Table 6
ACK
SUBADDRESS
ACK
DATA 0
ACK
--------
DATA n
ACK
P
Explanation of Table 5
PART
DESCRIPTION
S
START condition
Slave address
1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1)
ACK
acknowledge, generated by the slave
Subaddress (note 2)
subaddress byte
DATA
data byte
--------
continued data bytes and ACKs
P
STOP condition
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read.
2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
Slave Receiver
Table 7
Subaddress 26 and 27
DATA BYTE
LOGIC LEVEL
WSS0 to WSS13
−
DESCRIPTION
Wide Screen Signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
WSSON
Table 8
0
wide screen signalling output is disabled
1
wide screen signalling output is enabled
Subaddress 38 and 39
DATA BYTE
DESCRIPTION
GY0 to GY4
Gain luminance of RGB (Cr, Y and Cb) output, ranging from (1 − 16⁄32) to (1 + 15⁄32). Suggested
nominal value = −6 (11010b), depending on external application.
GCD0 to GCD4
Gain Colour Difference of RGB (Cr, Y and Cb) output, ranging from (1 - 16⁄32) to (1 + 15⁄32).
Suggested nominal value = −6 (11010b), depending on external application.
1996 Oct 02
17
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 9
SAA7182A; SAA7183A
Subaddress 3A
DATA
BYTE
UV2C
Y2C
FMT16
DEMOFF
SYMP
PCREF
DISKEY
CBENB
1996 Oct 02
LOGIC
LEVEL
DESCRIPTION
0
Cb, Cr data are two’s complement.
1
Cb, Cr data are straight binary. Default after reset.
0
Y data is two’s complement.
1
Y data is straight binary. Default after reset.
0
Selects Cb, Y, Cr and Y on 8 lines on MP port (“CCIR 656” compatible). Default after reset.
1
Selects Cb and Cr on DP port and Y on MP port.
0
Y, Cb and Cr for RGB dematrix is active. Default after reset.
1
Y, Cb and Cr for RGB dematrix is bypassed.
0
Horizontal and vertical trigger is taken from RCV2 and RCV1 respectively. Default after reset.
1
Horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP port.
0
Normal polarity of CREF for DIG-TV2 compatible input signals.
1
Inverted polarity of CREF for DIG-TV2 compatible input signals.
0
OVL keying enabled for Y, C and CVBS outputs. Default after reset.
1
OVL keying disabled for Y, C and CVBS outputs.
0
Data from input ports is encoded. Default after reset.
1
Colour bar with programmable colours (entries of OVL_LUTs) is encoded. The LUTs are read in
upward order from index 0 to index 7.
18
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 10 Subaddress 42 to 59
DATA BYTE(1)
INDEX(2)
COLOUR
White
Yellow
Cyan
OVLY
OVLU
OVLV
107 (6BH)
0 (00H)
0 (00H)
107 (6BH)
0 (00H)
0 (00H)
82 (52H)
144 (90H)
18 (12H)
34 (22H)
172 (ACH)
14 (0EH)
42 (2AH)
38 (26H)
144 (90H)
03 (03H)
29 (1DH)
172 (ACH)
Green
17 (11H)
182 (B6H)
162 (A2H)
240 (F0H)
200 (C8H)
185 (B9H)
Magenta
234 (EAH)
74 (4AH)
94 (5EH)
212 (D4H)
56 (38H)
71 (47H)
209 (D1H)
218 (DAH)
112 (70H)
193 (C1H)
227 (E3H)
84 (54H)
169 (A9H)
112 (70H)
238 (EEH)
163 (A3H)
84 (54H)
242 (F2H)
144 (90H)
0 (00H)
0 (00H)
144 (90H)
0 (00H)
0 (00H)
Red
Blue
Black
0
1
2
3
4
5
6
7
Notes
1. Contents of OVL look-up tables. All 8 entries are 8-bits. Data representation is in accordance with “CCIR 601”
(Y, Cb and Cr), but two’s complement, e.g. for a 100⁄100 (upper number) or 100⁄75 (lower number) colour bar.
2. For normal colour bar with CBENB = logic 1.
Table 11 Subaddress 5A
DATA BYTE(1)
CHPS
VALUE
RESULT
tbf
PAL-B/G and data from input ports
tbf
PAL-B/G and data from look-up table
tbf
NTSC-M and data from input ports
tbf
NTSC-M and data from look-up table
Note
1. Phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256
degrees.
1996 Oct 02
19
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 12 Subaddress 5B and 5D
DATA BYTE
GAINU
DESCRIPTION
CONDITIONS
variable gain for Cb signal; white-to-black = 92.5 IRE(1)
input representation
GAINU = 0
accordance with
GAINU = 118 (76H)
“CCIR 601”
white-to-black = 100 IRE(2)
nominal GAINU for
SECAM encoding
REMARKS
output subcarrier of U contribution = 0
output subcarrier of U contribution = nominal
GAINU = 0
output subcarrier of U contribution = 0
GAINU = 125 (7DH)
output subcarrier of U contribution = nominal
value = 106 (6AH)
Notes
1. GAINU = −2.17 × nominal to +2.16 × nominal.
2. GAINU = −2.05 × nominal to +2.04 × nominal.
Table 13 Subaddress 5C and 5E
DATA BYTE
GAINV
DESCRIPTION
CONDITIONS
variable gain for Cr signal;
input representation
accordance with
“CCIR 601”
white-to-black = 92.5 IRE(1)
GAINV = 0
output subcarrier of V contribution = 0
GAINV = 165 (A5H)
output subcarrier of V contribution = nominal
IRE(2)
white-to-black = 100
nominal GAINV for
SECAM encoding
REMARKS
GAINV = 0
output subcarrier of V contribution = 0
GAINV = 175 (AFH)
output subcarrier of V contribution = nominal
value = −129 (17FH)
Notes
1. GAINV = −1.55 × nominal to +1.55 × nominal.
2. GAINV = −1.46 × nominal to +1.46 × nominal.
Table 14 Subaddress 5D
DATA BYTE
BLCKL
DESCRIPTION
CONDITIONS
REMARKS
IRE(1)
variable black level; input white-to-sync = 140
representation accordance
BLCKL = 0
with “CCIR 601”
BLCKL = 63 (3FH)
white-to-sync = 143
output black level = 24 IRE
output black level = 49 IRE
IRE(2)
BLCKL = 0
output black level = 24 IRE
BLCKL = 63 (3FH)
output black level = 50 IRE
Notes
1. Output black level/IRE = BLCKL × 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal.
2. Output black level/IRE = BLCKL × 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal.
1996 Oct 02
20
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 15 Subaddress 5E
DATA BYTE
BLNNL
DESCRIPTION
variable blanking level
CONDITIONS
REMARKS
white-to-sync = 140 IRE(1)
BLNNL = 0
output blanking level = 17 IRE
BLNNL = 63 (3FH)
white-to-sync = 143
DECTYP
RTCI
output blanking level = 42 IRE
IRE(2)
BLNNL = 0
output blanking level = 17 IRE
BLNNL = 63 (3FH)
output blanking level = 43 IRE
logic 0
real time control input from SAA7151B
logic 1
real time control input from SAA7111
Notes
1. Output black level/IRE = BLNNL × 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal.
2. Output black level/IRE = BLNNL × 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal.
Table 16 Subaddress 5F
DATA BYTE
DESCRIPTION
BLNVB
variable blanking level during vertical blanking interval is typically identical to value of BLNNL
CCRS
select cross colour reduction filter in luminance; see Table 17
Table 17 Logic levels and function of CCRS
CCRS1
CCRS0
0
0
no cross colour reduction; for overall transfer characteristic of luminance see Fig.7
0
1
cross colour reduction #1 active; for overall transfer characteristic see Fig.7
1
0
cross colour reduction #2 active; for overall transfer characteristic see Fig.7
1
1
cross colour reduction #3 active; for overall transfer characteristic see Fig.7
1996 Oct 02
FUNCTION
21
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 18 Subaddress 61:
DATA BYTE
FISE
PAL
SCBW
SECAM
YGS
INPI
DOWNA
DOWNB
1996 Oct 02
LOGIC LEVEL
DESCRIPTION
0
864 total pixel clocks per line; default after reset
1
858 total pixel clocks per line
0
NTSC encoding (non-alternating V component)
1
PAL encoding (alternating V component); default after reset
0
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 5 and 6); wide clipping for
SECAM
1
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 5 and 6); default after reset
0
no SECAM encoding; default after reset
1
SECAM encoding activated
0
luminance gain for white − black 100 IRE; default after reset
1
luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black
0
PAL switch phase is nominal; default after reset
1
PAL switch phase is inverted compared to nominal
0
DACs for CVBS, Y and C in normal operational mode; default after reset
1
DACs for CVBS, Y and C forced to lowest output voltage
0
DACs for R, G and B in normal operational mode; default after reset
1
DACs for R, G and B forced to lowest output voltage
22
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 19 Subaddress 62A
DATA BYTE
RTCE
LOGIC LEVEL
DESCRIPTION
0
no real time control of generated subcarrier frequency
1
real time control of generated subcarrier frequency through SAA7151B or SAA7111
(timing see Fig.18)
Table 20 Subaddress 62B
DATA BYTE
BSTA
DESCRIPTION
amplitude of colour burst;
input representation in
accordance with
“CCIR 601”
CONDITIONS
REMARKS
white-to-black = 92.5 IRE;
burst = 40 IRE; NTSC encoding
BSTA = 0 to 1.25 × nominal(1)
white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding
BSTA = 0 to 1.76 × nominal(2)
white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding
BSTA = 0 to 1.20 × nominal(3)
white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding
BSTA = 0 to 1.67 × nominal(4)
fixed burst amplitude with SECAM encoding
Notes
1. Recommended value: BSTA = 102 (66H).
2. Recommended value: BSTA = 72 (48H).
3. Recommended value: BSTA = 106 (6AH).
4. Recommended value: BSTA = 75 (4BH).
Table 21 Subaddress 63 to 66 (four bytes to program subcarrier frequency)
DATA BYTE
DESCRIPTION
FSC0 to FSC3 ffsc = subcarrier frequency
(in multiples of line
frequency);
fllc = clock frequency (in
multiples of line
frequency)
CONDITIONS
 f fsc
32 
FSC = round  -------- × 2 
 f llc

see note 1
Note
1. Examples:
a) NTSC-M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH).
b) PAL-B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH).
c) SECAM: ffsc = 274.304, fllc = 1728 → FSC = 681786290 (28A33BB2H).
1996 Oct 02
23
REMARKS
FSC3 = most significant byte
FSC0 = least significant byte
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 22 Subaddress 67 to 6A
DATA BYTE(1)
DESCRIPTION
L21O0
first byte of captioning data, odd field
L21O1
second byte of captioning data, odd field
L21E0
first byte of extended data, even field
L21E1
second byte of extended data, even field
Note
1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective
bytes have to carry the parity bit, in accordance with the definition of Line 21 encoding format.
Table 23 Subaddress 6B
DATA BYTE
PRCV2
ORCV2
CBLF
LOGIC LEVEL
DESCRIPTION
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input,
respectively; default after reset
1
polarity of RCV2 as output is active LOW, falling edge is taken when input,
respectively
0
pin RCV2 is switched to input; default after reset
1
pin RCV2 is switched to output
0
if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse
that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default
after reset
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset
1
if ORCV2 = HIGH, pin RCV2 provides a ‘Composite-Blanking-Not’ signal, this is a
reference pulse that is defined by RCV2S and RCV2E, excluding Vertical Blanking
Interval, which is defined by FAL and LAL
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = 1) and as an internal blanking signal
PRCV1
0
polarity of RCV1 as output is active HIGH, rising edge is taken when input; default
after reset
1
polarity of RCV1 as output is active LOW, falling edge is taken when input
ORCV1
0
pin RCV1 is switched to input; default after reset
1
pin RCV1 is switched to output
TRCV2
0
horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from
decoded frame sync of CCIR 656 input (at bit SYMP = HIGH); default after reset
1
horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
−
defines signal type on pin RCV1; see Table 24
SRCV1
1996 Oct 02
24
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 24 Logic levels and function of SRCV1
DATA BYTE
AS OUTPUT
AS INPUT
VS
VS
SRCV11
SRCV10
0
0
0
1
FS
FS
1
0
FSEQ
FSEQ
1
1
not applicable
not applicable
FUNCTION
vertical sync each field; default after reset
frame sync (odd/even)
field sequence, vertical sync every fourth field
(PAL = 0), eighth field (PAL = 1) or twelfth field
(SECAM = 1)
−
Table 25 Subaddress 6C and 6D
DATA BYTE
HTRIG
DESCRIPTION
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = tbf (tbf)
Table 26 Subaddress 6D
DATA BYTE
LOGIC LEVEL
−
VTRIG
DESCRIPTION
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
Table 27 Subaddress 6E
DATA BYTE
LOGIC LEVEL
SBLBN
0
DESCRIPTION
vertical blanking is defined by programming of FAL and LAL; default after reset
1
vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz)
PHRES
−
selects the phase reset mode of the colour subcarrier generator; see Table 28
FLC
−
field length control; see Table 29
Table 28 Logic levels and function of PHRES
DATA BYTE
FUNCTION
PHRES1
PHRES0
0
0
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
0
1
reset every two lines or SECAM-specific if bit SECAM = 1
1
0
reset every eight fields
1
1
reset every four fields
1996 Oct 02
25
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 29 Logic levels and function of FLC
DATA BYTE
FUNCTION
FLC1
FLC0
0
0
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
0
1
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
1
0
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
1
1
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 30 Subaddress 6F
DATA BYTE
LOGIC LEVEL
DESCRIPTION
CCEN
−
enables individual Line 21 encoding; see Table 31
TTXEN
0
disables teletext insertion
1
enables teletext insertion
−
selects the actual line, where closed caption or extended data are encoded
SCCLN
line = (SCCLN + 4) for M-systems
line = (SCCLN + 1) for other systems
Table 31 Logic levels and function of CCEN
DATA BYTE
FUNCTION
CCEN1
CCEN0
0
0
Line 21 encoding off
0
1
enables encoding in field 1 (odd)
1
0
enables encoding in field 2 (even)
1
1
enables encoding in both fields
Table 32 Subaddress 70 to 72
DATA BYTE
RCV2S
DESCRIPTION
start of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
RCV2S = tbfH (tbfH)
RCV2E
end of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
RCV2E = tbfH (tbfH)
1996 Oct 02
26
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 33 Subaddress 73 to 75
DATA BYTE
TTXHS
DESCRIPTION
start of signal on pin TTXRQ (standard for 50 Hz field rate = tbf)
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
TTXHE
end of signal on pin TTXRQ (standard for 50 Hz field rate = TTXHS + 1402)
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
Table 34 Subaddress 76, 77 and 7C
DATA BYTE
DESCRIPTION
TTXOVS
first line of occurrence of signal on pin TTXRQ in odd field = TTXOVS + 1 (50 Hz field rate)
TTXOVE
last line of occurrence of signal on pin TTXRQ in odd field = TTXOVE (50 Hz field rate)
Table 35 Subaddress 78, 79 and 7C
DATA BYTE
DESCRIPTION
TTXEVS
first line of occurrence of signal on pin TTXRQ in even field = TTXEVS + 1 (50 Hz field rate)
TTXEVE
last line of occurrence of signal on pin TTXRQ in even field = TTXEVE (50 Hz field rate)
Table 36 Subaddress 7A to 7C
DATA BYTE
FAL
DESCRIPTION
first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines
FAL = 0 coincides with the first field synchronization pulse
LAL
last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines
LAL = 0 coincides with the first field synchronization pulse
Table 37 Subaddress 7A to 7C
DATA BYTE
LINE
DESCRIPTION
individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective
bits, disabled line = LINExx (50 Hz field rate)
this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE
SUBADDRESSES
In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up.
1996 Oct 02
27
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Slave Transmitter
Table 38 Slave transmitter (slave address 89H or 8DH)
REGISTER
FUNCTION
Status byte
DATA BYTE
SUBADDRESS
−
D7
D6
D5
VER2
VER1
VER0
D4
D3
CCRDO CCRDE
D2
D1
D0
0
FSEQ
O_E
Table 39 No subaddress
DATA BYTE
LOGIC LEVEL
DESCRIPTION
VER
−
Version identification of the device. It will be changed with all versions of the IC that
have different programming models. Current Version is 001 binary.
CCRDO
1
Closed caption bytes of the odd field have been encoded.
0
The bit is reset after information has been written to the subaddresses 67 and 68. It
is set immediately after the data has been encoded.
1
Closed caption bytes of the even field have been encoded.
0
The bit is reset after information has been written to the subaddresses 69 and 6A.
It is set immediately after the data has been encoded.
1
During first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields,
SECAM = 12 fields.
0
Not first field of a sequence.
1
During even field.
0
During odd field.
CCRDE
FSEQ
O_E
1996 Oct 02
28
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MBE737
handbook, full
6 pagewidth
Gv
(dB)
0
−6
−12
−18
−24
(1)
(2)
−30
−36
−42
−48
−54
0
2
4
6
8
10
(1) SCBW = 1.
(2) SCBW = 0.
Fig.5 Chrominance transfer characteristic 1.
MBE735
handbook, halfpage
2
Gv
(dB)
0
(1)
(2)
−2
−4
−6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1.
(2) SCBW = 0.
Fig.6 Chrominance transfer characteristic 2.
1996 Oct 02
29
12
f (MHz)
14
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MGD672
6
Gv full pagewidth
handbook,
(dB)
(4)
0
(2)
(3)
−6
(1)
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
(1)
(2)
(3)
(4)
CCRS1 = 0; CCRS0 = 1.
CCRS1 = 1; CCRS0 = 0.
CCRS1 = 1; CCRS0 = 1.
CCRS1 = 0; CCRS0 = 0.
Fig.7 Luminance transfer characteristic 1.
MBE736
handbook, halfpage
1
Gv
(dB)
(1)
0
−1
−2
−3
−4
−5
0
2
4
f (MHz)
6
(1) CCRS1 = 0; CCRS0 = 0.
Fig.8 Luminance transfer characteristic 2.
1996 Oct 02
30
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MGB708
handbook, full pagewidth
Gv 6
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
f (MHz)
14
Fig.9 Luminance transfer characteristic in RGB.
MGB706
handbook, full pagewidth
Gv 6
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
Fig.10 Colour difference transfer characteristic in RGB.
1996 Oct 02
31
12
f (MHz)
14
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MGB705
handbook, full pagewidth
10
Gv
(dB)
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
f (MHz)
Fig.11 Gain of SECAM pre-emphasis.
MGB704
handbook,30
full pagewidth
ϕ
(deg)
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
f (MHz)
Fig.12 Phase of SECAM pre-emphasis.
1996 Oct 02
32
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MGB703
handbook, full pagewidth
20
Gv
(dB)
16
12
8
4
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
f (MHz)
Fig.13 Gain of SECAM anti-Cloche.
MGB702
handbook, full pagewidth
80
ϕ
(deg)
60
40
20
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
f (MHz)
Fig.14 Phase of SECAM anti-Cloche.
1996 Oct 02
33
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
CHARACTERISTICS
VDDD(3) = 3.0 to 3.6 V; VDDD(5) = 4.75 to 5.25 V; Tamb = 0 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply
VDDA(3)
analog supply voltage (3.3 V)
3.1
3.5
V
VDDD(3)
digital supply voltage (3.3 V)
3.0
3.6
V
VDDD(5)
digital supply voltage (5 V)
4.75
5.25
V
IDDA
analog supply current
note 1
−
110
mA
IDDD(3)
digital supply current (3.3 V)
note 1
−
80
mA
IDDD(5)
digital supply current (5 V)
note 1
−
10
mA
V
Inputs
VIL
LOW level input voltage
(except SDA, SCL, AP, SP and XTALI)
−0.5
+0.8
VIH
HIGH level input voltage
(except LLC, SDA, SCL, AP, SP and XTALI)
2.0
VDDD(5) + 0.5 V
HIGH level input voltage (LLC)
2.4
VDDD(5) + 0.5 V
ILI
input leakage current
−
1
µA
Ci
input capacitance
clocks
−
10
pF
data
−
8
pF
I/Os at high impedance −
8
pF
V
Outputs
VOL
LOW level output voltage
(except SDA and XTALO)
note 2
0
0.6
VOH
HIGH level output voltage
(except LLC, SDA, and XTALO)
note 2
2.4
VDDD(5) + 0.5 V
HIGH level output voltage (LLC)
note 2
2.6
VDDD(5) + 0.5 V
I2C-bus; SDA and SCL
VIL
LOW level input voltage
−0.5
+1.5
VIH
HIGH level input voltage
3.0
VDDD(5) + 0.5 V
Ii
input current
Vi = LOW or HIGH
−10
+10
µA
VOL
LOW level output voltage (SDA)
IOL = 3 mA
−
0.4
V
Io
output current
during acknowledge
3
−
mA
V
Clock timing (LLC)
TLLC
cycle time
note 3
34
41
ns
δ
duty factor tHIGH/TLLC
note 4
40
60
%
tr
rise time
note 3
−
5
ns
tf
fall time
note 3
−
6
ns
Input timing
tSU;DAT
input data set-up time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
6
−
ns
tHD;DAT
input data hold time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
3
−
ns
1996 Oct 02
34
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SYMBOL
PARAMETER
SAA7182A; SAA7183A
CONDITIONS
MIN.
MAX.
UNIT
Crystal oscillator
fn
nominal frequency (usually 27 MHz)
3rd harmonic
−
30
MHz
∆f/fn
permissible deviation of nominal frequency
note 5
−50
+50
10−6
CRYSTAL SPECIFICATION
Tamb
operating ambient temperature
0
70
°C
CL
load capacitance
8
−
pF
RS
series resistance
−
80
Ω
C1
motional capacitance (typical)
1.5 −20% 1.5 +20%
fF
C0
parallel capacitance (typical)
3.5 −20% 3.5 +20%
pF
Data and reference signal output timing
CL
output load capacitance
7.5
40
pF
th
output hold time
4
−
ns
td
output delay time
−
25
ns
1.35
1.45
V
1
3
Ω
75
300
Ω
10
−
MHz
CHROMA, Y, CVBS and RGB outputs
Vo(p-p)
output signal voltage (peak-to-peak value)
note 6
Rint
internal serial resistance
RL
output load resistance
B
output signal bandwidth of DACs
ILE
LF integral linearity error of DACs
−
±2
LSB
DLE
LF differential linearity error of DACs
−
±1
LSB
−3 dB
Notes
1. At maximum supply voltage with highly active input signals.
2. The levels have to be measured with load circuits of 1.2 kΩ to 3.0 V (standard TTL load) and CL = 25 pF.
3. The data is for both input and output direction.
4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%.
5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of
subcarrier frequency and line/field frequency.
6. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.4 V, the typical minimum output
voltage (digital zero at DAC) is 0.2 V.
1996 Oct 02
35
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
handbook, full pagewidth
SAA7182A; SAA7183A
TLLC
tHIGH
2.6 V
1.5 V
0.6 V
LLC clock output
tHD; DAT
tf
tr
TLLC
tHIGH
2.4 V
1.5 V
0.8 V
LLC clock input
tSU; DAT
tHD; DAT
tf
tr
2.0 V
input data
valid
valid
not valid
0.8 V
td
tHD; DAT
2.4 V
output data
valid
valid
not valid
0.6 V
MBE742
Fig.15 Clock data timing.
handbook, full pagewidth
LLC
MP(n)
Cb(0)
Y(0)
Cr(0)
Y(1)
Cb(2)
RCV2
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase.
The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
Fig.16 Functional timing.
1996 Oct 02
36
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
handbook, full pagewidth
LLC
CREF
MP(n)
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
DP(n)
Cb(0)
Cr(0)
Cb(2)
Cr(2)
Cb(4)
RCV2
MBE739
The data demultiplexing phase is coupled to the internal horizontal phase.
The CREF signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz.
The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
Fig.17 Digital TV timing.
sequence reserved (2)
5 bits bit (1) reset
reserved
bit (3)
handbook, full pagewidth
H/L transition
count start
LOW
128
13
4 bits
reserved
HPLL
increment
FSCPLL increment (4)
0
21
0
RTCI
time slot: 0 1
14
19
67 68
not used in
SAA7182A/83A
valid
sample
(1) Sequence bit:
PAL = logic 0 then (R − Y) line normal; PAL = logic 1 then (R − Y) line inverted.
NTSC = logic 0 then no change.
(2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems.
(3) Only from SAA7111 decoder.
(4) SAAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
Fig.18 RTCI timing.
1996 Oct 02
37
invalid
sample
8/LLC
MGD673
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Thus 37 TTX bits correspond to 144 LLC clocks, each bit
has a duration of nearly 4 LLC clocks. The chip-internal
sequencer and variable phase interpolation filter
minimizes the phase jitter, and thus generates a
bandwidth limited signal, which is digital-to-analog
converted for the CVBS and Y outputs.
Teletext timing
Time tFD is the time needed to interpolate input data TTX
and inserting it into the CVBS and Y output signal, such
that it appears at tTTX = 10.2 µs after the leading edge of
the horizontal synchronization pulse.
Time tPD is the pipeline delay time introduced by the
source that is gated by TTXRQ in order to deliver TTX
data.
At the TTX input, bit duration scheme repeats after 37 TTX
bits or 144 LLC clocks. The protocol demands that TXX
bits 10, 19, 28 and 37 are carried by three LLC samples,
all others by four LLC samples. After a cycle of 37 TTX
bits, the next bits with three LLC samples are bits 47, 56,
65 and 74; this scheme holds for all succeeding cycles of
37 TTX bits, until 360 TTX bits (including 16 run-in bits)
are completed. For every additional line with TTX data, the
bit duration scheme starts in the same way.
Since the pulse representing the TTXRQ signal is fully
programmable in duration and rising/falling edges (TTXHS
and TTXHE), the TTX data is always inserted at the correct
position of 10.2 µs after the leading edge of outgoing
horizontal synchronization pulse.
Time tTTXWin is the internally used insertion window for
TTX data; it has a constant length that allows insertion of
360 teletext bits (maximum) at a text data rate of
6.9375 Mbits/s. The insertion window is not opened if the
control bit TTXEN is zero.
Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.
TELETEXT PROTOCOL
The frequency relationship between TTX bit clock and the
system clock LLC for 50 Hz field rate is given by the
relationship of line frequency multiples, which means
1728/444.
handbook, full pagewidth
CVBS/Y
tTTX
textbit #:
1
tTTXWin
2
3
4
5
6
7
8
9 10 11 12
13 14
15
16
17
18 19 20
21
22
4
1/LLC
23
24
TTX
4
tPD
3
4
1/LLC
3
4
tFD
TTXRQ
MGB701
Fig.19 Teletext timing diagram.
1996 Oct 02
38
1996 Oct 02
39
+3.3 V digital
100 nF V
DDD8 80
VSSD1 to VSSD5
and
VSSD7 to VSSD9
100 nF
100 nF
100 nF
74
72
RI
70
62
QI
68
59
BI
56
SELI
65
63
60
57
54
Fig.20 Application environment of the EURO-DENC2; PLCC84.
69
71
73
55
58
61
VSSA1 to VSSA3
52, 67, 76
2 Ω(1)
2 Ω(1)
2 Ω(1)
2 Ω(1)
2 Ω(1)
64
GREEN
BLUE
100 nF
100 nF
100 nF
100 nF
VDDA5 VDDA4 VDDA3 VDDA2 VDDA1
2 Ω(1)
VSSA
VSSA
VSSA
VSSA
RED
VDDA9 VDDA8 VDDA7 VDDA6
SAA7182A
SAA7183A
46
VDDD6
3, 15, 24, 30, 39, 51,
79, 81
42
45
44
100
nF
VSSD
XTALO VSSD6
VSSD
XTALI
10
pF
(1) Typical value. (2) For 100⁄100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003. (4) Depending on GY/GCD value.
VSSD
VSSD
100 nF V
DDD5 38
100 nF V
DDD3 22
100 nF V
DDD1 5
+5 V digital
100 nF V
DDD9 82
100 nF V
DDD7 49
100 nF V
DDD4 29
100 nF V
DDD2 14
X1
27.0 MHz
(3)
3rd harmonic
10
pF
100 nF
100 nF
75 Ω
13 Ω
75 Ω
13 Ω
75 Ω
8Ω
75 Ω
27 Ω
75 Ω
27 Ω
75 Ω
27 Ω
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
MGD674
CHROMA
0.62 V (p-p)(2)
VSSA
Y
1.0 V (p-p)(2)
VSSA
CVBS
1.23 V (p-p)(2)
VSSA
BLUE
0.7 V (p-p)(2)(4)
VSSA
GREEN
0.7 V (p-p)(2)(4)
VSSA
RED
0.7 V (p-p)(2)(4)
Digital Video Encoder (EURO-DENC2)
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
digital
inputs and
outputs
1
nF
10
µH
3.3 V
oscillator
+3.3 V analog
handbook, full pagewidth
VSSD
Philips Semiconductors
Preliminary specification
SAA7182A; SAA7183A
APPLICATION INFORMATION
1996 Oct 02
40
+3.3 V digital
100 nF V
DDD8 76
VDDD6
100 nF
100 nF
100 nF
62
60
51
RI
58
RED
BI
45
BLUE
100 nF
100 nF
100 nF
100 nF
54
53
52
Fig.21 Application environment of the EURO-DENC2; QFP80.
49
2 Ω(1)
2 Ω(1)
2 Ω(1)
2 Ω(1)
2 Ω(1)
2Ω
43
(1)
57
59
61
44
47
50
VSSA1 to VSSA3
41, 55, 64
46
VDDA5 VDDA4 VDDA3 VDDA2 VDDA1
SELI
VSSA
VSSA
VSSA
VSSA
GREEN
48
QI
56
VDDA9 VDDA8 VDDA7 VDDA6
SAA7182A
SAA7183A
34
VSSD1 to VSSD5
and
VSSD7 to VSSD9
6, 14, 20, 29,
39, 67, 69, 74
31
33
32
100
nF
VSSD
XTALO VSSD6
VSSD
XTALI
10
pF
(1) Typical value. (2) For 100⁄100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003. (4) Depending on GY/GCD value.
VSSD
VSSD
100 nF V
DDD5 68
100 nF V
DDD3 28
100 nF V
DDD1 13
+5 V digital
100 nF V
DDD9 70
100 nF V
DDD7 37
100 nF V
DDD4 19
100 nF V
DDD2 5
X1
27.0 MHz
(3)
3rd harmonic
10
pF
100 nF
100 nF
75 Ω
13 Ω
75 Ω
13 Ω
75 Ω
8Ω
75 Ω
27 Ω
75 Ω
27 Ω
75 Ω
27 Ω
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
MGD707
CHROMA
0.62 V (p-p)(2)
VSSA
Y
1.0 V (p-p)(2)
VSSA
CVBS
1.23 V (p-p)(2)
VSSA
BLUE
0.7 V (p-p)(2)(4)
VSSA
GREEN
0.7 V (p-p)(2)(4)
VSSA
RED
0.7 V (p-p)(2)(4)
Digital Video Encoder (EURO-DENC2)
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
digital
inputs and
outputs
1
nF
10
µH
3.3 V
oscillator
+3.3 V analog
handbook, full pagewidth
VSSD
Philips Semiconductors
Preliminary specification
SAA7182A; SAA7183A
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Values for the external series resistors result from a 75 Ω
load (see Figs 20 and 21).
Analog output voltages
The analog output voltages are dependent on the open
loop voltage of the operational amplifiers for full-scale
conversion (typical value 1.4 V), the internal series resistor
(typical value 2 Ω), the external series resistor and the
external load impedance.
The analog inputs RI, GI, and BI are shifted first by an
offset of 0.16 V (typical value), followed by an amplification
of 1.72 (typical value). For an input voltage of 0 to 0.7 V an
open loop output voltage of 0.28 to 1.48 V is achieved,
resulting in Vo = 0.86 V (p-p) with an internal series
resistor of 2 Ω, an external series resistor of 27 Ω at a 75 Ω
load impedance.
The digital output signals in front of the DACs under
nominal conditions occupy different conversion ranges, as
indicated in Table 40 for a 100⁄100 colour bar signal.
Table 40 Digital output signals conversion range
CONVERSION RANGE (peak-to-peak
CVBS, SYNC
TIP-TO-PEAK CARRIER
(digits)
Y (VBS) SYNC TIP-TO-WHITE
(digits)
RGB (Y)
BLACK-TO-WHITE AT GDY = GDC = −6
(digits)
1023
888
712
1996 Oct 02
41
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PACKAGE OUTLINES
PLCC84: plastic leaded chip carrier; 84 leads
SOT189-2
eD
eE
y
X
74
A
54
53 Z E
75
bp
b1
w M
84
1
HE
E
pin 1 index
e
A
A4 A1
(A 3)
β
11
k1
33
Lp
k
detail X
12
32
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
k1
max.
Lp
v
w
y
0.51
1.44
1.02
0.18
0.18
0.10
Z D(1) Z E (1)
max. max.
UNIT
A
A1
min.
A3
A4
max.
bp
b1
mm
4.57
4.19
0.51
0.25
3.30
0.53
0.33
0.81
0.66
0.180
0.020 0.01
0.165
0.13
1.130 1.130 1.195 1.195 0.048
0.057
0.021 0.032 1.158 1.158
0.020
0.05
0.007 0.007 0.004 0.085 0.085
1.090 1.090 1.185 1.185 0.042
0.040
0.013 0.026 1.150 1.150
inches
D (1)
E (1)
e
eD
eE
HD
HE
k
29.41 29.41
28.70 28.70 30.35 30.35 1.22
1.27
29.21 29.21
27.69 27.69 30.10 30.10 1.07
2.16
β
2.16
45 o
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-03-11
SOT189-2
1996 Oct 02
EUROPEAN
PROJECTION
42
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
c
y
X
64
A
41
40
65
ZE
e
Q
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
80
L
25
detail X
24
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
3.2
0.25
0.05
2.90
2.65
0.25
0.45
0.30
0.25
0.14
20.1
19.9
14.1
13.9
0.8
24.2
23.6
18.2
17.6
1.95
1.0
0.6
1.4
1.2
0.2
0.2
0.1
Z D (1) Z E (1)
1.0
0.6
1.2
0.8
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-12-15
95-02-04
SOT318-2
1996 Oct 02
EUROPEAN
PROJECTION
43
o
7
0o
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
• The package footprint must incorporate solder thieves at
the downstream corners.
SOLDERING
Introduction
QFP
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Reflow soldering techniques are suitable for all PLCC and
QFP packages.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
The choice of heating method may be influenced by larger
PLCC or QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
METHOD (PLCC AND QFP)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Wave soldering
PLCC
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
1996 Oct 02
SAA7182A; SAA7183A
44
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Oct 02
45