INTEGRATED CIRCUITS DATA SHEET SAB9083 Multistandard Picture-In-Picture (PIP) controller Preliminary specification Supersedes data of 1999 Feb 18 File under Integrated Circuits, IC02 1999 Nov 12 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 FEATURES • Double window Picture-In-Picture (PIP) in interlaced or non-interlaced mode at 8-bit resolution • Internal 1-Mbit DRAM • Three 8-bit Analog-to-Digital Converters (ADCs) (7-bit performance) with clamp circuit for each acquisition channel The conversion to the digital environment is done on chip with ADCs. Processing and storage of the video data is done entirely in the digital domain. The conversion back to the analog domain is done by means of DACs. Internal clocks are generated by PLLs which lock on to the applied horizontal and vertical syncs. • One PLL which generates the line-locked clocks for the subchannel • One PLL which generates the line-locked clocks for the main and display channels • Three 8-bit Digital-to-Analog Converters (DACs) The main input channel is compressed horizontally by a factor of two and directly fed to the output. After compression, a horizontal expansion of two is possible for the main channel. • Linear zoom in both horizontal and vertical directions for the subchannel • Linear zoom in horizontal direction for the main channel The subchannel is also compressed horizontally by a factor of two but stored in memory before it is fed to the outputs. • Three multistandard PIP modes are available. GENERAL DESCRIPTION The SAB9083 can also create three multistandard PIP modes, one with three PIPs placed in a column (MP3) and two with two columns of three PIPs (MP6, MP6S). The reduction factors of these PIPs are horizontal 1⁄4 and vertical 1⁄3. In the first two modes, the column(s) can be placed on the left or right side of the screen. The SAB9083 is a multistandard PIP controller which can be used in double window applications. The SAB9083 inserts one or two live video signals with reduced size into another live video signal. The incoming video signals are expected to be analog baseband signals. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDD VDDA IDDD IDDA digital supply voltage analog supply voltage digital supply current analog supply current 3.0 3.0 − 140 3.3 3.3 50 165 3.6 3.6 − 210 V V mA mA − − − − 28 4 − 0.7 − − 4 − MHz kHz ns PLL fclk(sys) Bloop tjitter ζ system clock frequency loop bandwidth short term stability damping factor 1792 × fHSYNC peak-to-peak jitter for 64 µs ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAB9083H 1999 Nov 12 QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm 2 VERSION SOT317-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SV SY Vbias(SA) Vref(T)(SA) Vref(B)(SA) SHSYNC SVSYNC 5 6 7 14 15 16 17 20 39 40 41 42 61 64 65 66 67 76 77 78 85 86 79 8 81 10 HORIZONTAL AND VERTICAL FILTER 83 CLAMP AND ADC 84 82 12 DAC AND BUFFER 9 11 80 13 69 87 PLL AND CLOCK GENERATOR 72 LINE MEMORY DISPLAY CONTROL INTERNAL DRAM 68 3 18, 19 MU MY MV Vbias(MA) Vref(T)(MA) Vref(B)(MA) DHSYNC DVSYNC 2 2 98 30 100 HORIZONTAL FILTER CLAMP AND ADC 97 SAB9083 99 71 CONTROL 32 to 37 19 90 91 92 95 96 6 75 74 73 88 93 44 43 45 46 Vref(B)(DA) PKOFF FBL VSSD(T1) and VSSD(T2) VSSD(T3) DCLK TC T5 to T0 47 MGL584 VDDA(SP) VSSA(DP) VDDA(DP) VSSD(MA) n.c. SDA POR Fig.1 Block diagram. T6 SCL T7 TM TCBD TCLK TCBR TCBC SAB9083 VSSA(SP) VDDD(MA) Preliminary specification 89 21 to 29, 31, 52 to 60 Vref(T)(DA) VSSD(T8) and VSSD(T9) 38 TEST CONTROL Vbias(DA) 62, 63 94 70 DU VSSD(T4) to VSSD(T7) 4 I2C-BUS DV 48 to 51 1 PLL AND CLOCK GENERATOR DY Philips Semiconductors SU 4 VDDD(D) VSSA(SA) VSSD(SA) Multistandard Picture-In-Picture (PIP) controller VSSD(D) VDDA(SA) VDDA(SF) VDDD(SA) VDDA(MF) VDDA(MA) VSSA(DA) VSSD(DA) VDDD(P1) VDDD(RL) VSSD(RM) VSSD(RP) VSSD(P2) 3 BLOCK DIAGRAM handbook, full pagewidth 1999 Nov 12 VSSA(MA) VDDA(DA) VDDD(DA) VSSD(P1) VDDD(RP) VSSD(RL) VDDD(RM) VDDD(P2) Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 PINNING SYMBOL PIN TYPE DESCRIPTION Vref(B)(MA) 1 I/O MU 2 I analog U input for main channel VDDA(MF) 3 S analog supply voltage for main channel front-end buffers VSSA(MA) 4 S analog ground for main channel ADCs VDDA(MA) 5 S analog supply voltage for main channel ADCs VDDA(DA) 6 S analog supply voltage for DACs VSSA(DA) 7 S analog ground for DACs DY 8 O analog Y output of DAC Vbias(DA) 9 I/O input/output analog bias reference voltage for DACs analog bottom reference voltage for main channel ADCs DV 10 O analog V output of DAC Vref(T)(DA) 11 I/O input/output analog top reference voltage for DACs DU 12 O analog U output of DAC Vref(B)(DA) 13 I/O analog bottom reference voltage for DACs VDDD(DA) 14 S digital supply voltage for DACs VSSD(DA) 15 S digital ground for DACs VSSD(P1) 16 S digital ground for periphery VDDD(P1) 17 S digital supply voltage for periphery VSSD(T1) 18 S digital ground for test VSSD(T2) 19 S digital ground for test 20 S digital supply voltage for memory periphery 21 to 29 − not connected VSSD(T3) 30 S digital ground for test not connected VDDD(RP) n.c. n.c. 31 − T5 32 I/O test data input/output bit 5 (CMOS levels) T4 33 I/O test data input/output bit 4 (CMOS levels) T3 34 I/O test data input/output bit 3 (CMOS levels) T2 35 I/O test data input/output bit 2 (CMOS levels) T1 36 I/O test data input/output bit 1 (CMOS levels) T0 37 I/O test data input/output bit 0 (CMOS levels) TC 38 I test control input (CMOS levels) VDDD(RL) 39 S digital supply voltage for memory logic VSSD(RL) 40 S digital ground for memory logic VSSD(RM) 41 S digital ground for memory core VDDD(RM) 42 S digital supply voltage for memory core TCLK 43 I test clock input (CMOS levels) TM 44 I test mode input (CMOS levels) TCBD 45 I test control block data input (CMOS levels) TCBC 46 I test control block clock input (CMOS levels) 47 I test control block reset input (CMOS levels) 48 to 51 S digital ground for test TCBR VSSD(T4) to VSSD(T7) 1999 Nov 12 4 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SYMBOL n.c. VSSD(RP) PIN TYPE 52 to 60 − SAB9083 DESCRIPTION not connected 61 S digital ground for memory periphery 62 and 63 S digital ground for test VDDD(P2) 64 S digital supply voltage for periphery VSSD(P2) 65 S digital ground for periphery VSSD(D) 66 S digital ground for digital core VDDD(D) 67 S digital supply voltage for digital core FBL 68 O fast blanking control signal output (CMOS levels; +5 V tolerant) PKOFF 69 O peak off control signal output (CMOS levels; +5 V tolerant) DVSYNC 70 I vertical sync display channel input (CMOS levels; +5 V tolerant) DCLK 71 I test clock input (28 MHz; CMOS levels) VSSD(T8) and VSSD(T9) SVSYNC 72 I vertical sync for subchannel input (CMOS levels; +5 V tolerant) SCL 73 I/O input/output serial clock (I2C-bus; CMOS levels; +5 V tolerant) SDA 74 I/O input/output serial data/acknowledge output (I2C-bus; +5 V tolerant) POR 75 I power-on reset input (CMOS levels; pull-up resistor connected to VDD) VDDA(SA) 76 S analog supply voltage for subchannel ADCs VSSA(SA) 77 S analog ground for subchannel ADCs VDDA(SF) 78 S analog supply voltage for subchannel front-end buffers and clamps SU 79 I analog U input for subchannel Vref(B)(SA) 80 I/O SV 81 I Vref(T)(SA) 82 I/O SY 83 I Vbias(SA) 84 I/O VSSD(SA) 85 S digital ground for subchannel ADCs VDDD(SA) 86 S digital supply voltage for subchannel ADCs SHSYNC 87 I horizontal sync input for subchannel (Vi < VSHSYNC) T6 88 I/O test data input/output bit 7 (CMOS levels) VDDA(SP) 89 S analog supply voltage for subchannel PLL VSSA(SP) 90 S analog ground for subchannel PLL VSSA(DP) 91 S analog ground for display channel PLL VDDA(DP) 92 S analog supply voltage for display channel PLL T7 93 I/O input/output analog bottom reference voltage for subchannel ADCs analog V input for subchannel input/output analog top reference voltage for subchannel ADCs analog Y input for subchannel analog bias reference voltage for subchannel ADCs test data input/output bit 6 (CMOS levels) DHSYNC 94 I horizontal sync input for display channel (Vi < VDHSYNC) VDDD(MA) 95 S digital supply voltage for main channel ADCs VSSD(MA) 96 S digital ground for main channel ADCs Vbias(MA) 97 I/O MY 98 I Vref(T)(MA) 99 I/O MV 100 I 1999 Nov 12 analog bias reference voltage for main channel ADCs analog Y input for main channel analog top reference voltage for main channel ADCs analog V input for main channel 5 Philips Semiconductors Preliminary specification 81 SV 82 Vref(T)(SA) 83 SY 84 Vbias(SA) 85 VSSD(SA) 86 VDDD(SA) 87 SHSYNC 88 T6 89 VDDA(SP) SAB9083 91 VSSA(DP) 90 VSSA(SP) 92 VDDA(DP) 93 T7 94 DHSYNC 95 VDDD(MA) 97 Vbias(MA) 96 VSSD(MA) 98 MY 100 MV handbook, full pagewidth 99 Vref(T)(MA) Multistandard Picture-In-Picture (PIP) controller Vref(B)(MA) 1 80 Vref(B)(SA) MU 2 79 SU VDDA(MF) 3 78 VDDA(SF) VSSA(MA) VDDA(MA) 4 77 VSSA(SA) 5 76 VDDA(SA) VDDA(DA) VSSA(DA) 6 75 POR 7 74 SDA DY 8 73 SCL Vbias(DA) 9 72 SVSYNC DV 10 71 DCLK Vref(T)(DA) 11 70 DVSYNC DU 12 69 PKOFF Vref(B)(DA) 13 68 FBL VDDD(DA) 14 VSSD(DA) 15 67 VDDD(D) 66 VSSD(D) SAB9083 VSSD(P1) 16 VDDD(P1) 17 65 VSSD(P2) 64 VDDD(P2) VSSD(T1) 18 VSSD(T2) 19 63 VSSD(T9) 62 VSSD(T8) VDDD(RP) 20 61 VSSD(RP) n.c. 21 60 n.c. n.c. 22 59 n.c. n.c. 23 58 n.c. n.c. 24 57 n.c. n.c. 25 56 n.c. n.c. 26 55 n.c. n.c. 27 54 n.c. n.c. 28 53 n.c. n.c. 29 52 n.c. VSSD(T3) 30 Fig.2 Pin configuration. 1999 Nov 12 6 VSSD(T6) 50 VSSD(T5) 49 VSSD(T4) 48 TCBR 47 TCBC 46 TCBD 45 TM 44 TCLK 43 VDDD(RM) 42 VSSD(RM) 41 VSSD(RL) 40 VDDD(RL) 39 T0 37 TC 38 T1 36 T2 35 T3 34 T4 33 T5 32 n.c. 31 51 VSSD(T7) MGL585 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 FUNCTIONAL DESCRIPTION The starting-point of the acquisition can be controlled with the acquisition fine positioning added to a system constant. With a nominal input fHSYNC and standard NTSC signals, 1408 samples (active video) are acquired and processed by the SAB9083. Here, the nominal input fHSYNC results in a nominal system clock frequency of 1792 × fHSYNC (approximately 28 MHz). Acquisition The internal pixel rate is 28 MHz for the Y, U and V channels. It is expected that the bandwidth of the input signals will be limited to 4.5 MHz for the Y input and 1.125 MHz for the U and V inputs. Inset synchronisation is achieved via the acquisition HSYNC and VSYNC pins of the main channel. The display is driven by the main channel clock. PIP modes handbook, full pagewidth SUB MAIN SUB SUB MAIN MGM810 MAIN REPLAY Fig.3 PIP modes. 1999 Nov 12 7 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 handbook, full pagewidth S0 S0 S1 S1 S2 S2 S0 S1 S2 S3 S4 S5 S4 S1 S2 S3 S4 S5 S0 S0 S1 MAIN MAIN S1 MAIN S2 S0 S2 MAIN S0 MAIN S2 S1 S0 S1 S0 S1 S3 S2 S3 S2 S3 S5 S4 S5 S4 S5 MGL587 S0 S1 S2 S3 S4 S5 Fig.4 Multistandard PIP modes. I2C-bus control is according to the I2C-bus protocol: first, a START sequence must be put on the I2C-bus Then, the I2C-bus address of the circuit must be sent, followed by a subaddress. After this sequence, the data of the subaddresses must be sent. An auto-increment function gives the option of sending data of the incremented subaddresses until a STOP sequence is sent. Table 1 gives an overview of the I2C-bus addresses. The data bits that are not used should be set to zero. I2C-bus description The I2C-bus provides bidirectional 2-line communication between different ICs. The SDA line is the serial data line and the SCL the serial clock line. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. The SAB9083 has the I2C-bus address 2CH. Valid subaddresses are 00H to 18H, register 15H (except bits 7 and 6) and registers 16H to 18H are reserved for future extensions. 1999 Nov 12 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 9 00H MPIPON SPIPON S1FLD SFreeze DNonint PipMode2 PipMode1 PipMode0 01H SHBlow1 SHBlow0 SHRed5 SHRed4 SHRed3 SHRed2 SHRed1 SHRed0 02H SVBlow SVRed6 SVRed5 SVRed4 SVRed3 SVRed2 SVRed1 SVRed0 03H BGVfp3 BGVfp2 BGVfp1 BGVfp0 BGHfp3 BGHfp2 BGHfp1 BGHfp0 04H SDHfp7 SDHfp6 SDHfp5 SDHfp4 SDHfp3 SDHfp2 SDHfp1 SDHfp0 05H SDVfp7 SDVfp6 SDVfp5 SDVfp4 SDVfp3 SDVfp2 SDVfp1 SDVfp0 06H SHPic7 SHPic6 SHPic5 SHPic4 SHPic3 SHPic2 SHPic1 SHPic0 07H SVPic7 SVPic6 SVPic5 SVPic4 SVPic3 SVPic2 SVPic1 SVPic0 08H MAHfp3 MAHfp2 MAHfp1 MAHfp0 SAHfp3 SAHfp2 SAHfp1 SAHfp0 09H SAVfp7 SAVfp6 SAVfp5 SAVfp4 SAVfp3 SAVfp2 SAVfp1 SAVfp0 0AH DUVPol DVSPol DFPol DHsync SUVPol SVSPol SFPol SHsync 0BH MainFidPos7 MainFidPos6 MainFidPos5 MainFidPos4 MainFidPos3 MainFidPos2 MainFidPos1 MainFidPos0 0CH SubFidPos7 SubFidPos6 SubFidPos5 SubFidPos4 SubFidPos3 SubFidPos2 SubFidPos1 SubFidPos0 0DH BGOn BOn MFidPOn SFidPOn Prio AlgOff SFBlkPkOff1 SFBlkPkOff0 0EH BSel1 BSel0 SBBrt1 SBBrt0 − SBCol2 SBCol1 SBCol0 0FH DPal SPal SLSel5 SLSel4 SLSel3 SLSel2 SLSel1 SLSel0 10H I2CHold SV1 SDSel5 SDSel4 SDSel3 SDSel2 SDSel1 SDSel0 11H MDHfp7 MDHfp6 MDHfp5 MDHfp4 MDHfp3 MDHfp2 MDHfp1 MDHfp0 12H MDVfp7 MDVfp6 MDVfp5 MDVfp4 MDVfp3 MDVfp2 MDVfp1 MDVfp0 13H MHBlow SV2 MHRed5 MHRed4 MHRed3 MHRed2 MHRed1 MHRed0 14H − VBwidth2 VBWidth1 VBWidth0 SV3 HBWidth2 HBWidth1 HBWidth0 15H DNTSC SNTSC all bits are reserved all bits are reserved SAB9083 Preliminary specification 16H to 18H Philips Semiconductors DATA BYTES SUB ADDRESS Multistandard Picture-In-Picture (PIP) controller 1999 Nov 12 Table 1 Overview of I2C-bus addresses For a description of the various data bits, see the following pages. Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 Table 2 MPIPON (DOUBLE WINDOW) Bit MPIPON is used to switch the main channel PIP on (logic 1) or off (logic 0). SPIPON Bit SPIPON is used to switch the subchannel PIPs on (logic 1) or off (logic 0). PRIO The priority bit decides whether the main channel PIP (Prio set to logic 0) or the subchannel PIP (Prio set to logic 1) will be on top when both PIPs overlap. PIP modes PipMode<2:0> MODE 000 double window mode 001 replay PIP 010 multistandard PIP 3 011 multistandard PIP 6 100 reserved 111 multistandard PIP 6 split SHRED AND SVRED (DOUBLE WINDOW) Bits SHRed<5:0> and SVRed<6:0> determine the reduction factor in the double window mode. S1FLD The horizontal reduction is equal to SHRed/96; the vertical reduction is equal to SVRed/96. SHRed should lie in the range from 0 to 48; if set to logic 0, the PIP is off. SVRed should lie in the range from 0 to 96; if set to logic 0, the PIP is off. If S1FLD is set to logic 0, two fields are used for the live PIP. When a 50/60 Hz or a 60/50 Hz mode is detected, the SAB9083 automatically switches to the 1-Field mode (1-Field resolution vertically). If S1FLD is set to logic 1, only one field is used. This causes joint line errors but saves memory. This bit should not be set in normal modes. When the horizontal reduction factor is 48/96, 704 samples are processed. The horizontal reduction factor is linear; therefore, when it is 24/96, 352 samples are processed. The same holds for the vertical reduction factor but then with the number of lines. For NTSC, the number of processed lines can be calculated from SVRed/96 × 228 lines; for PAL, this is SVRed/96 × 276 lines. SFREEZE With SFreeze set to logic 1, the current live subchannel PIP will be frozen. If set to logic 0, it is unfrozen. ALGOFF SHRED AND SVRED (REPLAY) In double window mode, precautions are taken to prevent a joint line error. Under some conditions, this feature should be switched off. This can be realized by setting this bit to logic 1. Normally, bit AlgOff should be set to logic 0. Bit SV3, when set to logic 0, can overrule the AlgOff bit. It is recommended to set SV3 to logic 1. In replay mode, the range of SHRed and SVRed is limited as follows: SHRed = 12; SVRed = 24, 16 or 12. This leads to a fixed horizontal reduction factor of 1⁄8; and to a variable vertical reduction factor of 1⁄4, 1⁄6 or 1⁄8. Note that the resulting replay PIP can be expanded by using SHBlow and/or SVBlow. DNONINT SHPIC AND SVPIC (MULTISTANDARD PIP MODES) In normal mode (this bit is logic 0), the SAB9083 calculates whether a signal is non-interlaced and reacts accordingly. With bit DNonint set to logic 1, the display channel is forced into the non-interlaced mode. In the non-interlaced mode, only one field is used during the processing of the PIPs. Bytes SHPic and SVPic control the picture size in the multistandard PIP modes. The horizontal range is 256 steps of four 28 MHz clock periods. The vertical range is 256 steps of 1 line/field. PIPMODE In the double window and replay PIP modes, the picture size is determined by the reduction factors (SHRed and SVRed) and bits HBlow and VBlow. The PIP modes for the SAB9083 are shown in Table 2. 1999 Nov 12 10 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller BGHFP AND BGVFP SAB9083 field identification position fine tuning. The default value is off (logic 0), no fine positioning. When on (logic 1), the field identification position is determined by the value of MainFidPos and SubFidPos. These bits control the horizontal and vertical positioning of the PIP configuration on the screen. The horizontal range is adjustable in 16 steps of four 28 MHz clock periods. The vertical range is 16 steps of 1 line/field. The background colour can be adjusted with bits BSel, SBBrt and SBCol. BGON Bit BGOn determines whether the background is visible. The background has a size of 720 pixels and 240 lines for NTSC and 720 pixels and 288 lines for PAL. The background colour can be adjusted with bits BSel, SBBrt and SBCol. SDHFP AND SDVFP These bytes control the horizontal and vertical positioning of the subchannel PIPs on the screen. The horizontal range is 256 steps of eight 28 MHz clock periods. The vertical range is 256 steps of 1 line/field. BON, SBBRT, SBCOL AND BSEL Bit BOn can switch the sub-borders on (logic 1) or off (logic 0). Bits SBBrt<1:0> and SBCol<2:0> set the brightness and colour type of the selected border. The brightness is set in four levels: 30%, 50%, 70% and 100% IRE. The colour type is one of black (grey), blue, red, magenta, green, cyan, yellow or white (grey). For black and white, a finer scale is available. MAHFP, SAHFP AND SAVFP Bits MAHfp<3:0>, bits SAHfp<3:0> and byte SAVfp control the horizontal and vertical inset starting-points of the acquired data. The horizontal range is 16 steps of eight 28 MHz clock periods when SV2 is set to logic 1. When SV2 set to logic 0, the horizontal range is restricted to eight steps. The vertical range is 256 steps of 1 line/field. Bits BSel<1:0> select which colour is set, background or border, see Table 3. DUVPOL, DVSPOL, DFPOL AND DHSYNC Table 3 These bits control the PLL/deflection settings. With DUVPol, the polarity of the border UV signals can be inverted when the deflection circuit after the SAB9083 expects inverted signals. BSel<1:0> With DVSPol set to logic 0, the SAB9083 triggers on positive edges of the DVSYNC. If DVSPol is set to logic 1, it triggers on negative edges. Bit DFPol can invert the field ID of the incoming fields. Bit DHsync determines the timing of the DHSYNC pulse. If it is set to logic 0, a burstkey is expected and if it is set to logic 1, a horizontal sync is expected at pin DHSYNC. BORDER COLOUR SET 00 main 01 sub 10 background 11 sub-border select MDHFP AND MDVFP These bytes control the horizontal and vertical positioning of the main PIP on the screen. The horizontal range is 256 steps of eight 28 MHz clock periods. The vertical range is 256 steps of 1 line/field. SUVPOL, SVSPOL, SFPOL AND SHSYNC These bits control the PLL/decoder settings. With SUVPol, the polarity of the video UV signals can be inverted when the decoder circuit before the SAB9083 emits inverted signals. With SVSPol set to logic 0, the SAB9083 triggers on positive edges of the SVSYNC. If it is set to logic 1, it triggers on the negative edges. Bit SFPol can invert the field ID of the incoming fields. Bit SHsync determines the timing of the SHSYNC pulse. If it is set to logic 0, a burstkey is expected and if it is set to logic 1, a horizontal sync is expected at pin SHSYNC. MHRED Bits MHRed<5:0>, in a range from 0 to 48, determine the horizontal reduction factor MHRed/96. If they are set to logic 0, the PIP is off. If they are set to the maximum value of 48, the horizontal reduction factor is 0.5. SHBLOW AND SVBLOW (REPLAY MODE) Bits SHBlow<1:0> and bit SVBlow are used in the replay mode. These bits can expand a pixel on the display side by a factor two (01) or four (11) in the horizontal direction (SHBlow) and a factor of two (1) in the vertical direction (SVBlow). Zero values indicate no expansion. MFIDPON AND SFIDPON Bits MFidPOn (main field identification position on) and SFidPOn (subfield identification position on) enable the 1999 Nov 12 BSel modes 11 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller MHBLOW SAB9083 Table 4 Bit MHBlow can expand the main picture by a factor of two in the horizontal direction. SFBlkPkOff<1:0> SHIFT OF FBL AND PKOFF 00 no shift 01 +0.5 pixel 10 −0.5 pixel 11 −1 pixel SLSEL (REPLAY MODE) In the replay PIP mode, bits SLSel<5:0> determine at which memory location the PIP data is written, the range depends on the memory usage for each PIP. The maximum number of PIPs that can be stored in NTSC mode is 42. Shifts of FBLK and PKOff I2CHOLD Bit I2CHold controls the updating of the I2C-bus controlled function towards the PIP. If set to logic 1, some updates are on hold until the bit is set to logic 0. At the next main Vsync, all settings are passed to the PIP functions. SLSEL (MULTISTANDARD PIP MODES) Bits SLSel<5:0> select which of the PIPs in a multistandard PIP mode is live. In MP3 modes, SLSel must be in the range from 0 to 2. In all MP6 modes, SLSel must be in the range from 0 to 5. The bits and bytes that are on hold when bit I2CHold is set to logic 1 are: • MPIPON, SPIPON, DNonint and PipMode • SHBlow and SVBlow SDSEL (REPLAY MODE) • SHRed and SVRed Bits SDSel<5:0> select which PIP is read from memory. Valid numbers are dependent on the maximum value of SLSel. • BGHfp and BGVfp • SDHfp and SDVfp • SHPic and SVPic DPAL AND SPAL • BGOn, BOn and Prio In normal operation (DPal and SPal are logic 0), the SAB9083 calculates from the number of incoming lines whether the signal is NTSC (< 288 lines) or PAL (≥ 288 lines). If DPal is set to logic 1, the main window is sized to 276 lines. If DPal is set to logic 1 and the subchannel is still NTSC, the subchannel picture will be smaller than the main channel picture (difference of approximately 40 lines). If SPal is set to logic 1, the subchannel is forced to PAL mode and 276 lines are acquired instead of 228 in NTSC mode. • BSel, SBBrt and SBCol • SDSel • MDHfp and MDVfp • HBWidth and VBWidth. SV1 Bit SV1 controls the internal horizontal offset of the background. When set to logic 0, the offset is 0.86 µs; when set to logic 1, the offset is 4.56 µs. DNTSC AND SNTSC SV2 In normal operation (DNTSC and SNTSC are logic 0), the SAB9083 calculates from the number of incoming lines whether the signal is NTSC (< 288 lines) or PAL (≥ 288 lines). If DNTSC is set to logic 1, the main window is sized to 228 lines. If DNTSC is set to logic 1 and the subchannel is still PAL, the subchannel picture will be larger than the main channel picture (difference of approximately 40 lines). If SNTSC is set to logic 1, the channel is forced to NTSC mode and 228 lines are acquired instead of 276 in PAL mode. Bit SV2, when set to logic 0, limits the range of the MAHfp and SAHfp parameters. Otherwise (bit SV2 set to logic 1), the parameters have their maximum range (which is recommended). SV3 Bit SV3, when set to logic 0, can overrule bit AlgOff when the main channel is NTSC and the subchannel is PAL. In this particular case, bit AlgOff is always set to logic 0 internally. Otherwise (bit SV3 set to logic 1), bit AlgOff is never overruled. It is recommended to set SV3 to logic 1. SFBLKPKOFF Bits SFBlkPkOff<1:0> shift signals FBL and PKOFF with respect to the YUV output, by half pixels, see Table 4. 1999 Nov 12 12 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 8. Mixed PAL/NTSC multistandard PIP modes are available by setting bit DNTSC to logic 1 when the main picture is PAL and the subpicture is NTSC. In this way, the display channel is forced to operate in NTSC mode and the lower parts of the original PAL main picture (approximately 40 lines) will not be displayed. Because the screen will not be filled completely in the vertical direction, the use of a black background is suggested here. The picture can be centred by changing the value of the SAVfp bits. HBWIDTH AND VBWIDTH Bits HBWidth<2:0> and VBWidth<2:0>control the horizontal and vertical border sizes in steps of two pixels and one line. The default horizontal border size is four pixels and the vertical border size is two lines per field. Default means after power-up and no I2C-bus data sent to the PIP controller. In MP6 mode, the minimum value of HBWidth is two. NOTES Acquisition channel ADCs and clamping 1. When the input signals for the main and/or subchannel are non-interlaced, joint line errors can occur. When non-interlaced signals are input, the SAB9083 switches automatically to the non-interlaced mode. The analog input signals are converted to digital signals by three ADCs per channel. The resolution of the ADCs is 8 bits (DNL is 7 bits and INL is 6 bits) and the sampling is performed at the system clock frequency of 28 MHz for the Y input. A bias voltage (Vbias) is used to decouple the AC components on internal references. 2. When the prevent joint line error algorithm is switched off (AlgOff is set to logic 1), joint line errors can still occur in the 2-Field mode. The inputs should be AC coupled and an internal clamp circuit (using external clamp capacitors) will clamp the input to a level derived internally from Vref(B)(MA/SA) for the luminance channels and, for the chrominance channels, to (Vref(T)(MA/SA) + Vref(B)(MA/SA))/2 + LSB/2. The clamping starts at the active edge of the burst key. Internal video buffers amplify the standard Y, U and V input signals to the correct ADC levels. 3. When a PAL signal is applied to the main channel and an NTSC signal is applied to the subchannel, the subchannel will automatically enter the 1-Field mode. Now, a joint line error can occur. In the PAL/NTSC mode, the subpicture will be smaller than the main picture (difference of approximately 40 lines). 4. When an NTSC signal is applied to the main channel and a PAL signal is applied to the subchannel, the subchannel will automatically enter the 1-Field mode. Now, a joint line error can occur. In the NTSC/PAL mode, the subpicture will be larger than the main picture (difference of approximately 40 lines): PLL The PLL generates an internal system clock of 1792 × fHSYNC, from fHSYNC, which is approximately 28 MHz. 5. The multistandard PIP modes are not meant for mixing PAL and NTSC PIPs. DACs and video buffers 6. In all MP6 modes, the live PIP is displayed in the 1-Field mode when the input signal is PAL. This means that joint line errors can occur in the live PIP when the input signal is PAL. The 28 MHz digital video signals are fed to the 8-bit DACs that produce the required analog video signals. The video buffers amplify these signals prior to being fed to the output to drive another device. 7. Mixed NTSC/PAL multistandard PIP modes are available by setting bit SNTSC to logic 1 when the main picture is NTSC and the subpicture is PAL. In this way, the subchannel is forced to operate in NTSC mode and the lower parts of the original PAL subchannel PIPs (approximately 40 lines) will not be displayed. The picture can be centred by changing the value of the SAVfp bits. 1999 Nov 12 13 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage range −0.5 5.0 V Tstg storage temperature −25 +150 °C Tamb ambient temperature 0 70 °C Vesd electrostatic discharge handling − 2 kV Rth(j-a) thermal resistance − 45 K/W Pmax maximum power dissipation − 1.0 W QUALITY SPECIFICATION In accordance with “SNW-FQ-611, Part E”, dated 14 December 1992. ESD LEVELS The standard ESD specification is JEDEC Class II (2 kV Human Body Model, 200 V Machine Model) unless indicated otherwise. Table 5 ESD performance PIN SYMBOL HUMAN BODY MODEL (V) 68 FBL 1000 69 PKOFF 1000 70 DVSYNC 1000 72 SVSYNC 1000 73 SCL 1000 74 SDA 1000 all other pins standard specification rest in range 1 to 17 rest in range 64 to 100 1999 Nov 12 14 MACHINE MODEL (V) standard specification Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 ANALOG CHARACTERISTICS VDDA = 3.3 V; VDDD = 3.3 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA positive supply voltage 3.0 3.3 3.6 V VSSA ground voltage − 0 − V ∆VDDA(max) maximum DC difference between supply voltages − 0 100 mV ∆VSSA(max) maximum DC difference between ground voltages − 0 100 mV IDDD(q) quiescent current of digital supply voltages − 0 50 µA IDDA(DP) display PLL supply current − 0.4 − mA IDDA(SP) sub PLL supply current − 0.4 − mA note 1 IDDA(MA) main ADCs supply current note 2 60 70 90 mA IDDA(SA) sub ADCs supply current note 2 60 70 90 mA IDDA(DA) DACs supply current 8 10 12 mA IDDA(MF) main buffers supply current 4 6 9 mA IDDA(SF) sub buffers supply current 4 6 9 mA IDDA(tot) total analog supply current 140 165 210 mA IDDD(tot) total digital supply current − 50 − mA 2.70 2.82 2.95 V note 2 Analog-to-digital converter and clamping Vref(T) top reference voltage note 3 Vref(B) bottom reference voltage note 3 0.95 1.07 1.20 V ViY(p-p) Y input signal amplitude (peak-to-peak value) note 4 − 1.00 1.04 V Vi(V)(p-p) V input signal amplitude (peak-to-peak value) note 4 − 1.05 1.10 V Vi(U)(p-p) U input signal amplitude (peak-to-peak value) note 4 − 1.33 1.38 V Ii input current clamping off − 0.1 − µA clamping on − 55 − µA − 5 − pF − 1792 × fHSYNC − kHz 8 8 8 bit Ci input capacitance fsample sample frequency RES resolution note 5 DNL differential non-linearity −1.4 − +1.4 LSB INL integral non-linearity −2.0 − +2.0 LSB αcs channel separation − 48 − dB Vclamp(Y) Y clamping voltage level note 6 1.25 1.34 1.45 V Vclamp(U,V) U/V clamping voltage level note 7 1.80 1.93 2.15 V 1999 Nov 12 15 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SYMBOL PARAMETER SAB9083 CONDITIONS MIN. TYP. MAX. UNIT Digital-to-analog converter and output stage Vref(T) top reference voltage 1.10 1.20 1.30 V Vref(B) bottom reference voltage 0.15 0.23 0.30 V RL load resistance 1 − 1000 kΩ CL load capacitance 0 − 5 pF fsample sample frequency − 1792 × fHSYNC − kHz RES resolution 8 8 8 bit note 8 DNL differential non-linearity −1.0 − +1.0 LSB INL integral non-linearity −1.0 − +1.0 LSB αcs channel separation − 48 − dB NTSC 14 15.75 17 kHz PAL 14 15.625 17 kHz NTSC 14 15.75 17 kHz PAL 14 15.625 17 kHz Display PLL and clock generation fi(PLL) input frequency Sub PLL and clock generation fi(subPLL) input frequency Notes 1. Digital clocks are silent, input pins POR and TM are connected to VDDA. 2. This value is measured with an external bias resistor of 39 kΩ resulting in a bias current of 55 µA. 3. Voltages Vref(T) and Vref(B) are made by a resistor division of VDDA. They can be calculated with the formulas: 2.82 1.07 V ref(T) = V DDA × ------------------------- V and V ref(B) = V DDA × ------------------------- V . V DDA(nom) V DDA(nom) 4. The input signals are amplified to meet an internal peak-to-peak voltage level of 0.8 × (Vref(T) − Vref(B)), which equals the internal ADC input range. 5. The internal system clock frequency is 1792 × fHSYNC of the input channel. 6. The Y clamp level is not equal to the Vref(B) of the ADCs. V ref ( B ) + V ref ( T ) + V LSB 7. The UV channels are clamped to: ------------------------------------------------------------ . 2 8. The internal system clock frequency is 1792 × fHSYNC of the main channel. 1999 Nov 12 16 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 DIGITAL CHARACTERISTICS VDDA = 3.3 V; VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC characteristics VIH HIGH-level input voltage default 0.8VDDD − VDDD + 0.5 V pin 74 0.8VDDD − 5.5(1) V 5 V tolerant pins 68, 69, 70, 72, 73 0.8VDDD − 5.5(1) −0.5 − 0.2VDDD V 0.8 − − V 0.85VDD − − V VIL LOW-level input voltage Vhys hysteresis voltage VOH HIGH-level output voltage IOH = −X mA; VDDD = 3.0 V; note 2 VOL LOW-level output voltage IOL = X mA; VDDD = 3.0 V; note 2 − − 0.4 V IOL = 2 mA; VDDD = 3.0 V − − 0.4 V VI = 0 V − − 1 µA VI = VDDD − − 1 µA |ILI| input leakage current default D |IOZ| 3-state output leakage current VO = 0 V or VO = VDDD − − 1 µA Ilu(I/O) I/O latch-up current V < 0 V; V > VDDD 200 − − mA Rpu internal pull-up resistor 16 33 78 kΩ − 1792 × fHSYNC − kHz AC characteristics fclk(sys) system clock frequency note 3 tr rise time − 6 25 ns tf fall time − 6 25 ns Notes 1. The absolute maximum input voltage is 6.0 V. 2. X is the source/sink current under worst case conditions. X is reflected in the name of the I/O cell according to the drive capability. The minimum value of X is 1 mA. 3. The internal system clock frequency is 1792 × fHSYNC of the main channel and subchannel. 1999 Nov 12 17 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 TEST AND APPLICATION INFORMATION Figure 5 gives the application diagram in a standard configuration. Input signals main channel CVBS and subchannel CVBS from different video sources are processed by the SAB9083 and inserted by the YUV to RGB switch. HS/VS handbook, full pagewidth FBL subchannel CVBS SUB DECODER YUV YUV TDA8310 SAB9083 PIP CONTROLLER YUV to RGB SWITCH TDA4780 HS/VS HS/VS RGB YUV/RGB PROCESSING AND DEFLECTION CIRCUIT HS/VS RGB main channel CVBS MAIN DECODER YUV YUV TDA8310 MGL586 Fig.5 Application diagram. 1999 Nov 12 18 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT317-2 c y X 80 A 51 81 50 ZE e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp L 31 100 detail X 30 1 wM bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 20.1 19.9 14.1 13.9 0.65 24.2 23.6 18.2 17.6 1.95 1.0 0.6 0.2 0.15 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT317-2 1999 Nov 12 EUROPEAN PROJECTION 19 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Nov 12 SAB9083 20 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable(2) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 Nov 12 21 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Nov 12 22 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller NOTES 1999 Nov 12 23 SAB9083 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 68 © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/25/02/pp24 Date of release: 1999 Nov 12 Document order number: 9397 750 06156