INTEGRATED CIRCUITS 74ABT843 9-bit interface latch with set and reset (3-State) Product specification Supersedes data of 1995 Sep 06 IC23 Data Handbook 1998 Jan 16 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) FEATURES 74ABT843 DESCRIPTION • High speed parallel latches • Extra data width for wide address/data paths or buses carrying The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. parity The 74ABT843 consists of nine D-type latches with 3-State outputs. In addition to the LE and OE pins, it has a Master Reset (MR) pin and Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When MR is Low, the outputs are Low if OE is Low. When MR is High, data can be entered into the latch. When PRE is Low, the outputs are High, if OE is Low. PRE overrides MR. • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors • Slim DIP 300 mil package • Broadside pinout • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model • Power-up 3-State • Power-up reset QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 5.0 ns tPLH tPHL Propagation delay Dn to Qn CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 500 nA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP –40°C to +85°C 74ABT843 N 74ABT843 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT843 D 74ABT843 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT843 DB 74ABT843 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT843 PW 74ABT843PW DH SOT355-1 PIN CONFIGURATION PIN DESCRIPTION OE 1 24 VCC D0 2 23 Q0 PIN NUMBER SYMBOL FUNCTION 1 OE 2, 3, 4, 5, 6, 7, 8, 9, 10 D0-D8 Data inputs Data outputs Output enable input (active-Low) D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 23, 22, 21, 20, 19,18, 17, 16, 15 Q0-Q8 11 MR Master reset input (active-Low) 13 LE Latch enable input (active rising edge) TOP VIEW D5 7 18 Q5 D6 8 17 Q6 D7 9 16 Q7 D8 10 15 Q8 14 PRE Preset input (active-Low) MR 11 14 PRE 12 GND Ground (0V) 13 LE 24 VCC Positive supply voltage GND 12 SA00250 1998 Jan 16 2 853-1620 18864 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) LOGIC SYMBOL 74ABT843 LOGIC SYMBOL (IEEE/IEC) 1 11 2 3 4 5 6 7 8 9 14 10 EN R S2 13 C1 D0 D1 D2 D3 D4 D5 D6 D7 D8 13 LE 2 14 PRE 3 22 11 MR 4 21 1 OE 5 20 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 6 19 7 18 8 17 9 16 10 15 23 22 21 20 19 18 17 16 15 SA00251 1D 23 SA00252 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE OE PRE MR LE Dn Qn L L X X X H Preset L H L X X L Clear L L H H H H H H L H L H Transparent L L H H H H ↓ ↓ l h L H Latched High impedance H X X X X Z L H H L X NC H = h = L = l = NC= X = Z = ↓ = Hold High voltage level High voltage level one set-up time prior to the High-to-Low LE transition Low voltage level Low voltage level one set-up time prior to the High-to-Low LE transition No change Don’t care High impedance “off” state High-to-Low transition 1998 Jan 16 3 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) 74ABT843 LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 D8 10 14 PRE P P D L P D C Q L P C Q L P D D C Q L P D C Q L P D C Q L P D C Q L P D C Q L D C Q L C Q 11 MR 13 LE 1 OE 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 SA00253 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jan 16 4 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) 74ABT843 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C 2.0 ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range V DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK VOH Input clamp voltage High–level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.9 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low–level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power–up output low voltage3 VCC = 5.5V; IO = 1mA; VI = VCC or GND 0.13 0.55 0.55 V II Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3–state output current4 VCC = 2.0V; VO = 0.5V; V OE = VCC; VI = GND or VCC ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA –80 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 0.5 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 25 34 34 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.5 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA IOFF IPU/IPD IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip–flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100µsec is permitted. 1998 Jan 16 5 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) 74ABT843 AC CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM UNIT Min Typ Max Min Max 1 1.6 2.2 3.6 5.0 5.2 6.3 1.6 2.2 6.0 7.2 ns Propagation delay LE to Qn 2 2.0 2.8 4.1 4.8 5.6 6.3 2.0 2.8 6.5 6.9 ns tPLH tPHL Propagation delay PRE to Qn 1 2.2 3.0 4.7 5.2 6.2 6.5 2.2 3.0 7.4 7.2 ns tPLH tPHL Propagation delay MR to Qn 1 2.5 3.1 5.0 5.5 6.3 6.8 2.5 3.1 7.1 8.0 ns tPZH tPZL Output enable time OE to Qn 4 5 1.0 2.0 2.7 4.2 4.2 5.5 1.0 2.0 5.2 6.5 ns tPHZ tPLZ Output disable time OE to Qn 4 5 2.9 2.2 4.9 5.0 6.2 6.3 2.9 2.2 6.8 6.7 ns tPLH tPHL Propagation delay Dn to Qn tPLH tPHL AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER +25oC Tamb = VCC = +5.0V WAVEFORM Tamb = -40 to +85oC VCC = +5.0V ±0.5V Min Typ Min UNIT ts(H) ts(L) Setup time, High or Low Dn to LE 3 2.5 3.0 1.1 1.3 2.5 3.0 ns th(H) th(L) Hold time, High or Low Dn to LE 3 1.0 1.0 –1.0 –1.0 1.0 1.0 ns tw(H) LE pulse width, High 3 3.3 1.8 3.3 ns tw(L) PRE pulse width, Low 6 4.5 3.0 4.5 ns tw(L) MR pulse width, Low 6 5.5 4.0 5.5 ns trec PRE recovery time 6 2.9 1.6 2.9 ns trec MR recovery time 6 3.6 2.0 3.6 ns 1998 Jan 16 6 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) 74ABT843 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V Dn PRE VM VM MR, Dn LE tPLH Qn VM VM tPHL VM tPLH VM tPHL Qn VM VM SA00254 SA00255 Waveform 1. Propagation Delay, Data to Output, Master Reset to Output, Preset to Output Waveform 2. Propagation Delay, Latch Enable to Output ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ VM Dn VM ts(H) VM th(H) VM ts(L) OE VM th(L) tPZH tw(H) VM LE VM VM Qn VM tPHZ VOH –0.3V VM 0V NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00166 SA00256 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 3. Data Setup and Hold Times and Latch Enable Pulse Width PRE, MR OE VM VM tPZL VM tw(L) tPLZ LE Qn VM VM tREC VM VOL +0.3V VOL Qn SA00109 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level Qn SA00257 Waveform 6. Master Reset and Preset Pulse Width, Master Reset and Preset to Latch Enable Recovery Time TEST CIRCUIT AND WAVEFORM 1998 Jan 16 7 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) 7V 500 Ω From Output Under Test S1 Open GND 500 Ω CL = 50 pF Load Circuit TEST S1 tpd open tPLZ/tPZL 7V tPHZ/tPZH open DEFINITIONS Load capacitance includes jig and probe capacitance; CL = see AC CHARACTERISTICS for value. SA00012 1998 Jan 16 8 74ABT843 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) DIP24: plastic dual in-line package; 24 leads (300 mil) 1998 Jan 16 9 74ABT843 SOT222-1 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) SO24: plastic small outline package; 24 leads; body width 7.5 mm 1998 Jan 16 10 74ABT843 SOT137-1 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm 1998 Jan 16 11 74ABT843 SOT340-1 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm 1998 Jan 16 12 74ABT843 SOT355-1 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) NOTES 1998 Jan 16 13 74ABT843 Philips Semiconductors Product specification 9-bit bus interface latch with set and reset (3-State) 74ABT843 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 14 Date of release: 05-96 9397-750-03475