INTEGRATED CIRCUITS DATA SHEET SAB9076H Picture-In-Picture (PIP) controller Preliminary specification File under Integrated Circuits, IC02 1996 Aug 13 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H FEATURES Display • Twin PIP in interlaced mode at 8-bit resolution • Sub-title mode features built in • Large display fine positioning area, both channels independent GENERAL DESCRIPTION • Only 2 Mbit required as external VDRAM (2 × 1 Mbit or 1 × 2 Mbit) The SAB9076H is a picture-in-picture controller for NTSC TV-sets. The circuit contains ADCs, reduction circuitry, memory control, display control and DACs. • Four 8-bit Analogue Digital Converters (ADCs; > 7-bit performance) with clamp circuit The device inserts one or two live video signals with original or reduced sizes into a live video signal. All video signals are expected to be analog baseband signals. The conversion into the digital environment and back to the analog environment is carried out on chip. Internal clocks are generated by two acquisition PLLs and a display PLL. • Most PIP modes handle interlaced pictures without joint line error • Two PLLs which generate the line-locked clocks for the acquisition channels • Display PLL to generate line-locked clock for the display • Three 8-bit Digital Analogue Converters (DACs) • 4 : 1 : 1 data format Due to the two PIP channels and a large external memory a wide range of PIP modes are offered. The emphasis is put on single-PIP, double-PIP, split-screen mode and a many multi-PIP modes. • Data reduction factors 1 to 1, 1 to 2, 1 to 3 and 1 to 4, horizontal and vertical independent. I2C-bus programmable • Single and double PIP modes can be set • Full field still mode available • Several aspect ratios can be handled • Reduction factors can be set freely • Selection of vertical filtering type • Freeze of live pictures • Fine tuned display position, H (8-bit), V (8-bit), both channels independent • Fine tuned acquisition area, H (4-bit), V (8-bit), both channels independent • Eight main borders, sub-borders and background colours selectable • Border and background brightness adjustable, 30%, 50%, 70% and 100% IRE • Several type of decoder input signals can be set. 1996 Aug 13 2 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage 4.5 5.0 5.5 V IDD supply current − 200 − mA fsys system frequency − 27 − MHz floop PLL loop bandwidth frequency 4 − − kHz tjitter PLL short term stability time − − 4 ns ς PLL damping factor − 0.7 − − note 1 jitter during 1 line (64 µs) Note 1. The internal system frequency is 1728 times the HSync input frequency for both the Acquisition and Display PLLs. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAB9076H QFP100(1) DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm VERSION SOT317-2 Note 1. When using IR reflow soldering it is recommended that the Drypack instructions in the “Quality Reference Handbook” (order number 9398 510 63011) are followed. 1996 Aug 13 3 1996 Aug 13 4 MVsync MPVbias MPHsync MAVrefT MAVrefB MAVbias MV MU MY SVsync SPVbias SPHsync SAVrefB SAVrefT SAVbias SV SU SY 66 67 45 13 44 14 43 49 47 31 40 32, 34, 36, 38, 39, 37, 35, 33 LINE MEMORY HORIZONTAL AND VERTICAL FILTER LINE MEMORY 42 41 I2C-BUS CONTROL SAB9076H 59 16 15 23, 25, 27, 29, 30, 28, 26, 24 VDRAM CONTROL AND (RE-) FORMATTING 48 20 21 92 PLL AND CLOCK GENERATOR 18 84 LINE MEMORY DISPLAY CONTROL DAC AND BUFFER 51, 53, 55, 91 57, 58, 56, 54, 52, 50 83 93 89 87 85 88 99 98 97 65 46 62 SDA 61 SCL 60 A0 TM0 MCVDDD MCVSSD TM1 TM2 22 TC 19 TACLK TDCLK 63 95 MGC962 DPHsync DPVbias DVsync DFB DAVrefB DAVrefT DAVbias DV DU DY Picture-In-Picture (PIP) controller Fig.1 Block diagram. POR DCVDDD DVSSD VDDD SCVDDD SPVSSA DPVDDA MPVSSA DCVSSD DVDDD VSSD SCVSSD SPVDDA DPVSSA MPVDDA 1 94 82 68 HORIZONTAL AND VERTICAL FILTER 70 DAVDDA DAVSSA DAVDDD DAVSSD 96 PLL AND CLOCK GENERATOR CLAMP AND ADC PLL AND CLOCK GENERATOR 81 69 AD0 to AD8 17 100 77 DAI0 to DAI7 DAO0 to DAO7 2 9 7 5 8 6 10 80 64 79 72 74 76 73 CLAMP AND ADC 78 SC 90 11 DT 86 12 WE 71 4 CAS 75 3 RAS SAVSSD SVSSD MAVSSA SAVSSA MVSSD SAVDDD SVDDD MAVDDA SAVDDA MVDDD handbook, full pagewidth MAVDDD MAVSSD Philips Semiconductors Preliminary specification SAB9076H BLOCK DIAGRAM Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H PINNING SYMBOL PIN I/O TYPE DESCRIPTION MPVbias 1 MPHsync 2 I/O E027 analog bias reference for main channel I HPP01 MAVSSD 3 I/O E009 digital ground for main channel ADCs and PLLs MAVDDD 4 I/O E030 digital positive power supply for main channel ADCs and PLLs MAVbias 5 I E027 analog bias reference input for main channel ADCs MU 6 I E027 analog U input for main channel MAVrefT 7 I E027 analog top reference voltage input for main channel ADCs MV 8 I E027 analog V input for main channel MAVrefB 9 I E027 analog bottom reference voltage input for main channel ADCs MY 10 I E027 analog Y input for main channel horizontal synchronization input for main channel MAVDDA 11 I/O E030 analog positive power supply for main channel ADCs MAVSSA 12 I/O E009 analog ground for main channel ADCs MVSSD 13 I/O E009 digital ground for main-channel core MVDDD 14 I/O E030 digital positive power supply for main-channel core MCVDDD 15 I/O E030 digital positive power supply for main-clock buffer MCVSSD 16 I/O E009 digital ground for main-clock buffer MVsync 17 I HPP01 vertical synchronization input for main channel TDCLK 18 I HPP01 test clock input for display TC 19 I HPP01 test control input TM0 20 I HPP01 test mode 0 input TM1 21 I HPP01 test mode 1 input n.c. 22 − − DAI0 23 I HPP01 data bus input from memory; bit 0 DAI7 24 I HPP01 data bus input from memory; bit 7 DAI1 25 I HPP01 data bus input from memory; bit 1 DAI6 26 I HPP01 data bus input from memory; bit 6 DAI2 27 I HPP01 data bus input from memory; bit 2 DAI5 28 I HPP01 data bus input from memory; bit 5 DAI3 29 I HPP01 data bus input from memory; bit 3 not connected DAI4 30 I HPP01 data bus input from memory; bit 4 DT 31 O OPF20 memory data transfer output; active LOW DAO0 32 O OPF20 data bus output to memory; bit 0 DAO7 33 O OPF20 data bus output to memory; bit 7 DAO1 34 O OPF20 data bus output to memory; bit 1 DAO6 35 O OPF20 data bus output to memory; bit 6 DAO2 36 O OPF20 data bus output to memory; bit 2 DAO5 37 O OPF20 data bus output to memory; bit 5 DAO3 38 O OPF20 data bus output to memory; bit 3 DAO4 39 O OPF20 data bus output to memory; bit 4 SC 40 O OPF20 memory shift clock output 1996 Aug 13 5 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SYMBOL SAB9076H PIN I/O TYPE DESCRIPTION DCVSSD 41 I/O E009 digital ground for display-clock buffer DCVDDD 42 I/O E030 digital positive power supply for display-clock buffer DVDDD 43 I/O E030 digital positive power supply for display core DVSSD 44 I/O E009 digital ground for display core VSSD 45 I/O E009 digital ground for peripherals VDDD 46 I/O E030 digital positive power supply for peripherals WE 47 O OPF20 memory write enable output; active LOW CAS 48 O OPF20 memory column address strobe output; active LOW RAS 49 O OPF20 memory row address strobe output; active LOW AD8 50 O OPF20 memory address bus output; bit 8 AD0 51 O OPF20 memory address bus output; bit 0 AD7 52 O OPF20 memory address bus output; bit 7 AD1 53 O OPF20 memory address bus output; bit 1 AD6 54 O OPF20 memory address bus output; bit 6 AD2 55 O OPF20 memory address bus output; bit 2 AD5 56 O OPF20 memory address bus output; bit 5 AD3 57 O OPF20 memory address bus output; bit 3 AD4 58 O OPF20 memory address bus output; bit 4 A0 59 I HPF01 I2C-bus address 0 selection input SCL 60 I HPF01 shift clock input for I2C-bus SDA 61 I/O IOI41 POR 62 I HUP07 power-on reset input TACLK 63 I HPP01 test clock input for acquisition SVsync 64 I HPP01 vertical synchronization input for sub-channel SCVSSD 65 I/O E009 digital ground for sub-clock buffer SCVDDD 66 I/O E030 digital positive power supply for sub-clock buffer SVDDD 67 I/O E030 digital positive power supply for sub-channel core SVSSD 68 I/O E009 digital ground for sub-channel core SAVSSA 69 I/O E009 analog ground for sub-channel ADCs SAVDDA 70 I/O E030 analog positive power supply for sub-channel ADCs SY 71 I E027 analog Y input for sub-channel SAVrefB 72 I E027 analog bottom reference input voltage for sub-channel ADCs SV 73 I E027 analog V input for sub-channel SAVrefT 74 I E027 analog top reference input voltage for sub-channel ADCs SU 75 I E027 analog U input for sub-channel SAVbias 76 I/O E027 analog bias reference input/output for sub-channel ADCs SAVDDD 77 I/O E030 digital positive power supply for sub-channel ADCs and PLLs SAVSSD 78 I/O E009 digital ground for sub-channel ADCs and PLLs SPHsync 79 I HPP01 SPVbias 80 I/O E027 analog bias reference input/output for sub-channel SPVSSA 81 I/O E009 analog ground for sub-channel PLL 1996 Aug 13 shift I2C-bus input data; acknowledge I2C-bus output data horizontal synchronization input for sub-channel 6 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SYMBOL SAB9076H PIN I/O TYPE DESCRIPTION SPVDDA 82 I/O E030 analog positive power supply for sub-channel PLL DAVDDA 83 I/O E030 analog positive power supply for DACs DAVSSA 84 I/O E009 analog ground for DACs DAVbias 85 I E027 analog bias voltage reference input for DACs DY 86 O E027 analog Y output of DAC DAVrefT 87 I E027 analog top reference input voltage for DACs DV 88 O E027 analog V output of DAC DAVrefB 89 I E027 analog bottom reference input voltage for DACs DU 90 O E027 analog U output of DAC DAVSSD 91 I/O E009 digital ground for DACs DAVDDD 92 I/O E030 digital positive power supply for DACs DFB 93 O OPF20 fast blanking control output signal DVsync 94 I HPP01 vertical synchronization input for display channel DPHsync 95 I HPP01 horizontal synchronization input for display PLL DPVbias 96 I/O E027 analog bias voltage reference input/output for display PLL DPVSSA 97 I/O E009 analog ground for display PLL DPVDDA 98 I/O E030 analog positive power supply for display PLL MPVDDA 99 I/O E030 analog positive power supply for main channel PLL MPVSSA 100 I/O E009 analog ground for main channel PLL Table 1 Pin type explanation PIN TYPE DESCRIPTION E030 VDD pin; diode to VSS E009 VSS pin; diode to VDD E027 analog input pin; diode to VDD and VSS HPF01 digital input pin; CMOS levels, diode to VSS HPP01 digital input pin; CMOS levels, diode to VDD and VSS HUP07 digital input pin; CMOS levels with hysteresis, pull-up resistor to VDD, diode to VDD and VSS IOI41 I2C-bus pull-down output stage; CMOS input levels, diode to VSS OPF20 digital output pin; CMOS levels 1996 Aug 13 7 Philips Semiconductors Preliminary specification 81 SPVSSA 83 DAVDDA 82 SPVDDA 85 DAVbias 84 DAVSSA 86 DY 87 DAVrefT 90 DU 89 DAVrefB 88 DV SAB9076H 92 DAVDDD 91 DAVSSD 93 DFB 94 DVsync 96 DPVbias 95 DPHsync handbook, full pagewidth 98 DPVDDA 97 DPVSSA 100 MPVSSA 99 MPVDDA Picture-In-Picture (PIP) controller MPVbias MPHsync MAVSSD 1 80 SPVbias 2 79 SPHsync 78 SAVSSD MAVDDD 4 MAVbias 5 77 SAVDDD 76 SAVbias 3 MU 6 75 SU MAVrefT 7 74 SAVrefT MV 8 73 SV MAVrefB 9 72 SAVrefB 71 SY MY 10 70 SAVDDA 69 SAVSSA MAVDDA 11 MAVSSA 12 MVSSD 13 MVDDD 14 68 SVSSD 67 SVDDD MCVDDD 15 66 SCVDDD SAB9076H MCVSSD 16 MVsync 17 65 SCVSSD 64 SVsync TDCLK 18 63 TACLK TC 19 62 POR TM0 20 61 SDA TM1 21 60 SCL 59 A0 n.c. 22 Fig.2 Pin configuration. 1996 Aug 13 8 AD8 50 RAS 49 CAS 48 WE 47 VDDD 46 VSSD 45 DVSSD 44 DVDDD 43 DCVSSD 41 DCVDDD 42 SC 40 DAO4 39 51 AD0 DAO3 38 52 AD7 DAI4 30 DAO5 37 53 AD1 DAI3 29 DAO2 36 54 AD6 DAI5 28 DAO6 35 55 AD2 DAI2 27 DAO1 34 56 AD5 DAI6 26 DAO7 33 57 AD3 DAI1 25 DAO0 32 58 AD4 DAI7 24 DT 31 DAI0 23 MGC963 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H FUNCTIONAL DESCRIPTION Display mode Pixel rate The internal display pixel rate is 864 × DPHsync which is 13.5 MHz. This pixel rate is up sampled by interpolation to 1728 × DPHsync before the DAC stage. The internal chrominance format used is 4 : 1 : 1. It is expected that the bandwidth of the input signals is limited to 4.5 MHz for the Y input and 1.125 MHz for the U/V input. Display area The Y input is sampled with a 1728 × HS (≈27.0 MHz) clock and is filtered and down sampled to the internal 864 × HS (≈13.5 MHz) pixel rate. The display background is an area of 696 pixels and 238 lines. This can be put on/off by the BGON bit independent of the PIPON bit. This area can be moved by the display background fine positioning (BGHFP and BGVFP registers). Its colour is determined by the BGCOL and BGBRT registers. The U and V inputs are multiplexed and sampled with a 432 × HS clock and down sampled to the internal 216 × HS (≈3.375 MHz) pixel rate. Within this area PIPs are defined dependent on the PIP mode. The PIP sizes are determined by the display reduction factors as is shown in Table 2. Acquisition area Synchronisation is achieved via the acquisition HSync and Vsync pins. With the acquisition fine positioning added to a system constant the starting point of the acquisition can be controlled. The display fine positioning determines the location of the PIPs with respect to the background. Sub-channel and main channel both have their independent PIP size and location control, which is shown in Fig.3. The acquisition area is 672 pixels/line and 228 lines/field for NTSC. Both main and sub-channels are equivalent in handling the data. Table 2 PIP sizes REDUCTION H/1 H/2 H/3 H/4 V/1 V/2 V/3 V/4 Pixels 672 336 224 168 − − − − Lines − − − − 228 114 76 57 1996 Aug 13 9 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H handbook, full pagewidth BGHFP BGVFP SAVFP SAHFP MAVFP MAHFP SUB CHANNEL MAIN CHANNEL 238 lines 696 pixels MGC964 Fig.3 Display fine positioning. Approximately 800 8-bit words can be fetched from the external VDRAM in one display line which is not enough to display one complete display line with true 8-bit resolution. PIP modes The two independent acquisition channels can be controlled independently on the display side. A wide variety of modes is possible but a subset of 7 modes is fixed and can be set easily by the I2C-bus. An overview of the preconditioned modes is given in Table 3. For all PIP modes the main and sub-display fine positioning must be set to obtain a display configuration. Two methods of reducing data are available. One is simply skipping the 8-bit to 6-bit (SKIP6, I2C-bus bit) and the other is a small form of data reduction to come from 8-bit to 6-bit (SMART6, I2C-bus bit). If both bits are set to logic 0 the device is in true 8-bit resolution mode. For the twin PIP mode the main channel is not placed in the VDRAM but in an internal buffer, so still 8-bit resolution is achieved. DATA TRANSFER The internal data path has an 8-bit resolution and 4 : 1 : 1 data format. The communication to the external VDRAM takes place at 864 × Hsync (both display and acquisition). 1996 Aug 13 10 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller Table 3 PIP modes PIP MODES NAME SP FIGURE SP small SUB-CHANNEL MAIN CHANNEL MODE REDH REDV REDH REDV HFP VFP HFP VFP 0000 1⁄ 4 1⁄ 4 − − − − − − 3 1⁄ 3 − − − − − − 2 1⁄ 2 − − − − − − − 1⁄ 4 1⁄ 4 − − − − 3 1⁄ 3 − − − − 2 1⁄ 2 − − − − 2 1⁄ 2 03H 46H 57H 46H 2 1⁄ 1 SP SP medium 0000 1⁄ SP SP large 0000 1⁄ SP SAB9076H SP small 0000 − SUB-CHANNEL MAIN CHANNEL SP SP medium 0000 − − 1⁄ SP SP large 0000 − − 1⁄ 0000 1⁄ 2 1⁄ 2 1⁄ 2 1⁄ 1 1⁄ 03H 05H 57H 05H 4 1⁄ 4 − − 08H 46H − − 4 1⁄ 4 − − 72H 10H 4 1⁄ 4 DP DP DP twin PIP 1001 1⁄ MP3L POP-left 0010 1⁄ MR3R POP-right 0010 − − 1⁄ 4 1⁄ 4 1⁄ 08H 10H 72H 10H 4 1⁄ 4 − − 03H 05H − − 4 1⁄ 4 1⁄ 2 1⁄ 2 03H 05H 44H 20H 2 1⁄ 2 1⁄ 2 1⁄ 2 03H 05H 03H 77H 3 1⁄ 3 1⁄ 3 1⁄ 3 03H 05H 51H 3BH 4 1⁄ 4 − − 03H 05H 03H 05H 4 1⁄ 4 1⁄ 1⁄ 03H 05H 03H 77H 1 1⁄ 1 MR3D POP-double 0010 1⁄ MP7 POP-double 0011 1⁄ 0011 1⁄ 0001 1⁄ MP8 MP4 MP7 Quatro MP9 MP9 0100 1⁄ MP16 MP16 0101 1⁄ 0110 1⁄ MP16 MP16 mix 4 4 FFS full field still 0000 1⁄ − − 03H 05H − − FFL full field live 1000 − − 1⁄ 1⁄ 1 − − 03H 05H MAN manual 0111 X X X X X X X X 1 PIP COMBINATIONS Figures 4, 5 and 6 provide an overview of possible combinations as they can be shown on the screen. An example of fine positioning is given in the right four columns of Table 3. More PIP modes can be obtained by varying the horizontal and vertical reduction factors to meet correct aspect ratios when using 16 : 9 screens. 1996 Aug 13 11 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H handbook, halfpage handbook, halfpage SP-Small MGD594 handbook, halfpage MGD595 DP MGD597 POP-Left MGD588 handbook, halfpage SP-Large MGD596 handbook, halfpage handbook, halfpage Twin-PIP MGD598 Fig.4 PIP Modes. 1996 Aug 13 SP-Medium 12 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller handbook, halfpage SAB9076H handbook, halfpage POP-Right MGD589 MGD590 MP8 MGD592 Quatro MGD584 handbook, halfpage handbook, halfpage MP7 MGD591 handbook, halfpage handbook, halfpage MP13 MGD593 Fig.5 PIP Modes (continued). 1996 Aug 13 POP-Double 13 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H handbook, halfpage handbook, halfpage MP9 MGD585 Full Field Still Full Field Live MGD587 MP16 handbook, halfpage Fig.6 PIP Modes (continued). 1996 Aug 13 14 MGD586 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H I2C-bus description I2C-bus control is in accordance with the I2C-bus protocol. The I2C-bus provides bi-directional 2-line communication between different ICs. The SDA line is the serial data line and SCL serves as serial clock line. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. First a START sequence must be put on the I2C-bus, then the I2C-bus address of the circuit must be send, followed by a subaddress. After this sequence the data of the subaddresses must be sent. An auto-increment function gives the option to send data of the incremented subaddresses until a STOP sequence is send. Table 4 gives an overview of the I2C-bus addresses. The SAB9076H has the I2C-bus addresses 2C and 2E, switchable by the pin A0. Valid Sub-Addresses (SA) are 00H to 18H (Table 4) and 20H to 32H (Table 6). Table 4 Overview of I2C-bus sub-addresses DATA BYTE SA BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 00H MPIPON SPIPON MFREEZE SFREEZE PIPMODE3 PIPMODE2 PIPMODE1 PIPMODE0 01H note 1 note 1 M1FLD S1FLD note 1 02H DFILT FILLOFF SMART6 SKIP6 YTH3 YTH2 YTH1 YTH0 03H BGHFP3 BGHFP2 BGHFP1 BGHFP0 BGVFP3 BGVFP2 BGVFP1 BGVFP0 04H SDHFP7 SDHFP6 SDHFP5 SDHFP4 SDHFP3 SDHFP2 SDHFP1 SDHFP0 05H SDVFP7 SDVFP6 SDVFP5 SDVFP4 SDVFP3 SDVFP2 SDVFP1 SDVFP0 06H MDHFP7 MDHFP6 MDHFP5 MDHFP4 MDHFP3 MDHFP2 MDHFP1 MDHFP0 07H MDVFP7 MDVFP6 MDVFP5 MDVFP4 MDVFP3 MDVFP2 MDVFP1 MDVFP0 08H MDREDH1 MDREDH0 MDREDV1 MDREDV0 SDREDH1 SDREDH0 SDREDV1 SDREDV0 DNONINT BIT 1 MNONINT BIT 0 SNONINT 09H MAREDH1 MAREDH0 MAREDV1 MAREDV0 SAREDH1 SAREDH0 SAREDV1 SAREDV0 0AH MAHFP3 MAHFP2 MAHFP1 MAHFP0 SAHFP3 SAHFP2 SAHFP1 SAHFP0 0BH SAVFP7 SAVFP6 SAVFP5 SAVFP4 SAVFP3 SAVFP2 SAVFP1 SAVFP0 0CH MAVFP7 MAVFP6 MAVFP5 MAVFP4 MAVFP3 MAVFP2 MAVFP1 MAVFP0 0DH MLSEL3 MLSEL2 MLSEL1 MLSEL0 SLSEL3 SLSEL2 SLSEL1 SLSEL0 0EH MBSEL3 MBSEL2 MBSEL1 MBSEL0 SBSEL3 SBSEL2 SBSEL1 SBSEL0 0FH BHSIZE3 BHSIZE2 BHSIZE1 BHSIZE0 BVSIZE3 BVSIZE2 BVSIZE1 BVSIZE0 10H note 1 SBON SBBRT1 SBBRT0 note 1 SBCOL2 SBCOL1 SBCOL0 11H note 1 SBSON SBSBRT1 SBSBRT0 note 1 SBSCOL2 SBSCOL1 SBSCOL0 12H note 1 MBON MBBRT1 MBBRT0 note 1 MBCOL2 MBCOL1 MBCOL0 13H note 1 MBSON MBSBRT1 MBSBRT0 note 1 MBSCOL2 MBSCOL1 MBSCOL0 14H note 1 BGON BGBRT1 BGBRT0 note 1 SBGCOL2 SBGCOL1 SBGCOL0 15H note 1 note 1 note 1 SVFILT SUVPOL SVSPOL SHSYNC SFPOL 16H note 1 note 1 note 1 MVFILT MUVPOL MVSPOL MHSYNC MFPOL 17H note 1 FBDEL2 FBDEL1 FBDEL0 DUVPOL DVSPOL DHSYNC DFPOL 18H PEDESTV3 PEDESTV2 PEDESTV1 PEDESTV0 PEDESTU3 PEDESTU2 PEDESTU1 PEDESTU0 Note 1. The data bits which are not used should be set to zero. 1996 Aug 13 15 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H The YTH3 to YTH0 bits control the video output. If the current Y-value is less then YTH × 16 then the fast blank is switched off, the original live background will be visible. This feature can be used to pick up sub-titles and display them as On-Screen Display (OSD) anywhere on the screen. SA 00H PIP REGISTER The MPIPON and SPIPON bits switch respectively the main and sub PIPs of the SAB9076H on or off. The MFREEZE and SFREEZE bits make the current live pictures for the channels main and sub frozen. The writing to the VDRAM is stopped. The PIPMODE3 to PIPMODE0 bits set the PIP mode in accordance with Table 3. SA 03H DISPLAY BACKGROUND FINE POSITIONING REGISTER The BGHFP3 to BGHFP0 bits control the horizontal display positioning of the background. The resolution is 16 steps of 4 pixels. The BGVFP3 to BGVFP0 bits control the vertical display positioning of the background. The resolution is 16 steps of 2 lines/field. The background fine positioning moves the complete display. It is a general offset of all the PIP pictures and background. It is intended only to adjust once the centring of all PIP modes (see Fig.3). SA 01H DISPLAY REGISTER The M1FLD and S1FLD(1) bits control the use of the reserved second field in the VDRAM. If this bit is set to logic 0 then address spaces are reserved for both fields in the VDRAM. This avoids joint line errors. Whether these address spaces are used is dependent on the interlacing of the input signals and the three NONINT bits. If a 1FLD bit is set to logic 1 then only 1 address space is used in the VDRAM for both fields. In some PIP modes the use of a second field is not possible since there is not enough space in the VDRAM, in these modes the 1FLD bit must be set to logic 1. DNONINT controls the interlace mode of the display part. If set to logic 1 then data is only read from one field in the VDRAM. If set to logic 0 then both fields (if available) are used for display. SA 04H AND SA 05H DISPLAY SUB-CHANNEL FINE POSITIONING REGISTERS These registers control the horizontal and vertical fine positioning of the display sub-channel with respect to the display background. This is the actual fine positioning (see Fig.3). The horizontal resolution is 256 steps of 4 pixels and the vertical resolution is 256 steps of 1 line/field. The MNONINT and SNONINT bits control the interlace mode of the acquisition blocks. If set to logic 1 then data is only written to one field in the VDRAM (two fields remain allocated). If set to logic 0 then both fields (if available) are used for acquisition. SA 06H AND SA 07H DISPLAY MAIN-CHANNEL FINE POSITIONING REGISTERS These registers control the horizontal and vertical fine positioning off the display main-channel with respect to the display background. This is the actual fine positioning (see Fig.3). The horizontal resolution is 256 steps of 4 pixels and the vertical resolution is 256 steps of 1 line/field. SA 02H DISPLAY REGISTER The DFILT bit controls an interpolating filter that changes the internal 864 pixels data rate to the output data rate of 2 × 864 pixels. If DFILT is set to logic 1 then the filter is on. The FILLOFF bit controls filling of PIPs when the PIP mode is switched. If FILLOFF is set to logic 0 then all PIPs are filled with a 30% gray until their channel has been updated. If FILLOFF is set to logic 1 then the VDRAM content is always visible. This is useful when a new, ‘similar’ to the previous one, PIP mode is set. The previous data can then be displayed. SA 08H DISPLAY REDUCTION FACTORS REGISTER This register sets the display reduction factors, independent of the acquisition reduction factors. It sets the PIP size to a certain default value in such a way that the border drawn around the PIP is just fitting. SA 09H ACQUISITION REDUCTION FACTORS REGISTER The SMART6 and SKIP6 bits control the data transfer mode to the external VDRAM. For modes which display a complete line (672 pixels) a type of data reduction has to be carried out. Two transfer modes are available. One is simply skipping the 8-bit data path to 6-bit (SKIP6). The other is carry out an intelligent data reduction which retains an 8-bit resolution (SMART6). This register sets the acquisition reduction factors, independent of the display reduction factors. If the HRED is 1 : 1 then the VRED must also be 1 : 1. Restrictions are: • The DREDH and AREDH must be the same • The DREDV is equal or smaller than the AREDV (e.g DREDV is 1 : 2 and AREDV is 1 : 1). (1) The 1 FLD bits only operate when the NONINT bits of the corresponding channel is set. 1996 Aug 13 16 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H If SBSON is set to logic 1 then one sub-PIP border can have a different colour. This border is selected by the SBSEL3 to SBSEL0 bits. SA 0AH TO SA 0CH ACQUISITION FINE POSITIONING REGISTERS These registers determine the start of the acquisition area. Horizontal fine positioning can be adjusted with 16 steps of 2 pixels, vertical fine positioning can be adjusted with 256 steps of 1 line/field. The SBSBRT and SBSCOL bits control the brightness and colour off the sub-border selection colour. SA 12H AND SA 13H BORDER COLOUR AND BORDER SA 0DH TO SA 0EH SELECTION REGISTERS SELECTION COLOUR OF MAIN CHANNEL REGISTERS (see Table 5) The MLSEL3 to MLSEL0 and SLSEL3 to SLSEL0 bits control which PIP is live. Both main channel and sub-channel can have one live PIP. Counting is carried out from upper-left to lower-right. If MBON is set to logic 1 then the border of the main channel is visible. The MBBRT and MBCOL bits control the brightness and colour of the main-channel border colour. The MBSEL3 to MBSEL0 and SBSEL3 to SBSEL0 bits control which PIP border has a different colour. Both main channel and sub-channel can have a different PIP channel border selection. Counting is done from upper-left to lower-right. If MBSON is set to logic 1 then one main PIP border can have a different colour. This border is selected by the MBSEL3 to MBSEL0 bits. The MBSBRT and MBSCOL bits control the brightness and colour off the main-border selection colour. SA 0FH BORDER SIZE REGISTER This register controls the border size. The minimum horizontal border is 2 pixels. The minimum vertical border is 1 line. The vertical border size is multiplied by the FH mode number before it is displayed on the screen. SA 14H BACKGROUND CONTROL REGISTER (see Table 5) If BGON is set to logic 1 then the background is visible. BGBRT and BGCOL registers control the brightness and colour of the background colour. SA 10H AND SA 11H BORDER COLOUR AND BORDER SELECT (see Table 5) COLOUR OF SUB-CHANNEL REGISTERS If SBON is set to logic 1 then the border of the sub-channel is visible. SBBRT and SBCOL control the brightness and colour of the sub-channel border colour. 1996 Aug 13 17 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller Table 5 SAB9076H Colour types and brightness levels COLOUR TYPE COLOUR BRIGHTNESS LEVEL VALUE 4H 5H 6H 7H Black 0H 0% 10% 30% 50% Blue 1H 30% 50% 70% 100% Red 2H 30% 50% 70% 100% Magenta 3H 30% 50% 70% 100% Green 4H 30% 50% 70% 100% Cyan 5H 30% 50% 70% 100% Yellow 6H 30% 50% 70% 100% White 7H 60% 70% 80% 100% Table 5 indicates how I2C-bus register settings control the colour and brightness. All colour registers are similar, they contain one on/off bit, two brightness bits and three colour type bits. To determine which colour is visible in the event two or more colours being displayed on the same position, the next priority scheme is followed. SA 17H DISPLAY SETTINGS REGISTER The FBDEL2 to FBDEL0 bits can adjust the fast blank delay in 8 steps of 1⁄2 a clock cycle (−8 to +7). 0H is mid-scale. The DUVPOL bit inverts the UV polarity of the border colours. The DVSPOL bit determines the active edge of the Vsync (see Fig.7). The DHSYNC bit determines the timing of the Hsync pulse (burstkey or Hsync). The DFPOL bit can invert the field identification of the incoming fields (see Fig.7). 1. Sub-select colour (SBS) 2. Sub-border colour (SB) 3. Main-select colour (MBS) 4. Main-border colour (MB) SA 18H PEDESTAL SETTINGS REGISTER 5. Background colour (BG). The PEDESTU3 to PEDESTU0 and PEDESTV3 to PEDESTV0 bits provide the U and V DAC outputs an offset of −8 to +7 LSB when the FBL is switched off. This can be used to adjust the white point of the system. SA 15H AND SA 16H DECODER REGISTERS The MVFILT and SVFILT bits can set the type of vertical filtering. The MUVPOL and SUVPOL bits invert the UV polarity of the incoming signals. The MVSPOL and SVSPOL bits determine the active edge of the Vsync (see Fig.7). MHSYNC and SHSYNC bits determine the timing of the Hsync pulse (burstkey or Hsync timing). The MFPOL and SFPOL bits can invert the field identification (ID) of the incoming fields (see Fig.7). 1996 Aug 13 18 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H Additional I2C-bus settings Table 6 Overview of additional I2C-bus sub-addresses DATA BYTE SA BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 20H PRIO note 1 note 1 note 1 MVRPN1 MVRPN0 SVRPN1 SVRPN0 21H MHRPO31 MHRPO30 MHRPO21 MHRPO20 MHRPO11 MHRPO10 MHRPO01 MHRPO00 22H MHRPN31 MHRPN30 MHRPN21 MHRPN20 MHRPN11 MHRPN10 MHRPN01 MHRPN00 23H MHPIC7 MHPIC6 MHPIC5 MHPIC4 MHPIC3 MHPIC2 MHPIC1 MHPIC0 24H MVPIC7 MVPIC6 MVPIC5 MVPIC4 MVPIC3 MVPIC2 MVPIC1 MVPIC0 25H MHDIS07 MHDIS06 MHDIS05 MHDIS04 MHDIS03 MHDIS02 MHDIS01 MHDIS00 26H MHDIS17 MHDIS16 MHDIS15 MHDIS14 MHDIS13 MHDIS12 MHDIS11 MHDIS10 27H MHDIS27 MHDIS26 MHDIS25 MHDIS24 MHDIS23 MHDIS22 MHDIS21 MHDIS20 28H MHDIS37 MHDIS36 MHDIS35 MHDIS34 MHDIS33 MHDIS32 MHDIS31 MHDIS30 29H MVDIS7 MVDIS6 MVDIS5 MVDIS4 MVDIS3 MVDIS2 MVDIS1 MVDIS0 2AH SHRPO31 SHRPO30 SHRPO21 SHRPO20 SHRPO11 SHRPO10 SHRPO01 SHRPO00 2BH SHRPN31 SHRPN30 SHRPN21 SHRPN20 SHRPN11 SHRPN10 SHRPN01 SHRPN00 2CH SHPIC7 SHPIC6 SHPIC5 SHPIC4 SHPIC3 SHPIC2 SHPIC1 SHPIC0 2DH SVPIC7 SVPIC6 SVPIC5 SVPIC4 SVPIC3 SVPIC2 SVPIC1 SVPIC0 2EH SHDIS07 SHDIS06 SHDIS05 SHDIS04 SHDIS03 SHDIS02 SHDIS01 SHDIS00 2FH SHDIS17 SHDIS16 SHDIS15 SHDIS14 SHDIS13 SHDIS12 SHDIS11 SHDIS10 30H SHDIS27 SHDIS26 SHDIS25 SHDIS24 SHDIS23 SHDIS22 SHDIS21 SHDIS20 31H SHDIS37 SHDIS36 SHDIS35 SHDIS34 SHDIS33 SHDIS32 SHDIS31 SHDIS30 32H SVDIS7 SVDIS6 SVDIS5 SVDIS4 SVDIS3 SVDIS2 SVDIS1 SVDIS0 Note 1. The data bits which are not used should be set to zero. be displayed by setting the Vertical Repetition Rate Number VRPN bits. The distance between the rows can be set by SVDIS and MVDIS bits. Every row is built-up of a maximum of four PIPs. The minimum is one PIP and the distance between the starting points of those PIPs on a row is determined by SHDIS and MHDIS bits. In Manual mode more PIP modes become available with the help of register 20H to 32H. An overview of these I2C-bus registers is given in Table 6. The meaning and relation of the I2C-bus registers is shown in Fig.8. The background has a fixed size and can be fine positioned with the BGHFP and BGHFP bits. The shown PIPs are only for one channel (Main or Sub), the other channel has the same control and can be displayed at the same time. The SDHFP and MDHFP bits determine the most left shown pixel for this channel in 256 steps of 4 pixels. The SDVFP and MDVFP bits determine the most upper shown line for this channel in 256 steps of 1 line. The SHPIC and MHPIC bits determine the horizontal picture size in 256 steps of 4 pixels, the minimum value is 4 pixels. The SVPIC and MVPIC bits determine the vertical picture size in 256 steps of 1 line, the minimum value is 1 line. The PIP mode is built-up of a maximum of four horizontal rows. The minimum is one row, more rows can 1996 Aug 13 SA 20H CONTROL REGISTER The PRIO bit sets the priority between Main and Sub channel. If PRIO is set to logic 0, priority is given to the Sub channel which means that the Sub channel PIPs, if present, are placed on top of the Main PIPs. If PRIO is set to logic 1, the Main PIPs are set on top of the Sub PIPs. The MVRPN and SVRPN bits determine the number of repeated PIP rows. There is always one row visible of each channel. If no PIPs should be visible the PIP channel must be switched off (SA 00, bit 7 or bit 6). 19 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H The reference levels are made internally by a resistor network which divides the analog supply voltage to a default set of preferred levels. External capacitors are needed to filter AC components on the reference levels. The resolution of the ADCs is 8 bit. Differential Non-Linearity (DNL) is 7-bit; Integral Non-Linearity (INL) is 6-bit, and the sampling is carried out at the system frequency of 27 MHz for the Y input. The U/V inputs are multiplexed and sampled at 13.5 MHz. The analog input signals are amplified to make maximum use of the dynamic range of the ADCs. A bias voltage Vbias is used for decoupling AC components on internal references. The inputs should be AC-coupled and an internal clamping circuit will clamp the input to AVrefB for the luminance SA 21H AND SA 2AH HORIZONTAL REPETITION OFFSET REGISTERS FOR ROW 0 TO 3 The horizontal repetition offsets (MHRPO and SHRPO bits) are strongly related to the horizontal distance (MHDIS and SHDIS bits). These registers set for each row a certain grid of possible starting points for the PIPS in that row. Every grid point has a number 0 (the most left PIP), 1, 2 or 3. The MHRPO and SHRPO bits determine the first PIP number which will be displayed. This mechanism can be set for each row. SA 22H AND SA 2BH HORIZONTAL REPETITION NUMBER REGISTERS FOR ROW 0 TO 3 The horizontal repetition numbers (MHRPN and SHRPN bits) determine how many times the PIPs are repeated in a row, once the first PIP is displayed. The repeated PIPs stay in the grid determined by the MHDIS and SHDIS bits for that row. This mechanism can be set for each row independent. AV refT – AV refB LSB channels and to ---------------------------------------- + ------------ for the 2 2 chrominance channels. The clamping starts at the active edge of the burst key. SA 23H AND SA 24H; SA 2CH AND SA 2DH PICTURE SIZE The digitally processed signals are converted to analog signals by three 8-bit DACs. The output voltages of these DACs are default set by the DAVrefT pin for the top level and DAVrefB pin for the bottom level. Default values are 1.5 V. Output DACs REGISTERS The MHPIC and SHPIC bits determine the horizontal PIP size in 256 steps of 4 pixels. The MVPIC and SVPIC bits determine the vertical PIP size in 256 steps of 1 line. External Memory SA 25H AND SA 29H; SA 2EH AND SA 32H PICTURE DISTANCE REGISTERS For the external memory two VDRAMs of type Mitsubishi M5M442256 are used. They have a storage capacity of 262 144 words of 4-bit each and will be used in parallel. For each row the distance between starting points of PIPs can be set with the bits MHDIS and SHDIS in 256 steps of 4 pixels. The distance between two rows can be set with the MVDIS and SVDIS bits in 256 steps of 1 line. It is also possible to use a 2 Mbit VDRAM with a storage capacity of 262 144 words of 8 bit each. An overview of the timing diagrams is given in Fig.9. Acquisition Channel ADCs Both channels convert the analog input signals to digital signals by means of two ADCs for each channel. The input levels of the ADCs of each channel are equal and can be set by the AVrefT and AVrefB pins. 1996 Aug 13 20 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H handbook, full Hpagewidth (external) sync field ID (internal) (number of pixels) 43 389 432 V sync (external) 1st field V sync (external) MBE100 2nd field Fig.7 Vertical synchronization timing and field identification. handbook, full pagewidth BGHFP BGVFP DVFP 1 + VRPN rows DHFP VPIC HPIC VDIS HDIS 1 + HRPN columns MGD583 Fig.8 Relation of display I2C-bus register. 1996 Aug 13 21 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H (1) handbook, full pagewidth CLOCK RAS CAS refresh cycle CLOCK (2) RAS CAS AD0 to AD8 ROW COLUMN COLUMN COLUMN COLUMN COLUMN WE DAO0 to DAO7 write cycle (main or sub) CLOCK (2) RAS CAS AD0 to AD8 ROW COLUMN WE DT read cycle SC DAI0 to DAI7 MGC970 (1) CLOCK = 13.5 MHz. (2) CLOCK = 27 MHz. shift clock cycles Fig.9 VDRAM timing 1996 Aug 13 22 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 +6.5 V Pmax maximum power dissipation − 1.5 W Tstg storage temperature −25 +150 °C Tamb operating ambient temperature −25 +70 °C Vesd electrostatic discharge handling Human body model 3000(1) V Machine model 300(2) V Note 1. Human body model: see UZW-B0/FQ-B302; The numbers of the quality specification can be found in the “Quality Reference Handbook”. The handbook can be ordered using the code 9397 750 00192. 2. Machine model: see UZW-B0/FQ-A302; The numbers of the quality specification can be found in the “Quality Reference Handbook”. The handbook can be ordered using the code 9397 750 00192. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 34 K/W QUALITY SPECIFICATION In accordance with “SNW-FQ-611 part E”. The numbers of the quality specification can be found in the “Quality Reference Handbook”. The handbook can be ordered using the code 9397 750 00192. 1996 Aug 13 23 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H CHARACTERISTICS VDD = 5.0 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD all positive supply voltages 4.5 5.0 5.5 V VSS all ground voltages − 0 − V ∆VDD(max) maximum difference between supply voltages − 0 100 mV ∆VSS(max) maximum difference between ground voltages − 0 100 mV IDDDQ quiescent current of digital supply voltages − 0 50 µA IMPVDDA main PLL supply current − 6 − mA ISPVDDA sub PLL supply current − 6 − mA IDPVDDA display PLL supply current − 6 − mA IMAVDDA main ADCs supply current − 40 − mA ISAVDDA sub ADCs supply current − 40 − mA IDAVDDA display DACs supply current − 20 − mA IDDA(tot) total analog supply current − 115 − mA IDDD(tot) total digital supply current − 100 − mA note 1 Analog-to-digital converter and clamping VrefT top reference voltage note 2 1.9 2.1 2.3 V VrefB bottom reference voltage note 2 0.3 0.4 0.5 V note 2 1.2 1.5 1.6 V clamping off − 0.1 − µA clamping on − 100 − µA − 5 − pF − 1728HS − MHz 6 8 − bit Vi(Y,U,V)(p-p) input signal amplitude (peak-to peak value) Ii input current Ci input capacitance fs sample frequency rate RES resolution note 3 DNL differential non-linearity −2.0 − +2.0 LSB INL integral non-linearity −4.0 − +4.0 LSB αcs channel separation − 48 − dB − 48 − dB − VrefB − V − note 5 − V PSRR power supply rejection ratio VclampY clamping voltage level Y VclampUV clamping voltage level U/V 1996 Aug 13 note 4 24 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SYMBOL SAB9076H PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital-to-analog converter and output stage VrefT top reference voltage 2.2 2.3 2.4 V VrefB bottom reference voltage 0.3 0.4 0.5 V Vo(Y,U,V) output signal amplitude − 1.5 1.6 RL load resistance CL load capacitance fs sample frequency rate note 6 note 6 note 3 V 75 220 10 × 0 − 50 pF − 1728HS − MHz 103 Ω RES resolution 6 8 8 bit DNL differential non-linearity −1.0 − +1.0 LSB INL integral non-linearity −1.0 − +1.0 LSB αcs channel separation − 48 − dB PSRR power supply rejection ratio − 48 − dB note 3 14 15.75 18 kHz note 3 14 15.75 18 kHz PLL and clock generation acquisition fi(PLL) input frequency PLL and clock generation display fi(PLL) input frequency Notes 1. Digital clocks are silent, POR is VDD. 2. The VrefT and VrefB are made by a resistor division of the VDD. They can be calculated with the formulas: 2.0 0.4 V refT = AV DD × -------- V and V refB = AV DD × -------- V 5.0 5.0 The analogue supply voltages are 5 V. 3. The internal system frequency is 1728 times the Hsync input frequency for both the acquisition and display PLLs. 4. The Y-channel is clamped to the VrefB of the ADCs. 5. The UV-channel is clamped to 1/2(VrefT + VrefB + VLSB). 6. The gain of the SAB9076H is 1 under the condition that the RL is 220 Ω. 1996 Aug 13 25 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H DC CHARACTERISTICS FOR THE DIGITAL PART VDDD = 4.5 to 5.5 V (all VDDD pins); Tamb = −20 to +75 °C; unless otherwise specified. SYMBOL VIH VIL PARAMETER HIGH level input voltage LOW level input voltage CONDITIONS MIN. TYP. MAX. UNIT HPF01 70 − − %VDD HPP01 70 − − %VDD HUP07 80 − − %VDD IOI41 70 − − %VDD HPF01 − − 30 %VDD HPP01 − − 30 %VDD HUP07 − − 20 %VDD IOI41 − − 30 %VDD Vhys hysteresis voltage HUP07 − 33 − %VDD VOH HIGH level output voltage OPF20; IOL = −2 mA; VDDD = 4.5 V 4.1 − − V VOL LOW level output voltage ILI input leakage current IOI41; IOL = +4 mA; VDDD = 4.5 V − − 0.4 V OPF20; IOL = +2 mA; VDDD = 4.5 V − − 0.4 V HPF01; VDDD = 5.5 V; note 1 − 0.1 1 µA HPP01; VDDD = 5.5 V; note 1 − 0.1 1 µA IOZ 3-state output leakage current IOI41; VDDD = 5.5 V; note 1 − 0.2 5 µA Rpu internal pull-up resistor 17 − 134 kΩ HUP07 Note 1. Vi is attached to the VDDD or VSSD. AC CHARACTERISTICS FOR THE DIGITAL PART VDDD = 4.5 to 5.5 V (all VDDD pins); Tamb = −20 to +75 °C; unless otherwise specified. SYMBOL PARAMETER fsys system frequency tr rise time tf fall time CONDITIONS MIN. TYP. MAX. UNIT acquisition; note 1 − 27 display; note 1 − 27 30 MHz − 6 25 ns − 6 25 ns 30 MHz Note 1. The internal system frequency is1728 times the Hsync input frequency for both the acquisition and display PLLs. 1996 Aug 13 26 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H The synchronization of the display PLL is derived from the deflection circuit. The main signals are also fed to the deflection circuit and the YUV/RGB switch where the SAB9076H signals can be inserted. The signals for deflection can also be taken from the main channel or sub-channel decoder. TEST AND APPLICATION INFORMATION The application diagram for 1 FH mode in a standard configuration is shown in Fig.10. Two input signals MCVBS and SCVBS of different sources are processed by the SAB9076H and inserted by the YUV/RGB switch. handbook, full pagewidth VDRAM 2 Mbit HS VS SCVBS DECODER SUB Y U V HS (1 FH) SAB9076H HS VS VS HS VS MCVBS DECODER MAIN YUV/RGB SWITCH AND DEFLECTION CIRCUIT FLB Y Y U U V V R YUV TO RGB G B R G HS VS main signals B Y U V MGC971 Fig.10 Application diagram for 1 FH mode. 1996 Aug 13 27 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H +5 V +5 V +5 V handbook, full pagewidth +5 V 100 +5 V 4 3 DAVDDA 83 DAVSSA DY DAVbias DV DAVrefT 89 88 87 86 85 84 DAVrefB DU DAVDDD DFB 92 90 DAVSSD 94 93 91 DVsync 95 DPHsync 98 96 DPVDDA DPVbias 1 99 DPVSSA 97 80 SPVbias 82 SPVDDA MPVbias MPVDDA MPVSSA MAVDDD SPVSSA 77 SAVDDD MAVSSD SAVSSD MPHsync SPHsync 2 HOUT 63 19 20 21 MCVSSD SCVSSD TDCLK POR TACLK SDA TC TM0 SCL n.c. 8 32, 34, 36, 38, 8 39, 37, 35, 33 43 23, 25, 40 31 47 48 49 51, 53, 44 27, 29, 9 55, 57, 58, 56, 30, 28, 54, 52, 26, 24 +5 V 50 2 Mbit MEMORY All capacitors are 100 nF. On the application board a ground plane should be used. Fig.11 Application diagram. 1996 Aug 13 TDA8315T −U Y 65 62 61 60 TM1 DAO0 to DAO7 22 +5 V −V 28 41 42 +5 V A0 45 59 VDDD 18 MCVDDD 68 SVSSD 66 SCVDDD MVSSD VSSD 16 CVBS/Y sub-channel input DCVDDD 15 +5 V MVDDD DCVSSD 13 +5 V 69 SAVSSA 67 SVDDD MAVSSA DVDDD 14 DVSSD 12 AD0 to AD8 +5 V CVBS/Y RAS CVBS/Y main-channel input VOUT +5 V CAS +5 V SAB9076H WE CVBS/Y HOUT SVsync 76 SAVbias 73 SV 72 SAVrefB 75 SU 74 SAVrefT 71 SY 70 SAVDDA DT Y MVsync 5 MAVbias 8 MV 9 MAVrefB 6 MU 7 MAVrefT 10 MY 11 MAVDDA SC −U 78 64 DAI0 to DAI7 −V TDA8315T +5 V 79 17 VOUT +5 V 81 46 +5 V MGC972 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT317-2 c y X 80 A 51 81 50 ZE Q e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp L 31 100 detail X 30 1 wM bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 20.1 19.9 14.1 13.9 0.65 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.4 1.2 0.2 0.15 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT317-2 1996 Aug 13 EUROPEAN PROJECTION 29 o 7 0o Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Aug 13 30 Philips Semiconductors Preliminary specification Picture-In-Picture (PIP) controller SAB9076H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Aug 13 31 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1996 SCA51 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/50/01/pp32 Date of release: 1996 Aug 13 Document order number: 9397 750 01016