INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4520B MSI Dual binary counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4520B MSI Dual binary counter LOW transition of the CP1 input if CP0 is low. Either CP0 or CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of CP0, CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0 to O3) and an active HIGH overriding asynchronous master reset input (MR). The counter advances on either the LOW to HIGH transition of the CP0 input if CP1 is HIGH or the HIGH to Fig.2 Pinning diagram. HEF4520BP(N): 16-lead DIL; plastic HEF4520BD(F): 16-lead DIL; ceramic (cerdip) (SOT38-1) (SOT74) HEF4520BT(D): 16-lead SO; plastic (SOT109-1) (SOT109-1) ( ): Package Designator North America Fig.1 Functional diagram. PINNING CP0A, CP0B clock inputs (L to H triggered) CP1A, CP1B clock inputs (H to L triggered) MRA, MRB master reset inputs O0A to O3A outputs O0B to O3B outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors Dual binary counter January 1995 Fig.3 Logic diagram (one counter). FUNCTION TABLE 3 CP0 CP1 MR MODE H L counter advances L counter advances L no change L no change L no change L no change H O0 to O3 = LOW L X X L H X X Notes Product specification HEF4520B MSI 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition Philips Semiconductors Product specification HEF4520B MSI Dual binary counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYPICAL EXTRAPOLATION FORMULA TYP. MAX. Propagation delays CP0 , CP1 → On 5 HIGH to LOW 10 110 220 ns 83 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 110 220 ns 83 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 75 150 ns 48 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 15 25 50 ns 17 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns tPHL 15 5 LOW to HIGH 10 tPLH 15 MR → On HIGH to LOW 5 10 tPHL Output transition times HIGH to LOW LOW to HIGH 10 tTHL pulse width; LOW 20 40 ns 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 tTLH 5 10 tWCPL 15 Minimum CP1 pulse width; HIGH 5 10 tWCPH 15 Minimum MR pulse width; HIGH 5 10 tWMRH 15 Recovery time for MR 5 10 tRMR 15 Set-up times CP0 → CP1 CP1 → CP0 Maximum clock pulse frequency 5 60 30 ns 30 15 ns 20 10 ns 60 30 ns 30 15 ns 20 10 ns 30 15 ns 20 10 ns 16 8 ns 50 25 ns 30 15 ns 20 10 ns 50 25 ns 30 15 ns 15 20 10 ns 5 50 25 ns 10 10 tsu 30 15 ns 15 20 10 ns 5 8 16 MHz 15 30 MHz 20 40 MHz 10 15 January 1995 6 ns + (0,28 ns/pF) CL 15 15 Minimum CP0 9 ns + (0,42 ns/pF) CL tsu fmax 4 10 ns + (1,0 ns/pF) CL see also waveforms Figs 4 and 5 Philips Semiconductors Product specification HEF4520B MSI Dual binary counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power 5 TYPICAL FORMULA FOR P (µW) 850 fi + ∑ (foCL) × VDD2 dissipation per 10 3 800 fi + ∑ (foCL) × VDD package (P) 15 10 200 fi + ∑ (foCL) × VDD2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑(foCL) = sum of outputs VDD = supply voltage (V) Fig.4 Waveforms showing recovery time for MR; minimum CP0, CP1 and MR pulse widths. January 1995 5 Philips Semiconductors Product specification HEF4520B MSI Dual binary counter Fig.5 Waveforms showing set-up times for CP0 to CP1 and CP1 to CP0, and propagation delays. January 1995 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors Dual binary counter January 1995 Fig.6 Timing diagram. 7 Product specification HEF4520B MSI WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com