Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor FEATURES SYMBOL PSMN003-25W QUICK REFERENCE DATA • ’Trench’ technology • Very low on-state resistance • Fast switching • Low thermal resistance d VDSS = 25 V ID = 100 A RDS(ON) ≤ 3.2 mΩ (VGS = 10 V) g RDS(ON) ≤ 3.5 mΩ (VGS = 5 V) s GENERAL DESCRIPTION SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:• d.c. to d.c. converters • switched mode power supplies PINNING PIN SOT429 (TO247) DESCRIPTION 1 gate 2 drain 3 source tab drain 1 2 3 The PSMN003-25W is supplied in the SOT429 (TO247) conventional leaded package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Continuous gate-source voltage Peak pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS MIN. MAX. UNIT Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 25 25 ± 15 V V V Tj ≤ 150 ˚C - ± 20 V - 55 1001 1001 300 300 175 A A A W ˚C Tmb = 25 ˚C; VGS = 5 V Tmb = 100 ˚C; VGS = 5 V Tmb = 25 ˚C Tmb = 25 ˚C 1 Maximum continuous current limited by package. October 1999 1 Rev 1.100 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN003-25W AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS EAS Non-repetitive avalanche energy Unclamped inductive load, IAS = 100 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 15 V; RGS = 50 Ω; VGS = 5 V; refer to fig:15 IAS Non-repetitive avalanche current MIN. MAX. UNIT - 162 mJ - 100 A THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. in free air TYP. MAX. UNIT - - 0.5 K/W - 45 - K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) IGSS IDSS Drain-source on-state resistance VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 4.5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C Gate-source leakage current VGS = ±5 V; VDS = 0 V; Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 175˚C TYP. MAX. UNIT 25 23 1 0.5 - 1.5 2.8 3.1 3.3 4.8 0.02 0.05 - 2 2.3 3.2 3.5 4.0 6.5 100 10 500 V V V V V mΩ mΩ mΩ mΩ nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 100 A; VDD = 15 V; VGS = 5 V - 219 30 113 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; RD = 0.6 Ω; VGS = 10 V; RG = 5.6 Ω Resistive load - 28 133 716 424 - ns ns ns ns Ld Ld Ls Internal drain inductance Internal drain inductance Internal source inductance Measured tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad - 3.5 4.5 7.5 - nH nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 12.6 3500 2400 - nF pF pF October 1999 2 Rev 1.100 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN003-25W REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge ISM October 1999 CONDITIONS MIN. TYP. MAX. UNIT - - 100 A - - 300 A IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V - 0.85 1.0 1.2 - V IF = 20 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 20 V - 250 1.5 - ns µC 3 Rev 1.100 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN003-25W Normalised Power Derating, PD (%) 1 Transient thermal impedance, Zth j-mb (K/W) 100 D = 0.5 90 80 0.2 0.1 70 0.1 60 0.05 50 40 P D 0.02 0.01 D = tp/T tp 30 20 T single pulse 10 0.001 1E-06 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Drain Current, ID (A) 10 V VGS = 3 V 100 Normalised Current Derating, ID (%) 100 90 90 Tj = 25 C 2.5 V 5V 80 80 2.4 V 70 70 60 60 50 50 40 40 30 30 20 2.3 V 2.2 V 2.1 V 20 10 2V 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 0 175 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb) 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID 1000 0.2 0.02 tp = 100 us Drain-Source On Resistance, RDS(on) (Ohms) 2V 0.018 2.1 V 2.2 V 2.3 V 2.5 V 2.4 V 0.016 1 ms 100 D.C. 0.014 0.012 10 ms 0.01 100 ms 0.008 10 0.006 5V 3V 0.004 VGS = 10V 0.002 1 Tj = 25 C 0 1 10 Drain-Source Voltage, VDS (V) 100 0 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp October 1999 10 20 30 40 50 60 Drain Current, ID (A) 70 80 90 100 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) 4 Rev 1.100 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN003-25W Threshold Voltage, VGS(TO) (V) Drain current, ID (A) 2.25 100 VDS > ID X RDS(ON) 90 2 80 1.75 70 1.5 maximum typical 60 1.25 50 1 40 minimum 175 C 0.75 30 20 0.5 Tj = 25 C 10 0.25 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 0 3 -60 -40 -20 0 Gate-source voltage, VGS (V) 200 60 80 100 120 140 160 180 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) VDS > ID X RDS(ON) 40 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) 220 20 Drain current, ID (A) 1.0E-01 VDS = 5 V Tj = 25 C 180 1.0E-02 160 175 C 140 1.0E-03 120 100 minimum typical maximum 1.0E-04 80 60 1.0E-05 40 20 0 1.0E-06 0 10 20 30 40 50 60 70 Drain current, ID (A) 80 90 100 0 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised On-state Resistance 100000 Capacitances, Ciss, Coss, Crss (pF) Ciss 10000 Coss Crss 1000 -60 -40 -20 0 20 40 60 80 100 Junction temperature, Tj (C) 120 140 160 180 0.1 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) October 1999 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 5 Rev 1.100 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN003-25W Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Maximum Avalanche Current, IAS (A) 1000 ID = 100 A VDD = 15 V Tj = 25 C 25 C 100 Tj prior to avalanche = 150 C 10 0 40 80 120 160 200 240 280 Gate charge, QG (nC) 320 360 400 1 0.001 440 0.01 0.1 1 10 Avalanche time, tAV (ms) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Source-Drain Diode Current, IF (A) 100 VGS = 0 V 90 80 70 60 50 40 175 C 30 Tj = 25 C 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj October 1999 6 Rev 1.100 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN003-25W MECHANICAL DATA Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247 SOT429 α E P A A1 β q S R D Y L1(1) Q b2 L 1 2 3 c w M b b1 e e 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 b2 c D E e L mm 5.3 4.7 1.9 1.7 1.2 0.9 2.2 1.8 3.2 2.8 0.9 0.6 21 20 16 15 5.45 16 15 (1) L1 4.0 3.6 P Q q R S w Y α β 3.7 3.3 2.6 2.4 5.3 3.5 3.3 7.5 7.1 0.4 15.7 15.3 6° 4° 17° 13° Note 1. Tinning of terminals are uncontrolled within zone L1. OUTLINE VERSION SOT429 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-04-07 99-08-04 TO-247 Fig.16. SOT429; pin 2 connected to mounting base Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT429 envelope. 3. Epoxy meets UL94 V0 at 1/8". October 1999 7 Rev 1.100 Philips Semiconductors Product specification N-channel logic level TrenchMOS transistor PSMN003-25W DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1999 8 Rev 1.100