Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET FEATURES PHB11N03LT, PHD11N03LT SYMBOL QUICK REFERENCE DATA • ’Trench’ technology • Low on-state resistance • Fast switching • Logic level compatible VDSS = 30 V d ID = 10.5 A RDS(ON) ≤ 150 mΩ (VGS = 5 V) g RDS(ON) ≤ 130 mΩ (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:• d.c. to d.c. converters • switched mode power supplies The PHB11N03LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD11N03LT is supplied in the SOT428 (DPAK) surface mounting package. PINNING SOT428 (DPAK) PIN DESCRIPTION 1 gate 2 drain 1 3 source SOT404 (D2PAK) tab tab 2 2 tab drain 1 1 3 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS VGSM ID Drain-source voltage Drain-gate voltage Gate-source voltage Pulsed gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 30 30 ± 15 ± 20 10.3 7.3 41 33 175 V V V V A A A W ˚C Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C 1 It is not possible to make contact to pin 2 of the SOT404 or SOT428 package September 1999 1 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHB11N03LT, PHD11N03LT AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy IAS Peak non-repetitive avalanche current CONDITIONS MIN. MAX. UNIT - 25 mJ - 10.3 A TYP. MAX. UNIT - 4.5 K/W 50 - K/W Unclamped inductive load, IAS = 3.3 A; tp = 220 µs; Tj prior to avalanche = 25˚C; VDD ≤ 15 V; RGS = 50 Ω; VGS = 5 V; refer to fig:15 THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS SOT428 and SOT404 package, pcb mounted, minimum footprint ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) Drain-source breakdown voltage Gate threshold voltage CONDITIONS MIN. VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) Drain-source on-state resistance VGS = 10 V; ID = 5.5 A VGS = 5 V; ID = 5.5 A gfs IGSS IDSS Forward transconductance VDS = 25 V; ID = 5.5 A Gate source leakage current VGS = ±5 V; VDS = 0 V Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Tj = 175˚C Tj = 175˚C TYP. MAX. UNIT 30 26 1.0 0.5 4 - 1.5 100 120 250 7 10 0.05 - 2.0 2.3 130 150 315 100 10 500 V V V V V mΩ mΩ mΩ S nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 10 A; VDD = 15 V; VGS = 5 V - 3.8 1.2 1.7 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; RD = 2.7 Ω; RG = 10 Ω; VGS = 5 V Resistive load - 6 64 20 26 16 80 30 40 ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 250 55 42 330 75 55 pF pF pF September 1999 2 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHB11N03LT, PHD11N03LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM September 1999 CONDITIONS MIN. TYP. MAX. UNIT - - 10.3 A - - 41 A IF = 10 A; VGS = 0 V - 1.15 1.5 V IF = 10 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 35 55 - ns nC 3 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHB11N03LT, PHD11N03LT Normalised Power Derating, PD (%) Transient thermal impedance, Zth j-mb (K/W) 10 100 90 D = 0.5 80 70 0.2 60 1 50 0.1 40 P D 0.05 D = tp/T tp 30 0.02 20 single pulse 10 0.1 1E-06 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 90 80 70 60 50 40 30 20 10 0 150 175 Tj = 25 C 5V VGS = 10V 3V 2.8 V 2.6 V 2.4 V 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) 0.5 Drain-Source On Resistance, RDS(on) (Ohms) 2.6 V 0.45 RDS(on) = VDS/ ID 2.8V Tj = 25 C 3V 2.4 V 0.4 tp = 10 us 10 0.35 100 us 3.2 V 0.3 3.4 V 0.25 1 ms 10 ms D.C. 1E+00 3.2 V Peak Pulsed Drain Current, IDM (A) 1 1E-01 3.4 V 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 100 1E-02 Drain Current, ID (A) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Normalised Current Derating, ID (%) 50 75 100 125 Mounting Base temperature, Tmb (C) 1E-03 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 100 25 1E-04 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 0 1E-05 T 0.2 5V 0.15 100 ms 0.1 VGS = 10V 0.05 0.1 0 1 10 Drain-Source Voltage, VDS (V) 100 0 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp September 1999 1 2 3 4 5 6 7 Drain Current, ID (A) 8 9 10 11 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) 4 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHB11N03LT, PHD11N03LT Drain current, ID (A) VDS > ID X RDS(ON) 9 Threshold Voltage, VGS(TO) (V) 2.25 10 2 8 1.75 7 1.5 6 1.25 5 maximum typical minimum 1 4 0.75 3 0.5 2 175 C 1 0.25 Tj = 25 C 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -60 -40 -20 Gate-source voltage, VGS (V) 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) 8 0 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) 1.0E-01 VDS > ID X RDS(ON) Drain current, ID (A) Tj = 25 C 7 1.0E-02 6 175 C 5 1.0E-03 minimum typical 4 1.0E-04 3 2 maximum 1.0E-05 1 1.0E-06 0 0 1 2 3 4 5 6 Drain current, ID (A) 7 8 9 0 10 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised On-state Resistance 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1000 Capacitances, Ciss, Coss, Crss (pF) Ciss 100 Coss Crss 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 0.1 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) September 1999 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 5 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHB11N03LT, PHD11N03LT Gate-source voltage, VGS (V) Maximum Avalanche Current, IAS (A) 100 ID = 10A VDD = 15 V Tj = 25 C 10 25 C 1 Tj prior to avalanche = 150 C 0 1 2 3 4 5 6 7 Gate charge, QG (nC) 8 9 0.1 0.001 10 0.01 0.1 1 10 Avalanche time, tAV (ms) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Source-Drain Diode Current, IF (A) 10 VGS = 0 V 9 8 7 6 5 175 C 4 3 Tj = 25 C 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj September 1999 6 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHB11N03LT, PHD11N03LT MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 OUTLINE VERSION D max. D1 E 11 1.60 1.20 10.30 9.70 e Lp HD Q 2.54 2.90 2.10 15.40 14.80 2.60 2.20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 SOT404 Fig.16. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". September 1999 7 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHB11N03LT, PHD11N03LT MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.17. SOT404 : soldering pattern for surface mounting. September 1999 8 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHB11N03LT, PHD11N03LT MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) SOT428 seating plane y A E A2 A A1 b2 D1 mounting base E1 D HE L2 2 L1 L 1 3 b1 w M A b c e e1 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.38 2.22 A1(1) A2 b b1 max. b2 c 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 D1 E D max. max. max. 6.22 5.98 4.81 4.45 6.73 6.47 E1 min. 4.0 e e1 2.285 4.57 HE max. L 10.4 9.6 2.95 2.55 L1 min. L2 w y max. 0.5 0.7 0.5 0.2 0.2 Note 1. Measured from heatsink back to lead. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT428 EUROPEAN PROJECTION ISSUE DATE 98-04-07 Fig.18. SOT428 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". September 1999 9 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHB11N03LT, PHD11N03LT MOUNTING INSTRUCTIONS Dimensions in mm 7.0 7.0 2.15 1.5 2.5 4.57 Fig.19. SOT428 : soldering pattern for surface mounting. September 1999 10 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHB11N03LT, PHD11N03LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 1999 11 Rev 1.000