PHILIPS PCK2022RDGG

INTEGRATED CIRCUITS
PCK2022R
CK00 (100/133 MHz) spread spectrum
differential system clock generator
Product specification
Supersedes data of 2000 Aug 08
2000 Nov 13
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum
differential system clock generator
FEATURES
PCK2022R
PIN CONFIGURATION
• 3.3 V operation
• Eight differential CPU clock pairs
• One IO clock at 33 MHz and 66 MHz
• Two 48 MHz clocks at 3.3 V
• One 14.318 MHz reference clock
• Power management control pins
• Host clock jitter less than 200 ps cycle-to-cycle
• Host clock skew less than 150 ps pin-to-pin
• Spread Spectrum capability
IOCLK
1
48 SEL100/133
VDD
2
47 VSS
48M_0/SELA
3
46 VDDA
48M_1/SELB
4
45 VSSA
VSS
5
44 PWRDWN
VDD
6
43 VDD
HCLK0
7
42 HCLK4
HCLKB0
8
41 HCLKB4
VSS
9
40 VSS
HCLK1 10
HCLKB1 11
VDD
DESCRIPTION
12
HCLK2 13
The PCK2022R is a clock synthesizer/driver for a Pentium III and
other similar processors
HCLKB2 14
VSS 15
The PCK2022R has eight differential pair CPU current source
outputs, one 33/66 MHz output which is configurable on power-up,
two 48 MHz clocks which can be disabled on power-up, and one
3.3 V reference clock at 14.318 MHz which can also be disabled on
power-up. All clock outputs meet Intel’s drive strength, rise/fall times,
jitter, accuracy, and skew requirements.
HCLK3 16
HCLKB3 17
VDD 18
The part possesses a dedicated power-down input pin for power
management control. This input is synchronized on chip, and
ensures glitch-free output transitions. In addition, the part can be
configured to disable the 48 MHz outputs for lower power operation
and an increase in the performance of the functioning outputs. The
IOCLK and REFCLK can also be disabled for the highest
performance of the Host outputs.
39 HCLK5
38 HCLKB5
37 VDD
36 HCLK6
35 HCLKB6
34 VSS
33 HCLK7
32 HCLKB7
31 VDD
REFCLK/SELC 19
30 MULTSEL0
SPREAD 20
29 MULTSEL1
VSS 21
28 VSS
XIN 22
27 VSSA
XOUT 23
VDD 24
26 IREF
25 VDDA
SW00665
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
48-Pin Plastic TSSOP
0°C to +70°C
PCK2022R DGG
SOT362-1
Intel and Pentium III are trademarks of Intel Corporation.
2000 Nov 13
2
853–2225 25005
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
PIN DESCRIPTION
PIN(S)
SYMBOL
FUNCTION
1
IOCLK
Dual frequency pin which can operate at either 33 MHz or 66 MHz per the selection table.
3, 4
48M_0/SELA
48M_1/SELB
3.3 V fixed 48 MHz clock outputs. During power-up pins function as latched inputs that enable SELA and
SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in.
7, 8
HCLK0
HCLKB0
Host output pair 0
10, 11
HCLK1
HCLKB1
Host output pair 1
13, 14
HCLK2
HCLKB2
Host output pair 2
16, 17
HCLK3
HCLKB3
Host output pair 3
42, 21
HCLK4
HCLKB4
Host output pair 4
39, 38
HCLK5
HCLKB5
Host output pair 5
36, 35
HCLK6
HCLKB6
Host output pair 6
33, 32
HCLK7
HCLKB7
Host output pair 7
19
REFCLK/SELC
3.3 V fixed 14.318 MHz output. During power-up, pin functions as a latched input that enables SELC prior
to the pin being used for the clock output. Part must be clocked to latch data in.
20
SPREAD
Enables spread spectrum mode when held LOW on differential host outputs and 33 MHz IOCLK clocks.
Asserts LOW.
21
XIN
Crystal input
22
XOUT
Crystal output
26
IREF
This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the correct current.
29, 30
MULTSEL0
MULTSEL1
Select input pin used to control the scaling of the HCLK and HCLKB output current.
44
PWRDWN
Device enters power-down mode when held LOW. Asserts LOW.
48
SEL100/133
Select input pin for enabling 133 MHz or 100 MHz CPU outputs
2, 6, 12,
18, 24, 31,
37, 43
VDD3
3.3 V power supply
5, 9, 15,
21, 28, 34,
40, 47
GND
Ground
25, 46
AVDD
3.3 V power supply for analog circuits
27, 45
AGND
Ground for analog circuits
2000 Nov 13
3
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
BLOCK DIAGRAM
REF[0] (14.318 MHz)
PWRDWN
XIN
SELC
14.318 MHz
OSC
XOUT
USB PLL
48MHz[0..1] (3 V)
PWRDWN
SELA/B
HOST[0..7] (100/133 MHz)
PWRDWN
IREF
IBIAS
PWRDWN
HOST_BAR[0..7] (100/133 MHz)
PWRDWN
IOCLK (33/66 MHz)
SYS PLL
PWRDWN
SEL100/133
LOGIC
SPREAD
MULTSEL0
MULTSEL1
SW00666
FUNCTION TABLE
SEL100/133
SELA
SELB
SELC
HOST
48MHz
IOCLK
REFCLK
0
0
0
0
100 MHz
48 MHz
33.3 MHz
14.318 MHz
0
0
0
1
100 MHz
48 MHz
66.7 MHz
14.318 MHz
0
0
1
0
100 MHz
Hi-Z
33.3 MHz
14.318 MHz
0
0
1
1
100 MHz
Hi-Z
66.7 MHz
14.318 MHz
0
1
0
0
100 MHz
Hi-Z
Low
Low
33.3 MHz
14.318 MHz
Hi-Z
Hi-Z
MHz1
0
1
0
1
100 MHz
0
1
1
0
Low
48
MHz1
Hi-Z
0
1
1
1
100 MHz
48
66.7 MHz
14.318 MHz
1
0
0
0
133 MHz
48 MHz
33.3 MHz
14.318 MHz
1
0
0
1
133 MHz
48 MHz
66.7 MHz
14.318 MHz
1
0
1
0
133 MHz
Hi-Z
33.3 MHz
14.318 MHz
1
0
1
1
133 MHz
Hi-Z
66.7 MHz
14.318 MHz
1
1
0
0
200 MHz
48 MHz
33.3 MHz
14.318 MHz
1
1
0
1
133 MHz
48 MHz1
33.3 MHz
14.318 MHz
1
1
1
0
TCLK/2
TCLK/4
TCLK/4
TCLK
133 MHz
MHz1
66.7 MHz
14.318 MHz
1
1
1
1
48
NOTE:
1. These frequencies are for debug, and thus can vary a small amount from the values listed at the vendor’s discretion.
2000 Nov 13
4
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
Table 1. Host swing select functions
MULTSEL0
MULTSEL1
BOARD
IMPEDANCE
IREF
IOH
VOH @ IREF = 2.32 mA
0
0
60 Ω
RREF = 475 1%
IREF = 2.32 mA
IOH = 5*IREF
0.71 V
0
0
50 Ω
RREF = 475 1%
IREF = 2.32 mA
IOH = 5*IREF
0.59 V
0
1
60 Ω
RREF = 475 1%
IREF = 2.32 mA
IOH = 6*IREF
0.85 V
0
1
50 Ω
RREF = 475 1%
IREF = 2.32 mA
IOH = 6*IREF
0.71 V
1
0
60 Ω
RREF = 475 1%
IREF = 2.32 mA
IOH = 4*IREF
0.56 V
1
0
50 Ω
RREF = 475 1%
IREF = 2.32 mA
IOH = 4*IREF
0.47 V
1
1
60 Ω
RREF = 475 1%
IREF = 2.32 mA
IOH = 7*IREF
0.99 V
1
1
50 Ω
RREF = 475 1%
IREF = 2.32 mA
IOH = 7*IREF
0.82 V
0
0
30 Ω
RREF = 221 1%
IREF = 5 mA
IOH = 5*IREF
0.75 V
0
0
25 Ω
RREF = 221 1%
IREF = 5 mA
IOH = 5*IREF
0.62 V
0
1
30 Ω
RREF = 221 1%
IREF = 5 mA
IOH = 6*IREF
0.90 V
0
1
25 Ω
RREF = 221 1%
IREF = 5 mA
IOH = 6*IREF
0.75 V
1
0
30 Ω
RREF = 221 1%
IREF = 5 mA
IOH = 4*IREF
0.60 V
1
0
25 Ω
RREF = 221 1%
IREF = 5 mA
IOH = 4*IREF
0.50 V
1
1
30 Ω
RREF = 221 1%
IREF = 5 mA
IOH = 7*IREF
1.05 V
1
1
25 Ω
RREF = 221 1%
IREF = 5 mA
IOH = 7*IREF
0.84 V
MIN.
MAX.
NOTE:
The outputs are optimized for the configurations shown shaded.
CONDITIONS
CONFIGURATION
LOAD
IOUT
VDD = 3.3 V
All combinations;
see Table 1 above
Nominal test load for
given configuration
–7% of IOH
see Table 1 above
+7% of IOH
see Table 1 above
IOUT
VDD = 3.3 V ±5%
All combinations;
see Table 1 above
Nominal test load for
given configuration
–12% of IOH
see Table 1 above
+12% of IOH
see Table 1 above
POWER-DOWN MODE
PWRDWN
HCLK/HCLKB
IOCLK
48MHz
REFCLK
Asserts LOW
0 = Active
Host = 2*IREF
Host_bar = undriven
LOW
LOW
LOW
NOTE:
The differential outputs should have a voltage forced across them when power-down is asserted.
SPREAD SPECTRUM FUNCTION
2000 Nov 13
SPREAD #
FUNCTION
48 MHz PLL
REFCLK
1
Host/IOCLK
No Spread
No Spread
0
Host/IOCLK
Down spread –0.5%
No Spread
5
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VDD3
PARAMETER
CONDITIONS
DC 3.3 V supply
LIMITS
MIN
MAX
–0.5
IIK
DC input diode current
VI < 0
VI
DC input voltage
IOK
DC output diode current
Note 2
VO
DC output voltage
IO
DC output source or sink current
–0.5
VO > VDD or VO < 0
Note 2
Tstg
Storage temperature range
Ptot
Power dissipation per package
plastic medium-shrink (SSOP)
–0.5
UNIT
4.6
V
–50
mA
VDD
V
±50
mA
VDD+0.5
V
±50
mA
+150
°C
850
mW
VO = 0 to VDD
–65
For temperature range –40°C to +125°C;
above +55°C derate linearly with 11.3 mW/K
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other condition beyond those indicated under “recommended operating condition” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage rating may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
MIN
MAX
UNIT
VDD3
DC 3.3 V supply voltage
3.135
3.465
V
AVDD
DC 3.3 V analog supply voltage
3.135
3.465
V
10
10
10
30
20
20
pF
pF
pF
14.31818
14.31818
MHz
0
+70
°C
CL
fref
Tamb
Capacitive load on:
IOCLK
48 MHz clock
REF
Must meet IOCLK 2.1 requirements
1 device load
1 device load
Reference frequency, oscillator normal value
Operating ambient temperature range in free air
POWER MANAGEMENT
CONDITION
MAXIMUM 3.3 V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAPACITANCE LOADS
VDDL = 3.465 V
ALL STATIC INPUTS = VDD3 OR VSS
Power-down mode (PWRDWN = 0)
60 mA
Full active 100/133 MHz
250 mA
2000 Nov 13
6
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C
SYMBOL
PARAMETER
CONDITIONS
VDD (V)
LIMITS
OTHER
MIN
TYP
MAX
UNIT
VIH
HIGH level input voltage
3.135 to 3.465
2.0
VDD+0.3
V
VIL
LOW level input voltage
3.135 to 3.465
VSS–0.3
0.8
V
VOH3
3.3 V output HIGH voltage
REF, 48M
3.135 to 3.465
IOH = –1 mA
2.0
–
V
VOL3
3.3 V output LOW voltage
REF, 48M
3.135 to 3.465
IOH = 1 mA
–
0.4
V
VOHP
3.3 V output HIGH voltage
IOCLK
3.135 to 3.465
IOH = –1 mA
2.4
–
V
VOLP
3.3 V output LOW voltage
IOCLK
3.135 to 3.465
IOH = 1 mA
–
0.55
V
Output HIGH current
IOCLK
3.135
VOUT = 1.0 V
3.465
VOUT = 3.135 V
IOH
O
Output HIGH current
48 MHz, REF
3.135
VOUT = 1.0 V
3.465
VOUT = 3.135 V
IOH
O
Output HIGH current
HOST/HOST_BAR
IOL
O
Output LOW current
IOCLK
3.135
VOUT = 1.95 V
3.465
VOUT = 0.4 V
Output LOW current
48 MHz, REF
3.135
VOUT = 1.95 V
3.465
VOUT = 0.4 V
VSS = 0 V
RS = 33.2 Ω
RP = 49.9 Ω
3.465
0 < VIN < VDD3
3.465
VOUT =
VDD or GND
IOH
O
IOL
O
VOL
O
±II
HOST/HOST BAR
HOST/HOST_BAR
Input leakage current
±IOZ
3-State output
OFF-State current
3 135 to 3
3.135
3.465
465
0.66 V
0.76 V
Type
y 5
12 – 55 Ω
–33
Type
y 3
20 – 60 Ω
–29
Type X1
mA
–33
mA
–23
11
30
Type
y 3
20 – 60 Ω
29
–50
IO = 0
mA
mA
38
Type X1
mA
mA
12.7
Type
y 5
12 – 55 Ω
mA
mA
mA
27
mA
0 05
0.05
V
50
µA
10
µA
Cin
Input pin capacitance
5
pF
Cout
Output pin capacitance
6
pF
Cxtal
Crystal input capacitance
22.5
pF
2000 Nov 13
13.5
7
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
AC ELECTRICAL CHARACTERISTICS
VDD3 = 3.3 V ±5%; fcrystal = 14.31818 MHz
Host clock outputs
Tamb = 0°C to +70°C; see Figure 1 for waveforms and Figure 6 for test setup.
LIMITS
133 MHz MODE
100 MHz MODE
MIN
MAX
MIN
MAX
HOST CLK average period
7.5
7.65
10.0
Absolute minimum host clock period
7.35
N/A
9.85
tRISE
HOST CLK rise time
175
700
tFALL
HOST CLK fall time
175
700
SYMBOL
PARAMETER
tPKP
Abs Min Period
tJITTER
HOST_CLK cycle-to-cycle jitter
DUTY CYCLE
Output duty cycle
UNITS
NOTES
10.2
ns
11, 14, 20
N/A
ns
11, 14, 20
175
700
ns
11, 15, 20
175
700
ps
11, 15, 20
150
ps
11, 12, 14, 20
55
%
11, 14, 20
ps
11, 14, 20
150
45
55
45
tSKEW
HOST CLK pin-to-pin skew
150
150
Rise/Fall Matching
Rise and Fall time matching
20%
20%
Vcrossover
40% VOH
55% VOH
40% VOH
55% VOH
11, 16, 20
V
11, 14, 20
UNITS
NOTES
REFER TO NOTES ON PAGE 9.
IOCLK outputs
Tamb = 0°C to +70°C
LIMITS
SYMBOL
PARAMETER
33 MHz MODE
66 MHz MODE
MIN
MAX
MIN
MAX
tPKP
IOCLK period
30.0
N/A
15.0
N/A
ns
2, 3, 9, 20
tPKH
IOCLK HIGH time
12.0
N/A
6.0
N/A
ns
5, 10, 20
tPKL
IOCLK LOW time
12.0
N/A
6.0
N/A
ns
6, 10, 20
tRISE
IOCLK rise time
0.5
2.0
0.5
2.0
ns
8, 20
tFALL
IOCLK fall time
0.5
2.0
0.5
2.0
ns
8, 20
200
ps
18, 20
55
%
18, 20
UNITS
NOTES
MHz
4
tJITTER
DUTY CYCLE
Cycle-to-cycle jitter
200
Output duty cycle
45
55
45
REFER TO NOTES ON PAGE 9.
USB clock output, 48MHz
Tamb = 0°C to +70°C; lump capacitance test load = 20 pF
LIMITS
SYMBOL
48 MHz MODE
PARAMETER
MIN
f
Frequency, actual
fD
Deviation from 48 MHz
MAX
48.08
ppm
4
tHKL
3V48MHZCLK LOW time
5.05
N/A
ns
20
tRISE
3V48MHZCLK rise time
1.0
4.0
ns
8, 20
tFALL
3V48MHZCLK fall time
1.0
4.0
ns
8, 20
250
ps
18, 20
55
%
18, 20
tJITTER
DUTY CYCLE
+167
Cycle-to-cycle jitter
Output duty cycle
45
REFER TO NOTES ON PAGE 9.
2000 Nov 13
8
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
REF clock output
Tamb = 0°C to +70°C; lump capacitance test load = 20 pF
LIMITS
SYMBOL
48 MHz MODE
PARAMETER
MIN
f
UNITS
NOTES
MAX
MHz
17, 20
tHKL
Frequency, actual
REFCLK LOW time
30
37
ns
20
tHKH
REFCLK HIGH time
30
37
ns
20
tJITTER
Cycle-to-cycle jitter
300
ps
18, 20
55
%
18, 20
UNITS
NOTES
ns
20
DUTY CYCLE
14.318
Output duty cycle
45
REFER TO NOTES ON PAGE 9.
All outputs
Tamb = 0°C to +70°C
LIMITS
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
MIN
MAX
MIN
MAX
tPZL, tPZH
Output enable delay (all outputs)
1.0
10.0
1.0
10.0
tPZL, tPZH
Output disable delay (all outputs)
1.0
10.0
1.0
10.0
ns
20
3
ms
7, 20
tSTABLE
All clock stabilization from power-up
3
REFER TO NOTES ON PAGE 9.
Group offset limits
GROUP
OFFSET
MEASUREMENT LOADS
(LUMPED)
MEASUREMENT POINTS
NOTES
Host to IOCLK
1.5 – 3.5 ns
Host leads
IOCLK @ 30 pF
Host @ Cross point
IOCLK @ 1.5 V
19, 20
NOTES TO THE AC TABLES:
1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels.
2. Period, jitter, offset, and skew measured on rising edge at 1.5 V for 3.3 V clocks.
3. The IOCLK clock is the Host clock divided by 4 in 33 MHz mode and divided by 2 in 66 MHz mode at Host = 133 MHz.
IOCLK clock is the Host clock divided by 3 in 33 MHz and divided by 2/3 in 66 MHz mode at Host = 100 MHz.
4. Frequency accuracy of 48 MHz must be +167 ppm to match USB default.
5. tHKH is measured at 2.4 V for 3.3 V outputs, as shown in Figure 7.
6. tHKL is measured at 0.4 V for all outputs as shown in Figure 7.
7. the time is specified from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable
and operating within specification.
8. tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification.
9. The average period over any 1 µs period of time must be greater than the minimum specified period.
10. Calculated at minimum edge rate (1 V/ns) to guarantee 45–55% duty cycle. Pulse width is required to be wider at faster edge rate to ensure
duty specification is met.
11. Test load is RS = 33.2 Ω, RP = 49.9 Ω.
12. Must be guaranteed in a realistic system environment.
13. Configured for VOH = 0.71 V in a 50 Ω environment.
14. Measured at crossing points.
15. Measured at 20% to 80%.
16. Determined as a fraction of 2*(tRP – tRN) / (tRP + tRN), where tRP is a rising edge, and tRN is an intersecting falling edge.
17. Frequency generated by crystal oscillator
18. Voltage measure point (VM = 1.5 V). VDD = 3.3 V.
19. All offsets are to be measured at rising edges.
20. Parameters are guaranteed by design.
2000 Nov 13
9
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
AC WAVEFORMS
VM = 1.25 V @ VDDL and 1.5 V @ VDD3
VX = VOL + 0.3 V
VY = VOH – 0.3 V
VOL and VOH are the typical output voltage drop that occur with the output load.
VOH
HOST CLK
50%
VI
50%
SEL1,
SEL0
VSS
VM
GND
VOH
HOST_BAR
CLK
50%
tPLZ
VSS
tPZL
VDD
tSKEW
OUTPUT
LOW-to-OFF
OFF-to-LOW
tPERIOD
SW00667
VM
VX
VOL
Figure 1. HOST CLOCK
tPHZ
tPZH
VOH
COMPONENT
MEASUREMENT
POINTS
VOH = 2.4 V
VOL = 0.4 V
VY
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
VDDL
VIH = 2.0 V
1.5 V
VIL = 0.7 V
VSS
SYSTEM
MEASUREMENT
POINTS
VSS
VM
outputs
enabled
outputs
disabled
SW00662
Figure 3. State enable and disable times
SW00668
Figure 2. 3.3 V clock waveforms
VDD
S1
2 VDD
Open
VSS
500 Ω
VI
VO
PULSE
GENERATOR
DUT
RT
CL
TEST
S1
tPLH/tPHL
Open
tPLZ/tPZL
2 VDD
tPHZ/tPZH
VSS
500 Ω
VDD = VDDL or VDD3, depending on the output.
SW00660
Figure 4. Load circuitry for switching times
2000 Nov 13
outputs
enabled
10
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
PWRDWN
HOST CLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
HOST CLK
(EXTERNAL)
PCICLK
(EXTERNAL)
Á
Á
Á
Á
OSC & VCO
USB (48 MHz)
SW00669
Figure 5. Power management
VDD
CL
CRYSTAL
14.318 MHz
RP = 50 Ω
RS
HOST
RS = 33.2 Ω
DUT
HOST_BAR
RS
CL
RP = 50 Ω
SW00671
Figure 6. HOST CLOCK measurements
tPKP
DUTY CYCLE
tPKH
3.3V CLOCKING
INTERFACE
2.4 V
1.5 V
0.4 V
tPKL
tRISE
tFALL
SW00659
Figure 7. 3.3 V clock waveforms
2000 Nov 13
11
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum
differential system clock generator
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
2000 Nov 13
12
PCK2022R
SOT362-1
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum
differential system clock generator
NOTES
2000 Nov 13
13
PCK2022R
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum
differential system clock generator
PCK2022R
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 11-00
Document order number:
2000 Nov 13
14
9397 750 07756