INTEGRATED CIRCUITS 74LVC821A 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) Product specification 1998 Sep 25 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) FEATURES 74LVC821A DESCRIPTION • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Supply voltage range of 2.7V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface with TTL levels • 10-bit positive edge-triggered register • Independent register and 3-State buffer operation • Flow-through pin-out architecture The 74LVC821A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC821A is a10-bit D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The ten flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the ten flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns PARAMETER SYMBOL tPHL/tPLH fmax CONDITIONS Propagation delay CP to Qn CL = 50 pF; VCC = 3 3.3 3V Maximum clock frequency CI Input capacitance Power dissipation capacitance per flip-flop CPD Notes 1 and 2 TYPICAL UNIT 5.4 ns 150 MHz 5.0 pF 26 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION TEMPERATURE RANGE ORDERING CODE PKG. DWG. # 24-Pin Plastic SO PACKAGES –40°C to +85°C 74LVC821A D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74LVC821A DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC821A PW SOT355-1 1998 Sep 25 2 853-1970 20088 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) 74LVC821A PIN DESCRIPTION PIN NUMBER SYMBOL 1 OE NAME AND FUNCTION Output enable input (active LOW) 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 D0 to D9 Data inputs 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 Q0 to Q9 3-State flip-flop outputs 12 GND Ground (0 V) 13 CP Clock input (LOW-to-HIGH, edge-triggered) 24 VCC Positive supply voltage FUNCTION TABLE INPUTS OPERATING MODES OUTPUTS FLOPS INTERNAL FLIP FLIP-FLOPS OE CP Dn Load and read register L L ↑ ↑ l h L H L H Load register and disable outputs H H ↑ ↑ l h L H Z Z Hold L H or L X NC NC H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state ↑ = LOW–to–HIGH clock transition NC= no change PIN CONFIGURATION LOGIC SYMBOL 13 OE 1 24 VCC D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 D5 7 18 Q5 D6 8 17 Q6 D7 9 16 Q7 D8 10 15 Q8 D9 11 GND 12 14 13 Q9 CP CP Q0 23 D1 Q1 22 4 D2 Q2 21 5 D3 Q3 20 6 D4 Q4 19 2 D0 3 7 D5 Q5 18 8 D6 Q6 17 9 D7 Q7 16 Q8 15 Q9 14 10 D8 11 D9 OE SA00413 1 SA00414 1998 Sep 25 3 Q0 to Q9 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) LOGIC SYMBOL (IEEE/IEC) 13 74LVC821A FUNCTIONAL DIAGRAM 2 D0 Q0 23 3 D1 Q1 22 C1 1 EN 2 1D 3 4 D2 Q2 21 23 5 D3 Q3 20 22 6 D4 Q4 19 Q5 18 3–STATE OUTPUTS FF0 to FF9 4 21 7 D5 5 20 8 D6 Q6 17 6 19 9 D7 Q7 16 7 18 10 17 D8 Q8 15 8 16 11 D9 Q9 14 9 10 15 13 CP 11 14 1 OE SA00416 SA00415 LOGIC DIAGRAM D1 D0 D Q D CP Q D CP Q D4 D CP FF1 FF0 D3 D2 Q D CP FF2 D5 Q D CP FF3 D6 Q D CP FF4 D7 Q D CP FF5 D8 Q D CP FF6 D9 Q D CP FF7 Q CP FF8 FF9 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 SA00417 1998 Sep 25 4 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) 74LVC821A RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VI VO PARAMETER CONDITIONS UNIT MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 DC Input voltage range 0 5.5 DC output voltage range; output HIGH or LOW state 0 VCC DC output voltage range; output 3-State 0 5.5 –40 +85 °C 0 0 20 10 ns/V V Tamb Operating ambient temperature range in free-air tr, tf Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V V V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC CONDITIONS UNIT –0.5 to +6.5 V IIK DC input diode current VI t0 –50 mA VI DC input voltage Note 2 –0.5 to +6.5 V IOK DC output diode current VO uVCC or VO t 0 "50 mA DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5 DC output voltage; output 3-State Note 2 –0.5 to 6.5 DC output source or sink current VO = 0 to VCC VO IO IGND, ICC Tstg PTOT DC supply voltage RATING DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K V "50 mA "100 mA –65 to +150 °C 500 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Sep 25 5 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) 74LVC821A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C TYP1 MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VOL II VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 VCC = 1.2V GND V LOW level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –18mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*0.8 VCC V VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.55 V "0 1 "0.1 "5 µA VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND 0.1 "5 µA Power off leakage supply VCC = 0.0V; VI or VO = 5.5V 0.1 "10 µA Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA Input leakage current VCC = 3 3.6V; 6V; VI = 5 5.5V 5V or GND IOZ 3-State output OFF-state current Ioff ICC ∆ICC V VCC = 2.7 to 3.6V HIGH level output voltage UNIT MAX NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state. AC CHARACTERISTICS GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL tPHL tPLH tPZH tPZL tPHZ tPLZ tW tSU th fmax PARAMETER Propagation delay CP to Qn 3-State output enable time OE to Qn 3-State output disable time OE to Qn Clock pulse width HIGH or LOW Setup time Dn to CP Hold time Dn to CP Maximum clock pulse frequency VCC = 3.3V ±0.3V WAVEFORM UNIT TYP1 MAX MIN MAX Figures 1, 4 1.5 5.4 7.3 1.5 8.5 ns Figures 2, 4 1.5 5.5 7.6 1.5 8.8 ns Figures 2, 4 1.5 3.8 6.2 1.5 6.8 ns Figure 1 3.3 1.7 – 3.3 – ns Figure 3 1.9 0.6 – 0.9 – ns Figure 3 1.5 0 – 1.5 – ns Figure 1 150 200 – 150 – MHz NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Sep 25 VCC = 2.7V MIN 6 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) 74LVC821A AC WAVEFORMS VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V VI CP INPUT VM GND tsu tsu ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ th th 1/fmax VI VI VM CP INPUT VM Dn INPUT VM VM GND GND tw tPHL VM Qn OUTPUT VOH Qn OUTPUT tPLH VOH VM VM VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VOL SA00394 SW00229 Figure 3. Data setup and hold times for the Dn input to the CP input. Figure 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. TEST CIRCUIT VI S1 VCC OE INPUT VM GND PULSE GENERATOR tPLZ VI tPZL RT 50pF CL 500Ω VM Test VX VOL tPHZ tPZH VOH OUTPUT HIGH-to-OFF OFF-to-HIGH S1 VCC VI tPLH/tPHL Open t 2.7V VCC tPLZ/tPZL 2 x VCC 2.7V – 3.6V 2.7V tPHZ/tPZH GND SY00003 VY VM GND outputs enabled outputs disabled Figure 4. Load circuitry for switching times. outputs enabled SA00412 Figure 2. 3-State enable and disable times. 1998 Sep 25 500Ω VO D.U.T. VCC OUTPUT LOW-to-OFF OFF-to-LOW 2 x VCC Open GND 7 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) SO24: plastic small outline package; 24 leads; body width 7.5 mm 1998 Sep 25 8 74LVC821A SOT137-1 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm 1998 Sep 25 9 74LVC821A SOT340-1 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm 1998 Sep 25 10 74LVC821A SOT355-1 Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) NOTES 1998 Sep 25 11 74LVC821A Philips Semiconductors Product specification 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) 74LVC821A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 08-98 9397–750–04584