INTEGRATED CIRCUITS DATA SHEET CGY2030M DECT 500 mW power amplifier Product specification Supersedes data of 1996 Jul 12 File under Integrated Circuits, IC17 1997 Jan 17 Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M FEATURES GENERAL DESCRIPTION • Power Amplifier (PA) overall efficiency 40% The CGY2030M is a GaAs Monolithic Microwave Integrated Circuit (MMIC) power amplifier specifically designed to operate at 3.6 V battery supply. When power control is not required, it can be operated without negative supply voltage. • 27 dB gain • 0 dBm input power • Operation possible without negative supply • Wide operating temperature range −30 to +85 °C • SSOP16 package. APPLICATIONS • 1.88 to 1.9 GHz transceivers for DECT applications • 2 GHz transceivers (PHS, DCS). QUICK REFERENCE DATA PARAMETER (1) SYMBOL MIN. TYP. MAX. UNIT VDD positive supply voltage − 3.2 − V IDD positive peak supply current − 400 − mA Po output power − 27 − dBm Tamb operating ambient temperature −30 − +85 °C Note 1. For conditions, see Chapters “AC characteristics” and “DC characteristics”. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME CGY2030M SSOP16 DESCRIPTION VERSION plastic shrink small outline package; 16 leads; body width 4.4 mm BLOCK DIAGRAM handbook, full pagewidth VDD1 VDD2 8 5 VDD3 13 CGY2030M RFI 9 16 2, 3, 4, 6, 7, 11, 12, 14, 15 10 VGG1 1 VGG2 Fig.1 Block diagram. 1997 Jan 17 2 RFO/VDD4 MBG631 SOT369-1 Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M PINNING SYMBOL PIN DESCRIPTION VGG2 1 GND 2 to 4 VDD2 5 GND 6 and 7 VDD1 8 first stage supply voltage RFI 9 PA input VGG1 10 first second and third stages negative gate supply voltage GND VDD3 GND RFO/VDD4 fourth stage negative gate supply voltage handbook, halfpage VGG2 1 16 RFO/VDD4 ground GND 2 15 GND second stage supply voltage GND 3 14 GND ground GND 4 CGY2030M 11 and 12 ground 13 third stage supply voltage 13 VDD3 VDD2 5 12 GND GND 6 11 GND GND 7 10 VGG1 VDD1 8 9 RFI MBG630 14 and 15 ground 16 PA output and fourth stage supply voltage Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION MODE 1 Amplifier In the first mode, the pins VGG1 and VGG2 are simply connected together to the ground via resistors (10 kΩ in the evaluation board; see Fig.4). The amplifier biases itself internally to a negative voltage by action of the incoming RF signal. In this mode, power control cannot be achieved by varying the amplifier supply voltage; therefore it is suitable only for applications where power control is not required such as DECT. The CGY2030M is a 4-stage GaAs MESFET power amplifier capable of delivering 500 mW (typ.) at 1.9 GHz into a 50 Ω load. Each amplifier stage has an open-drain configuration. The drains have to be loaded externally by adequate reactive circuits which must also provide a DC path to the supply. The amplifier can be switched off by means of an external PNP series switch connected between the battery and the amplifier drains. This switch can also be used to vary the actual supply voltage applied to the amplifier and hence, control the output power. MODE 2 If a negative bias is available, a second mode of operation is possible, in which the amplifier is biased by providing adequate negative voltages at pins VGG1 and VGG2. In this mode, the amplifier internal bias does not depend on the incoming RF level, nor on the drain voltage, so that power control is possible by variation of the supply voltage. This device is specifically designed to work with a maximum duty factor of 25%. Biasing Two modes of operation are possible: • Mode 1 • Mode 2. 1997 Jan 17 3 Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT − − 5.2 V − − 8 V maximum operating junction temperature − − 150 °C Ptot total power dissipation − − 400 mW Tstg IC storage temperature −55 − +125 °C VDD operating supply voltage VDD − VGG voltage difference between supply voltage and gate bias voltage Tj(max) no input signal THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE UNIT 145 K/W HANDLING Do not operate or store near strong electrostatic fields. Meets class 1 ESD test requirements [Human Body Model (HBM)], in accordance with “MIL STD 883C - method 3015”. DC CHARACTERISTICS VDD = 3.2 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Pins RFO/VDD4, VDD3, VDD2 and VDD1 VDD positive supply voltage 2.6 3.2 4.2 V IDD positive peak supply current − 400 500 mA note 1 − −1.2 − V Pins VGG1 and VGG2; in mode 2 VGG1 bias voltage for input stages VGG2 bias voltage for output stage note 1 − −2.0 − V IGG(tot) total gate peak current note 2 −1 − +1 mA Notes 1. Negative voltages VGG1 and VGG2 must be applied before supply voltage VDD. 2. Due to non linear effects at high power levels, the gate current can be either negative or positive. 1997 Jan 17 4 Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M AC CHARACTERISTICS VDD = 3.2 V; fRF = 1900 MHz; Pi = 0 dBm; Tamb = 25 °C; duty factor δ = 25%; 50 Ω impedance system; measured and guaranteed on CGY2030M evaluation board (see Fig.4). SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT −3 − +5 duty factor − − 25 % operating frequency − 1900 − MHz 28.5 dBm Pi input power δ fRF note 1 dBm Measured in mode 1; without negative biasing; VGG1 and VGG2 connected to ground Po output power 26 η efficiency Pleak RF leakage to output in power off state H2, H3 second and third harmonics level Stab stability (spurious levels) VDD = 0 V note 2 27 − 40 − % − −40 − dBm − −35 − dBc − −60 − dBc Measured in mode 2; with negative biasing at pins VGG1 and VGG2 Po output power 25.5 26.5 28 dBm η efficiency − 35 − % Pleak RF leakage to output in power off state − −50 − dBm VDD = 0 V Notes 1. Self biasing guaranteed in mode 1 at minimum input power (−3 dBm) and minimum supply voltage VDD (2.6 V). 2. The device is adjusted to provide nominal value of load power into a 50 Ω load. The device is switched off and a 6 : 1 load replaces the 50 Ω load. The device is switched on and the phase of the 6 : 1 load is varied 360 electrical degrees during a 60 seconds test period. MGG165 32 handbook, halfpage Po (dBm) 650 IDD (mA) Po 28 550 24 450 IDD 20 350 2 3 4 VDD (V) 5 Fig.3 Typical power and current characteristics in mode 1. 1997 Jan 17 5 Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M By switching on the last amplifier stages with some delay compared to the first stages, it is possible to get the last stages already self-biased before their supply voltage has reached its steady state value. This enables smooth power up-ramping without any power overshoot. A simpler drain switching circuit can be used if the amplifier is operated with negative biasing of the pins VGG1 and VGG2. APPLICATION INFORMATION The CGY2030M is operated and tested in accordance with the circuit diagram shown in Fig.4. Supply voltage switching is achieved by two bipolar PNP transistors. One transistor switches the first and second stages and the other switches the third and fourth stages. Vbat handbook, full pagewidth 10 nF 3.3 Ω 68 pF 100 µF DTC11YE BC858 330 Ω 10 pF 1Ω ramp 22 pF 6.8 pF TRL1(1) VDD1 GND 8 7 VGG2 TRL2(2) VDD2 GND GND 6 10 kΩ 5 4 VGG2 GND GND 3 2 1 14 15 16 CGY2030M 9 10 RFI Zc = 50 Ω 11 VGG1 GND 12 13 GND VDD3 GND GND RFO/ VDD4 PA input TRL4(4) 10 pF Zc = 50 Ω 1.5 pF PA output 10 kΩ 1.8 pF VGG1 TRL5(5) TRL3(3) 100 Ω BC807 100 nF 6.8 pF MGG166 Thickness: 0.8 mm; substrate: FR4; εr = 4.7. (1) TRL1: width = 500 µm; length = 11200 µm. (2) TRL2: width = 500 µm; length = 7770 µm. (3) TRL3: width = 300 µm; length = 15450 µm. (4) TRL4: width = 1600 µm; length = 12000 µm. (5) TRL5: width = 1600 µm; length = 11000 µm. Fig.4 Evaluation board schematic. 1997 Jan 17 6 Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 94-04-20 95-02-04 SOT369-1 1997 Jan 17 EUROPEAN PROJECTION 7 o Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1997 Jan 17 8 Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Jan 17 9 Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M NOTES 1997 Jan 17 10 Philips Semiconductors Product specification DECT 500 mW power amplifier CGY2030M NOTES 1997 Jan 17 11 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 437027/1200/03/pp12 Date of release: 1997 Jan 17 Document order number: 9397 750 01565