Data Sheet No. PD60367 IR3710MTRPBF WIDE INPUT AND OUTPUT, SYNCHRONOUS BUCK REGULATOR DESCRIPTION FEATURES The IR3710 is a single-phase sync-buck PWM controller optimized for efficiency in high performance portable electronics. The switching modulator uses constant on-time control. Constant on-time with diode emulation provides the highest light-load efficiency required for all. Input Voltage Range: 3V to 28V Output Voltage Range: 0.5V to 12V Constant On-Time control Excellent Efficiency at very low output current levels Gate drive charge pump option to maximize efficiency at higher output current levels Compensation Loop not Required Programmable switching frequency, soft start, and over current protection Power Good Output Precision Voltage Reference (0.5V, +/-1%) Enable Input with Voltage Monitoring Capability Pre-bias Start Up Under/Over Voltage Fault Protection 16pin 3x3 MLPQ lead free package RoHS compliant Programmable switching frequency, soft start, and over current protection allows for a very flexible solution suitable for many different applications. The combination of the gate drive charge pump option and constant on time control allow efficiency optimization in the whole output current range, making this device an ideal choice for battery powered applications. Additional features include pre-bias startup, very precise 0.5V reference, over/under voltage shut down, power good output, and enable input with voltage monitoring capability. APPLICATION CIRCUIT Enhanced Gate Drive Application Circuit: V5 D2 DBOOT VIN D1 RFF C1 V3.3 CPO PVCC FF BOOT 6.2k 10k EN L UGATE VCC VOUT CBOOT IR3710 PHASE COUT FCCM PGOOD LGATE PGND ISET RISET SS GND R1 FB R2 CSS ORDERING INFORMATION Package Description IR3710MTRPbF Page 1 of 20 Pin Count 16 www.irf.com Parts Per Reel 4000 IR Confidential 4/26/10 IR3710MTRPBF Fix Gate Voltage Application Circuit: V5 DBOOT VIN NC V3.3 RFF CPO PVCC FF BOOT 6.2k L UGATE VCC 10k IR3710 EN VOUT CBOOT PHASE COUT FCCM PGOOD LGATE RISET SS R1 PGND ISET FB GND R2 CSS 3.3V Input Voltage Application Circuit: V3.3 DBOOT NC 6.2k RFF CPO PVCC FF 10k BOOT EN L UGATE VCC VOUT CBOOT IR3710 PHASE COUT FCCM PGOOD LGATE PGND ISET RISET SS GND FB R2 CSS Page 2 of 20 www.irf.com R1 IR Confidential 4/26/10 IR3710MTRPBF ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings (Referenced to GND) BOOT Voltage: ................................................40 V PHASE Voltage:....-5V(100ns),-0.3V(DC) to 32.5 V FF, ISET:..........................................................32 V BOOT minus PHASE Voltage:........................7.5 V PVCC: ............................................................7.5 V VCC:................................................................3.9 V PGOOD:..........................................................3.9 V PGND to GND:................................... -0.3V to 0.3V All other pins ...................................................3.9 V Operating Junction Temperature .. -10°C to +150oC Storage Temperature Range .......... -65oC to 150oC ESD Rating ...............................................Class 1C MSL Rating ..................................................Level 2 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. RECOMMENDED OPERATING CONDITIONS Symbol Definition VIN Input Voltage BOOT to PHASE Supply Voltage VOUT Output Voltage Fs Switching Frequency Min Max Units 3 28* 12 V V V 1000 kHz 7.0 0.5 * Note: PHASE pin must not exceed 32.5V. ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply: VCC = 3.3V, PVCC = 7.0V, 0oC ≤ TJ ≤ 125oC PARAMETER BIAS SUPPLIES VCC Turn-on Threshold VCC Turn-off Threshold VCC Threshold Hysterisis PVCC Turn-on Threshold PVCC Turn-off Threshold PVCC Threshold Hysterisis VCC Shutdown Current VCC Operating Current PVCC Shutdown Current FF Shutdown Current CONTROL LOOP Reference Accuracy, VREF On-Time Accuracy Zero Current Threshold Soft-Start Current Page 3 of 20 NOTE TEST CONDITION MIN TYP MAX UNIT 3 V V mV V V mV 2.65 60 3.05 2.65 60 25 1.2 20 2 EN=LOW EN=HIGH, No gate loading EN=LOW; PVCC = 5V EN=LOW VFB = 0.5V RFF = 180K, VIN = 12.6V Measure at VPHASE FCCM = EN = HIGH www.irf.com IR Confidential 0.495 270 -4.5 8 0.5 300 10 μA mA μA μA 0.505 330 4.5 12 V ns mV μA 4/26/10 IR3710MTRPBF PARAMETER FAULT PROTECTION ISET pin output current Under Voltage Threshold Under Voltage Hysteresis Over Voltage Threshold PGOOD Delay Threshold (VSS) GATE DRIVE UGATE Source Resistance UGATE Sink Resistance UGATE Rise and Fall Time LGATE Source Resistance LGATE Sink Resistance LGATE Rise Time LGATE Fall Time Dead time NOTE TEST CONDITION Falling VFB & monitor PGOOD Rising VFB Rising VFB & monitor PGOOD 1 1 1 1 IGATE = 0.1A IGATE = 0.1A 3nF load; 1V & 4V thresholds IGATE = 0.1A IGATE = 0.1A 6.8nF load; 1V to 4V 6.8nF load; 4V to 1V Measure time from VLGATE = 1V to VUGATE = 1V Minimum LGATE Interval CHARGE PUMP OUTPUT Source Resistance ICPO =15mA Sink Resistance ICPO =15mA Charge Pump Disable FCCM = HIGH Threshold, VCP TH LOGIC INPUT AND OUTPUT EN Rising Threshold EN Hysterisis EN Input Current FCCM Rising Threshold FCCM Falling Threshold FCCM Hysterisis FCCM Input Current PGOOD pull down resistance IPGOOD =2mA NOTES: 1. Guaranteed by design, not tested in production Page 4 of 20 www.irf.com IR Confidential MIN TYP MAX UNIT 18 0.37 20 0.4 7.5 0.6 0.6 22 0.43 μA V mV V V 1.5 1 10 1.5 0.4 15 10 3 2 Ω Ω ns Ω Ω ns ns ns 5 3 1 50 400 ns 5 2.1 6.8 3.3 1 7.2 Ω Ω V 1.14 40 1.22 100 0.5 1 0.7 0.3 1.3 160 1 1.2 V mV μA V V 1 100 μA Ω 50 4/26/10 IR3710MTRPBF IC PIN ORDER AND DESCRIPTION I/O LEVEL VIN +PVCC VIN DESCRIPTION PGND LGATE 13 VIN + V5 14 Reference 3.3V 3.3V 3.3V 3.3V 3.3V 7.4V PVCC Reference VIN PHASE 3.3V 32V 3.3V 15 Bootstrapped gate drive supply – connect a capacitor to PHASE Input voltage feed forward – sets on-time with a resistor to VIN Enable input; EN = LOW inhibits GATE pulses Current limit setting with a resistor to PH pin Power good – pull up to 3.3V Bias return and signal reference Force continuous conduction mode when pulled up to VCC Feedback input Set soft start slew-rate with a capacitor to GND IC bias supply Charge Pump Output Gate drive supply Lower gate drive for synchronous MOSFET Power return – connect to source of synchronous MOSFET Phase node (or switching node) of MOSFET half bridge Upper gate drive for control MOSFET 12 PVCC 11 CPO 3 10 VCC 4 9 BOOT 1 FF 2 EN ISET PGOOD 8 7 GND 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UGATE NUMBER 16 BOOT FF EN ISET PGOOD GND FCCM FB SS VCC CPO PVCC LGATE PGND PHASE UGATE 5 NAME SS GND FCCM FB θJA = 49 oC/W θJC = 4 oC/W Page 5 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF BLOCK DIAGRAM PVCC FF PVCC VCC FCCM FF VCC FCCM VCC Charge Pump Regulator CPO PGND SS ZCROSS PWM COMP + + - Run SET PWM ON-TIME BOOT + OV - FB + x0.8 - UV# UGATE GATE DRIVE LOGIC PHASE PVCC Run VCC LGATE VREF GND x1.2 SOFT START FF EN Run SSDelay CONTROL LOGIC PGND POR ZCROSS OC# DCM PVCC OVER CURRENT PGOOD Page 6 of 20 www.irf.com IR Confidential ISET 4/26/10 IR3710MTRPBF TYPICAL OPERATING DATA (Circuit of Figure 18, VCC = 3.3V, V5 = 5V, VIN = 12.6V, Unless otherwise noted.) 19Vin 1000000 12Vin Ploss-19Vin Ploss-12Vin Rff ( 0.5 , fsw ) Feedforward Resistance (KΩ) Rff ( 1.5 , fsw ) Rff ( 2 , fsw ) Rff ( 2.5 , fsw ) Efficiency (% Feedforward Resistance Rff ( 1 , fsw ) VOUT = 5V Rff ( 3 , fsw ) Rff ( 3.5 , fsw ) Rff ( 4 , fsw ) Rff ( 4.5 , fsw ) Rff ( 5 , fsw ) 90 6.0 88 5.0 86 4.0 84 3.0 82 2.0 80 1.0 78 VOUT = 0.5V 0200000 76 000000 200 fsw Switching Frequency Power Loss (W) 1000 0.0 1000000 0 1000 2 4 6 8 Switching Frequency (KHz) 10 12 14 16 18 20 22 24 Output Current(A) Figure 1. Feedforward Resistance vs Switching Freq: 0.5V VOUT step, FCCM = HIGH. Figure 4. System Efficiency Fs =300kHz; Ccpo=1uF Fs=1.34MHz ;Ccpo=1uF Freq vs Load 7.4 7.2 300 7 250 PVCC (V) 200 150 6.8 6.6 100 6.4 50 6.2 0 0 2 4 6 8 10 12 14 16 18 20 22 6 24 0 5 10 15 12Vin@65C 19Vin@0C 19Vin@65C 1.10150 90 1.10100 88 30 35 40 45 5V Drive Enhanced Gate Ploss-5V Drive Ploss-Enhanced Gate 5.0 4.5 Efficiency (% 1.10050 Vout(V) 25 Figure 5. Charge Pump Regulation Figure 2. Switching Frequency vs Output Current 12Vin@0C 20 Gate Charge (nC) Output Current (A) 1.10000 1.09950 1.09900 4.0 3.5 86 3.0 2.5 84 2.0 82 1.09850 80 1.09800 78 Power Loss (W) Switching Frequency (KHz 350 1.5 1.0 0.5 0 2 4 6 8 Figure 3. Output Voltage Regulation versus Input Voltage and Ambient Temperature www.irf.com 2 4 6 8 10 12 Output Current(A) Output Current(A) Page 7 of 20 0.0 0 10 12 14 16 18 20 22 24 Figure 6. Charge Pump Efficiency Comparison: 1.25Vout, 12.6Vin, 300kHz, IRF8721/8721, 0.82uH (4.2mOhm DCR) IR Confidential 4/26/10 IR3710MTRPBF TYPICAL OPERATING WAVEFORM (Circuit of Figure 18, VCC = 3.3V, V5 = 5V, VIN = 12.6V, Unless otherwise noted.) CH1:Vout(20mV/div), CH2: PHASE (5V/div) CH1:Vout(0.5V/div), CH2: PHASE (20V/div) CH4: CPO(2V/div) ; 5uS/div CH3: PGOOD(5V/div), CH4:EN(5V/div) ; 50uS/div Figure 10. Charge Pump ON Figure 7. Start up with FCCM = Low @ 30mA CH1:Vout(0.5V/div), CH2: PHASE (20V/div) CH3: PGOOD(5V/div), CH4:EN(5V/div) ; 50uS/div Figure 8. Start up with Prebias Vout, FCCM = Low @ 30mA CH1:Vout(20mV/div), CH2: PHASE (5V/div) CH1:Vout(20mV/div), CH2: PHASE (5V/div), CH4: CPO(2V/div) ; 100uS/div CH4: FCCM(5V/div) ; 100uS/div Figure 11. DCM/FCCM Transition Figure 9. Charge Pump Off in DCM Page 8 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF CH2:Vout(20mV/div), CH3: Input Current (10A/div), CH4: Input Voltage (5V/div) 8V to 19V; 100uS/div CH1:Vout(50mV/div), CH2: PHASE (5V/div);50uS/div Figure 12. Frequency Variation less than 10% at 20A Load CH1:Vout(50mV/div), CH3: Inductor Current (10A/div), CH4: On-Board Load: 0A-14A ;50uS/div Figure 15. Input Voltage Step at 2A Load with 0.1V/uS CH1:Vout(0.5V/div), CH2: PHASE (10V/div), CH3: FB (0.5V/div), CH4: PGOOD (5V/div); 500uS/div Figure 16. Over Current Protection at 30A Figure 13. Load Step Transient in CCM @ Vin = 19V CH1:Vout(50mV/div), CH3: Inductor Current (10A/div), CH4: On-Board Load: 0.1A-12A; 50uS/div CH1:Vout(0.5V/div), CH2: PHASE (10V/div), CH3: EN (5V/div), CH4: PGOOD (2V/div); 200uS/div Figure 17. Shutdown by EN in DCM @500mA Figure 14. Load Step Transient in DCM @ Vin = 19V Page 9 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF TYPICAL OPERATING CIRCUIT V5 BAT54S VIN D2 BAT54T D1 180K CPO V3.3 PVCC FF 1uF BOOT EN IRF6721 L UGATE VCC 0.1uF IR3710 PHASE FCCM PGOOD LGATE PGND ISET 5.11K 56pF 2x10uF SS GND 0.5uH (0.82mOhm) IRF6635 Vout = 1.1V 2x330uF (9mOHM) 1.96K FB 1.65K 2.2nF Figure 18. Typical Application Circuit for 24A Load Page 10 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF The PWM comparator initiates a SET signal (PWM pulse) when the FB pin falls below lower of the reference (VREF) or soft start (SS) voltage. An adaptive dead time prevents the simultaneous conduction of the upper and lower MOSFETs. The lower gate voltage must be below approximately 1V after PWM goes HIGH before the upper MOSFET can be gated on. Also the upper gate voltage, the difference voltage between UGATE and PHASE, must be below approximately 1V after PWM goes LOW and before the lower MOSFET can be gated on. The PWM on-time duration is programmed with an external resistor (RFF) from the input supply (VIN) to the FF pin. The simplified equation for RFF is shown in the equation 1. The FF pin is held to an internal reference after EN goes HIGH. A copy of the current in RFF charges a timing capacitor, which set the ontime duration, as shown in equation 2. VOUT RFF = (1) 1V ⋅ 20 pF ⋅ FSW Diode emulation is enabled after PGOOD = HIGH when FCCM is LOW. The control MOSFET is gated on after the adaptive delay for PWM = HIGH and the synchronous MOSFET is gated on after the adaptive delay for PWM = LOW. The lower MOSFET is driven ‘off’ when the signal ZCROSS indicates that the inductor current reverses as detected by the PHASE voltage crossing the zero current threshold. The synchronous MOSFET stays ‘off’ until the next PWM falling edge. FUNCTIONAL DESCRIPTION Refer to Block Diagram ON-TIME GENERATOR TON = When FCCM = HIGH, forced continuous current condition is selected. The control MOSFET is gated on after the adaptive delay for PWM = HIGH and the synchronous MOSFET is gated on after the adaptive delay for PWM = LOW. RFF ⋅ 1V ⋅ 20 pF (2) VIN SOFT START An internal 10uA current source charges external capacitor on the SS pin to set the output voltage slew rate during the soft start interval. The output voltage reaches regulation when the FB pin is above the under voltage threshold and the UV# = HIGH. Once the voltage on the SS pin is above the PGOOD delay threshold, the combination of the SSDelay and UV# signals release the PGOOD pin. With EN = LOW, the capacitor voltage and SS pin is held to the FB pin voltage. OVER CURRENT MONITOR IR3710 monitors the output current every switching cycle. The voltage across the synchronous MOSFET, VPHASE is monitored for over current and zero crossing. The minimum LGATE interval allows time to sample VPHASE. The over current trip point is programmed with a resistor from ISET to PHASE pins, as shown in equation 3. When over current is detected, output gates are tri-state and SS voltage is pulled to 0V. A new soft start cycle begins right after. If there is three (3) consecutive OC events, IR3710 will disable switching. Toggling VCC or EN will allow next start up. RSET = RDSON ⋅ IOC 20 μA The synchronous MOSFET gate is driven on for a minimum duration. This minimum duration allows time to recharge the bootstrap capacitor and allows the current monitor to sample the phase voltage. CONTROL LOGIC The control logic monitors input power sources for supply voltage conditions, sequences the converter through the soft-start and protective modes, and indicates output voltage status on the PGOOD pin. VCC and PVCC pins are continuously monitored. IR3710 is disabled if either of these voltages drops below falling thresholds. IR3710 will initiate a soft start when the VCC and PVCC are in the normal range and the EN pin = HIGH. In the event of a sustained overload, a counter keep track of 4 consecutive soft-start cycles and disables IR3710. If the overload is momentary and output voltage is within regulation before 4 consecutive soft-start cycles, PGOOD transitions HIGH to reset the counter. OVER VOLTAGE PROTECTION IR3710 monitors the voltage at FB node. If the FB voltage is above the threshold of over voltage, the gates are turn off and pulls PGOOD signal low. Toggling VCC or EN will allow next start up. (3) GATE DRIVE LOGIC The gate drive logic features adaptive dead time, diode emulation, and a minimum lower gate interval. Page 11 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF CHARGE PUMP WON = The purpose of the charge pump is to improve the system efficiency. A combination of VCC, V5 and three(3) external components are used to boost PVCC up to VCP TH. PVCC drives the synchronous MOSFET and reduces the RDSON when compared to a regular 5V rail driver. The lower RDSON reduces the conduction power loss as discussed in the Power Loss section. The charge pump is continuously enabled for FCCM = HIGH. The charge pump circuit is disabled when FCCM = LOW and the output loading is less than half of inductor current ripple. In this case, PVCC is two (2) diode voltage away from V5 rail. Therefore, the power loss for driver is reduced. The charge pump circuit stops switching the CPO pin for PVCC above VCP TH. It is not recommended to use PVCC for supply power to boot capacitor when use charge pump circuit. This can be exceeding the maximum rating of BOOT to PHASE pins and damages to the IC. VIN ⋅ IPK (t3 - t1) (4) 2 PSW = WON ⋅ FS = VIN ⋅ IPK ⋅ 2 QGS2 + QGD ⋅ FS (5) IGDr Fs is the switching frequency. IGDr is gate driver current. To find the driver current, Figure 20 shows the simplified circuit of driver and MOSFET. IGdr can be found by using Ohm’s law as shown in the equation 6 with an assumption that VQgd is the gate voltage during t2 and t3. Therefore, the turn on switching power loss of a cycle can be easily be found as shown in equation 7. IPK VIN IOUT IGdr VGS POWER UP SEQUENCE With EN pin HIGH, IR3710 initiates a soft start when the VCC and PVCC are in the above ULVO threshold and VIN is in normal range. The order of VCC, PVCC and VIN is not require. VGS(th) QGS2 QGS1 QGD t2 t1 COMPONENT SELECTION t t3 Figure 19. Typical Turn-On Waveform. Selection of components for the converter is an iterative process which involves meeting the specifications and trade-offs between the performance and cost. The following sections will guide one through the process. VDR MOSFET Driver Power Loss The main sources contributing to the power loss of a converter are switching loss of the upper MOSFETs, conduction loss of the lower MOSFETs, AC and DC losses in the inductor, and driving loss which is a large factor at light load condition. In small duty cycle converter system, switching loss is main power loss of upper MOSFETs because its on-time is relatively small. To find the switching power loss, Figure 19 shows the typical turn-on waveform of the upper MOSFETs. Turn-off is quantitatively similar with x-axis reversed. The switching loss can be estimate as the cross sectional area in the figure. Equation 4 and 5 show the relationship of MOSFET’s switching charge and loss. RPU REXT RPD CGD RG VQgd CDS CGS Figure 20. Simplify Driver and MOSFET Circuit. VDR - VQgd (6a) RPU + REXT + RG VQgd (6b) IGDr(off - time) = RPD + REXT + RG VIN ⋅ IPK QGS2 + QGD PSW = ⋅ ⋅ FS (7) 2 IGDr(on - time) IGDr(on - time) = The reverse recovery power loss of the lower MOSFETs is also a factor of the upper MOSFET’s Page 12 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF switching power loss because the output current flow through the lower MOSFET’s body diode during the dead time stores some minority charges. When the upper MOSFETs turn on, it has to carry this extra current to remove the minority charges. The reverse recovery power loss can be found in equation 8. PQrr = Qrr ⋅ VIN ⋅ FS (8) By combining the PSW and PQrr, the total switching power loss of the upper MOSFETs is much greater than its conduction loss. International Rectifier MOSFET datasheets has separated the gate charge of QGS1 and QGS2 so that the designer can calculate the switching power loss. Therefore, selection of the upper MOSFETs should consider those factors. Otherwise, the converter losses degrade the system efficiency and may exceed the thermal constraints. The main power loss of lower MOSFETs is the conduction loss because its on-time is in the range of 90% of the switching period. The switching power loss of lower MOSFETs can be negligible because their body diode voltage drops are in the range of 1V. Equation 9 shows the conduction power loss calculation. TS is inversely proportional to fs, and TOFF is the on-time of the lower MOSFETs. RDS(on) increases approximately 30% with temperature. PCOND = IRMS_COND 2 ⋅ RDSON ⋅ TOFF Ts 1 ⎛ ΔI ⎞ ⋅⎜ ⎟ 3 ⎝ IOUT ⎠ 2 The driver power loss is a small factor when heavily loaded but it can be significant contributor of degradation to the converter efficiency in light load. Equation 10 shows the driver power loss relating to the total gate charge of upper and lower MOSFETs and switching frequency. 1 PCOND = Ts ΔI = VOUT VOUT ⋅ (VIN − VOUT ) ⋅ (1 − D) ⋅ Ts = (12) L VIN ⋅ L ⋅ Fs One can use equation 12 to find the inductance. The main advantage of small inductance is increased inductor current slew rate during a load transient, which leads to small output capacitance requirement as discussed in the Output Capacitor Selection section. The draw back of using smaller inductances is increased switching power loss in upper MOSFETs, which reduces the system efficiency and increases the thermal dissipation as discussed in the Power Loss section. Input Capacitor Selection (9) Where : IRMS_COND = IOUT ⋅ 1- D ⋅ 1 + Inductor selection involves meeting the steady state output ripple requirement, minimizing the switching loss of upper MOSFETs, transient response and minimizing the output capacitance. The output voltage includes a DC voltage and a small AC ripple component due to the low pass filter which has incomplete attenuation of the switching harmonics. Neglecting the inductance in series with output capacitor, the magnitude of the AC voltage ripple is determined by the total inductor ripple current flow through the total equivalent series resistance (ESR) of the output capacitor bank. Ts ∫ VDR ⋅ IGDr ⋅ dt = VDR ⋅ QGTotal ⋅ FS (10) 0 The main function of the input capacitor bank is to provide the input ripple current and fast slew rate current during the load current step up. The input capacitor bank must have adequate to handle the total RMS current. Figure 21 shows a typical input current. Equation 13 shows the RMS input current. The RMS input current contains the DC load current and the inductor ripple current. As shown in equation 12, inductor ripple current is unrelated to the load current. The maximum RMS input current occurs at the maximum output current. The maximum power dissipate in the input capacitor equals the square of the maximum RMS input current times the input capacitor’s total ESR. The low frequency and core losses are main factors of the total power loss of an inductor. Low frequency loss of an inductor is caused by the resistance of copper winding. The copper loss of the winding is shown in equation 11. The core loss of an inductor depends on the B-H loop characteristic, volume and frequency. This data can be obtained from the inductor manufactures. Figure 21. Typical Input Current Waveform. PDCR = IRMS 2 ⋅ DCR (11) 2 1 ΔI ⎞ Where : IRMS = IOUT ⋅ 1+ ⋅⎛⎜ ⎟ 3 ⎝ IOUT ⎠ IIN_RMS = Inductor Selection Page 13 of 20 www.irf.com IR Confidential 1 ⋅ Ts Ts ∫ 0 f 2 (t ) ⋅ dt = IOUT ⋅ D ⋅ 1 + 2 1 ⎛ ΔI ⎞ ⋅⎜ ⎟ (13) 3 ⎝ IOUT ⎠ 4/26/10 IR3710MTRPBF The voltage rating of the input capacitor needs to be greater than the maximum input voltage because of the high frequency ringing at the phase node. The typical percentage is 25%. Output Capacitor Selection Select the output capacitor involves meeting the overshoot requirement during the load removal, transient response when the system is demanding the current and meeting the output ripple voltage requirement. The output capacitor has the higher cost in the converter and increases the overall system cost. The output capacitor decoupling in the converter typically includes the low frequency capacitor, such as Specialty Polymer Aluminum, and mid frequency ceramic capacitors. The first purpose of output capacitors is to provide the different energy when the load demands the current until the inductor current reaches the load’s current as shown in figure 22. Equation 14 shows the charge requirement for certain load. The advantage of IR3710 at the load step is to reduce the delay, Tdmax, down to logic delay (in nanosecond) compare to fix frequency control method in microsecond or (1-D)*Ts. If the load increases right after the PWM signal low, the longest delay of Tdmax will be equal to the minimum lower gate on as shown in Electrical Specification table. IR3710 also reduces the total inductor time, which takes to reach output current, by increasing the switching frequency up to 2.5MHz. The result reduces the recovery time. requires a total ESR such that the ripple voltage at the FB pin is 7mV. The second purpose of the output capacitor is to minimize the overshoot of the output voltage when the load decreases as shown in Figure 23. By using the law of energy before and after the load removal, equation 15 shows the output capacitance requirement for a load step. COUT2 = L ⋅ ISTEP2 VOS2 − VOUT2 (15) Figure 23. Typical Output Voltage Response Vaveform. Boot Capacitor Selection The boot capacitor starts the cycle fully charged to a voltage of VB(0). An equivalent gate drive capacitance is calculated by consulting the high side MOSFET data sheet and taking the ratio of total gate charge at the V5 voltage, QG(V5), to the V5 voltage. QG(V5)/V5 is the equivalent gate drive capacitance Cg which will be used in the following calculations. The voltage of the capacitor pair CB and Cg after Cg becomes charged at CB’s expense will be VB(0)-ΔV. Choose a sufficiently small ΔV such that VB(0)-ΔV exceeds the maximum gate threshold voltage to turn on the high side MOSFET. Since total charge QT is conserved, we can write the following equations. VB (0) ⋅ C B = Q T = V(t on ) ⋅ (C B + C g ) (16) Figure 22. Charge Requirement during Load Step Q = C ⋅ V = IOUT ⋅ Tdmax + 0.5 ⋅ IOUT ⋅ dt COUT1 = (14a) ⎡ (1 − D) + 1 ⋅ L ⋅ ΔIOUT 2 ⎤ (14b) ⎢ ΔIOUT ⋅ ⎥ VDROP ⎢⎣ Fs 2 (VIN − VOUT ) ⎥⎦ 1 The output voltage drops, VDROP, initially depending on the characteristic of the output capacitor. VDROP is the sum of equivalent series inductance (ESL) of output capacitor times the rate of change output current and ESR times the change of output current. VESR is usually much greater than VESL. IR3710 Page 14 of 20 www.irf.com ⎛ V (0) ⎞ − 1⎟⎟ C B = C g ⋅ ⎜⎜ B ⎝ ΔV ⎠ Choose a boot capacitor value larger than the calculated CB. The voltage rating of this part needs to be larger than VB(0) plus the desired derating voltage. The voltage between BOOT and PHASE pins must not exceed the maximum rating of IR3710. Its ESR and ESL needs to be low in order to allow it to deliver the large current and di/dt’s which drive MOSFETs most efficiently. In support of these requirements a ceramic capacitor should be chosen. IR Confidential 4/26/10 IR3710MTRPBF DESIGN EXAMPLE ΔI = Design Criteria: Input Voltage, VIN, = 6V to 21V Output Voltage, VOUT = 1.1V Switching Frequency, FS = 300KHz Inductor Ripple Current, ΔI = 5A Maximum Output Current, IOUT = 20A Over Current Trip, IOC = 30A Overshoot Allowance, VOS = VOUT + 150mV Undershoot Allowance, VDROP = 150mV Choose input capacitor: 2 1.1V 1 ⎛ 6.2 A ⎞ ⋅ 1+ ⋅ ⎜ ⎟ = 4.7 A 21V 3 ⎝ 20 A ⎠ A 10uF (ECJ3YB1E106M) from Panasonic manufacture has 6Arms at 300KHz. Due to the chemistry of multilayer ceramic capacitors, the capacitance varies over temperature and operating voltage both of AC and DC. Two (2) of 10uF are recommended. In practical solution, one (1) of 1uF is required along with 2x10uF. The purposes of 1uF are to suppress the switching noise and deliver a high frequency current. IIN_RMS = 20 A ⋅ Find RFF : RFF = 1.1V ⋅ (21V - 1.1V ) = 6.2 A 21V ⋅ 0.56uH ⋅ 300K Hz 1.1V = 183 KΩ 1V ⋅ 20 pF ⋅ 300KHz Pick 182KΩ for 1% standard resistor Choose output capacitor: Find RSET : To meet the undershoot specification, select a set of output capacitor which has an equivalent of 7.5mΩ (150mV/20A). To meet the overshoot specification, equation 15 will be use to calculate the minimum output capacitance. As a result, 516uF will be needed. Combine those two requirements, one can choose a set of output capacitor bank from manufactures such as SP-Cap (Specialty Polymer Capacitor) from Panasonic or POSCAP from Sanyo. Two (2) of 270uF (EEFUD0D271XR) from Panasonic are recommended. This capacitor has 12mΩ ESR which leaves margin for voltage drop of ESL during load step up. The typical ESL for this capacitor is around 2nH. RSET = 1.3 ⋅ 3mΩ ⋅ 30 A 20 μA = 5.85KΩ 1.3 factor is base on RDSON of lower MOSFET increase over the temperature. Therefore, pick 5.9K for 1% standard resistor. Find resistor divider for VOUT = 1.1V: VFB = R2 ⋅ VOUT = 0.5V R2 + R1 R2 = 8.45KΩ, R1 = 10KΩ for 1% standard resistor LAYOUT RECOMMENDATION Choose the soft start capacitor: Bypass Capacitor: One 1uF high quality ceramic capacitor is recommended to be placed as near VCC pin as possible. Other end of capacitor can be via or directly connect to GND plane. Use a GND plane not a thin trace to GND pin because this thin trace has higher impedance compare to GND plane. A 1uF is recommended for both V5 and PVCC and repeat the layout procedure above for those signals. Charge Pump: It is recommended to place D1, D2 and C2 as close to the CPO and PVCC pins as possible. If those components can not placed on the same layer as IR3710, a minimum of two (2) vias need for the connection of C2 and CPO pin and the connection of D2 and PVCC. Boot Circuit: CBOOT needs to place near BOOT and PHASE pins to reduce the impedance during the turn on of the upper MOSFET. DBOOT does not need to be close to CBOOT because the average current to charge CBOOT is small during the on time of lower MOSFET. Once the soft start time has chosen such as 100uS to reach to the reference voltage, a 2.2nF for CSS is used to meet 100uS. Choose inductor to meet design specification: L= VOUT ⋅ (VIN − VOUT ) 1.1V ⋅ (21V - 1.1V ) = = 0.7u H VIN ⋅ ΔI ⋅ Fs 21V ⋅ 5 A ⋅ 300KHz Choose the inductor with lowest DCR and AC power loss as possible to increase the overall system efficiency. For instance, choose FDUE1250-R56M from TOKO manufacture. The inductance of this part is 0.56uH and has 0.82mΩ DCR. The core loss for this inductor is 0.41W and 0.41W for DCR. Ripple current needs to recalculate with a chosen inductor. Page 15 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF Gate Impedance: We recommended placing LGATE signal path on top next to the source of low side MOSFET path and place UGATE signal path on top of PHASE signal path. If the connection of PGND pin to the source of low side MOSFET is through an internal layer, it is recommended connecting through at least 2 vias by build a small island of next to PGND pin. Power Stage: Figure 24 shows the flowing current path for on and off period. The on time path has low average DC current with high AC current. Therefore, it is recommended to place input ceramic capacitor, upper and lower MOSFET in a tight loop as shown in Figure 24. The purpose tight loop of input ceramic capacitor is to suppress the high frequency (10MHz range) switching noise to reduce Electromagnetic Interference (EMI). If this path has high inductance, the circuit will cause voltage spike and ringing, increase the switching loss. The off time path has low AC and high average DC current. Therefore, it is recommended to layout with tight loop and fat trace at two end of inductor. The higher resistance of this loop increases the power loss. The typical resistance value of 1 ounce copper thickness has one-half miliΩ per square. Page 16 of 20 www.irf.com IR Confidential Figure 24. Current Path of Power Stage 4/26/10 IR3710MTRPBF PCB PAD AND COMPONENT PLACEMENT Figure 25. Ssuggested pad and component placement. Page 17 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF SOLDER RESIST Figure 26. Suggested solder resist placement. Page 18 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF STENCIL DESIGN Figure 27. Suggested stencil design. Page 19 of 20 www.irf.com IR Confidential 4/26/10 IR3710MTRPBF PACKAGE INFORMATION Figure 28. Package Outline Drawing Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUATERS: 233 Kansas St, EL Segundo, California 90245, USA Tel: (310)-252-7105 TAC Fax: (310)-252-7903 Visit us at www.irf.com for sales contact information. www.irf.com Page 20 of 20 www.irf.com IR Confidential 4/26/10