INTEGRATED CIRCUITS DATA SHEET OM6206 65 × 102 pixels matrix LCD driver Product specification File under Integrated Circuits, IC17 2001 Nov 14 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 Pin functions R0 to R64: row driver outputs C0 to C101: column driver outputs VSS1 and VSS2: ground supply rails VDD1, VDD2 and VDD3: supply voltage rails VLCDIN: LCD supply voltage VLCDOUT: voltage multiplier output VLCDSENSE: voltage multiplier regulation input T1 to T5: test pins SDIN: serial data line SCLK: serial clock line D/C: mode select SCE: chip enable OSC: oscillator RES: reset 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.7.1 Oscillator Address counter Display data RAM (DDRAM) Timing generator Display address counter LCD row and column drivers Addressing Data structure 2001 Nov 14 2 8 INSTRUCTIONS 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.4.1 8.5 8.6 8.7 8.8 8.9 8.10 Initialization Reset function Function set PD V H Display control D and E Set Y-address of RAM Set X-address of RAM Set high-voltage generator stages Bias system Temperature control Set VOP value 9 LIMITING VALUES 10 HANDLING 11 DC CHARACTERISTICS 12 AC CHARACTERISTICS 13 APPLICATION INFORMATION 13.1 13.2 13.3 13.4 Programming example for the OM6206 Application diagrams Application for COG Chip information 14 BONDING PAD INFORMATION 15 DEVICE PROTECTION CIRCUITS 16 TRAY INFORMATION 17 DATA SHEET STATUS 18 DEFINITIONS 19 DISCLAIMERS Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 1 OM6206 • Low power consumption, suitable for battery operated systems FEATURES • Single-chip LCD controller and driver • Temperature compensation of VLCD • 65 row and 102 column outputs • Temperature range from −40 to +85 °C • Display data RAM 65 × 102 bits • Slim chip layout, suited for Chip-On-Glass (COG) applications. • On-chip: – Configurable 5 (4, 3 and 2) × voltage multiplier generating VLCD (external VLCD also possible) 2 – Generation of intermediate LCD bias voltages APPLICATIONS • Telecom equipment. – Oscillator requires no external components (external clock also possible). • External reset input pin RES 3 • Serial interface maximum 4.0 Mbits/s • Logic supply voltage range from 2.5 to 5.5 V (VDD1 to VSS) The OM6206 is a low-power CMOS LCD controller and driver, designed to drive a graphic display of 65 rows and 102 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. • High-voltage generator supply voltage range from 2.5 to 4.5 V (VDD2 and VDD3 to VSS) The OM6206 interfaces to microcontrollers via a serial bus interface. • CMOS compatible inputs • Multiplex rate of 1 : 65 GENERAL DESCRIPTION • Display supply voltage range from 4.5 to 9.0 V (VLCD to VSS) 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME OM6206U/Z 2001 Nov 14 − DESCRIPTION VERSION − chip with bumps in tray 3 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 5 OM6206 BLOCK DIAGRAM handbook, full pagewidth VSS1 VSS2 214 to 217, 221, 222 VDD1 200 to 213 VDD2 174 to 179 VDD3 181 to 193 R0 to R64 C0 to C101 180 37 to 138 2 to 15, 18 to 36, 139 to 156, 159 to 172 ROW DRIVERS COLUMN DRIVERS VLCDIN 224 to 229 BIAS VOLTAGE GENERATOR SHIFT REGISTER DATA LATCHES RESET VLCDSENSE VLCDOUT T1 T2 T3 T4 T5 237 230 to 236 HIGH VOLTAGE GENERATOR DISPLAY DATA RAM (DDRAM) 65 × 102 OSCILLATOR 199 TIMING GENERATOR 218 198 ADDRESS COUNTER 223 DISPLAY ADDRESS COUNTER 220 219 1 DATA REGISTER OM6206 I/O BUFFER 195 194 196 197 MGT859 SDIN SCLK D/C Fig.1 Block diagram. 2001 Nov 14 4 SCE RES OSC Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 6 OM6206 6.1.3 PINNING SYMBOL PAD 18 to 36 LCD row driver outputs R19 to R32 2 to 15 LCD row driver outputs R33 to R50 156 to 139 LCD row driver outputs R51 to R64 159 to 172 LCD row driver outputs C0 to C101 37 to 138 LCD column driver outputs VSS1 200 to 213 ground supply 2 VDD1 174 to 179 supply voltage 1 VDD2 181 to 193 supply voltage 2 VDD3 180 224 to 229 LCD supply voltage (VLCD) VLCDOUT 230 to 236 voltage multiplier output (VLCD) VLCDSENSE 237 voltage multiplier regulation input (VLCD) T1 218 test 1 input T2 198 test 2 output T3 223 test 3 input/output T4 220 test 4 input T5 219 test 5 input SCLK 194 serial clock input SDIN 195 serial data input D/C 196 data or command selection input SCE 197 chip enable (active LOW) OSC 199 oscillator signal input RES 1 VDD1, VDD2 AND VDD3: SUPPLY VOLTAGE RAILS VDD2 and VDD3 are the supply voltage for the internal voltage generator. Both have the same voltage and should be connected together outside the chip. VDD1 is used as supply voltage for the rest of the chip. VDD1 can be connected together with VDD2 and VDD3 but in this case care must be taken to respect the supply voltage range (see Chapter 11). If the internal voltage generator is not used the pins VDD2 and VDD3 must be connected to pin VDD1 or connected to the supply voltage. supply voltage 3 VLCDIN 6.1.1 6.1.4 214 to 217, ground supply 1 221 and 222 VSS2 6.1 The supply rails VSS1 and VSS2 must be connected together. DESCRIPTION R0 to R18 VSS1 AND VSS2: GROUND SUPPLY RAILS 6.1.5 VLCDIN: LCD SUPPLY VOLTAGE Positive supply voltage for the liquid crystal display. An external LCD supply voltage can be supplied using pin VLCDIN. In this case, VLCDOUT has to be left open and the internal voltage generator has to be programmed to zero. If the OM6206 is in Power-down mode, the external LCD supply voltage has to be switched off. 6.1.6 VLCDOUT: VOLTAGE MULTIPLIER OUTPUT Positive supply voltage for the liquid crystal display. If the internal voltage generator is used, the two supply rails VLCDIN and VLCDOUT must be connected together. If an external supply is used this pin must be left open. 6.1.7 VLCDSENSE: VOLTAGE MULTIPLIER REGULATION INPUT VLCDSENSE is the input of the internal voltage multiplier regulation. external reset input (active LOW) If the internal voltage generator is used then VLCDSENSE must be connected to VLCDOUT. If an external supply voltage is used then VLCDSENSE can be left open or connected to ground. Pin functions R0 TO R64: ROW DRIVER OUTPUTS These pins output the row signals. 6.1.8 6.1.2 C0 TO C101: COLUMN DRIVER OUTPUTS T1, T3, T4 and T5 must be connected to VSS, T2 must be left open. Not accessible to user. These pins output the column signals. 2001 Nov 14 T1 TO T5: TEST PINS 5 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 6.1.9 OM6206 7.2 SDIN: SERIAL DATA LINE The address counter assigns addresses to the display data RAM for writing. The X-address X6 to X0 and the Y-address Y3 to Y0 are set separately. After a write operation, the address counter is automatically incremented by 1 according to bit V (see Section 7.7). Input for the data line. 6.1.10 SCLK: SERIAL CLOCK LINE Input for the clock signal: up to 4.0 Mbits/s. 6.1.11 D/C: MODE SELECT 7.3 Input to select either command or address data input. 6.1.12 SCE: CHIP ENABLE OSC: OSCILLATOR When the on-chip oscillator is used this input must be connected to VDD. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting pin OSC to VSS, the display is not clocked and may be left in a DC state. To avoid this the chip should always be put into Power-down mode before stopping the clock. 6.1.14 7.4 7.1 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus. 7.5 Display address counter The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. RES: RESET This signal will reset the device and must be applied to properly initialize the chip. Signal is active LOW. 7 Display Data RAM (DDRAM) The OM6206 contains a 65 × 102 bits static RAM which stores the display data. The RAM is divided into eight banks of 102 bytes (8 × 8 × 102 bits) and one bank of 102 bits (1 × 102 bits). During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between X-address and column output number. The enable pin allows data to be clocked in. Signal is active LOW. 6.1.13 Address counter The display status (all dots on/off and normal/inverse video) is set by bits E and D in the command ‘Display control’ (see Table 2). FUNCTIONAL DESCRIPTION 7.6 Oscillator The OM6206 contains 65 rows and 102 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected. The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input. 2001 Nov 14 LCD row and column drivers 6 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 frame n + 1 frame n ROW0 R0(t) ROW1 R1(t) COL0 C0(t) COL1 C1(t) Vstate1(t) VLCD V2 V3 Vstate2 (t) V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V3 − VSS Vstate1(t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD − VLCD VLCD V3 − VSS Vstate2 (t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD − VLCD 0 1 2 3 4 5 6 7 8... ... 64 0 1 2 3 4 5 6 7 8... Vstate1(t) = C1(t) to R0(t). Vstate2(t) = C1(t) to R1(t). Fig.2 Typical LCD driver waveforms. 2001 Nov 14 7 ... 64 MGT860 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 DDRAM bank 0 top of LCD bank 1 bank 2 LCD bank 3 bank 7 bank 8 MGT861 Fig.3 DDRAM to display mapping. 2001 Nov 14 8 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 7.7 OM6206 Addressing After the last Y-address (Y = 8) Y wraps around to 0 and X increments to address the next column. Data is downloaded in bytes into the RAM matrix of OM6206 as indicated in Figs.3, 4, 5 and 6. In horizontal addressing mode (bit V = 0) the X-address increments after each byte (see Fig.5). After the last X-address (X = 101) X wraps around to 0 and Y increments to address the next row. The display RAM has a matrix of 65 × 102 bits. The columns are addressed by the address pointer. The address ranges are: X from 0 to 101 (1100101) and Y from 0 to 8 (1000). Addresses outside these ranges are not allowed. After the very last address (X = 101, Y = 8) the address pointers wrap around to address X = 0, Y = 0. In vertical addressing mode (bit V = 1) the Y-address increments after each byte (see Fig.6). 7.7.1 DATA STRUCTURE LSB handbook, full pagewidth 0 MSB Y-address LSB 8 0 X-address MSB MGT862 Fig.4 RAM format, addressing. 2001 Nov 14 101 9 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 handbook, full pagewidth 0 9 1 10 0 2 3 4 Y-address 5 6 7 8 917 0 X-address 101 8 MGT 863 Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1). handbook, full pagewidth 0 1 2 102 103 104 204 205 206 306 307 308 408 409 410 510 511 512 612 613 614 714 715 716 816 817 818 0 0 Y-address 917 X-address 101 8 MGT864 Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0). 8 INSTRUCTIONS Every instruction can be sent in any order to the OM6206. The MSB of a byte is transmitted first (see Fig.7). Figure 8 shows one possible command stream, used to set up the LCD driver. The instruction format is divided into two modes: • If D/C (mode select) is set LOW, the current byte is interpreted as command byte (see Table 1). The serial interface is initialized when SCE is HIGH. In this state SCLK clock pulses have no effect and no power is consumed by the serial interface. A negative edge on SCE enables the serial interface and indicates the start of a data transmission. • If D/C is set HIGH, the following bytes are stored in the display data RAM. After every data byte the address counter is incremented automatically. The level of the D/C signal is read during the last bit of data byte. 2001 Nov 14 10 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver MSB (DB7) handbook, halfpage OM6206 LSB (DB0) data data MGT865 Fig.7 General format of data stream. handbook, full pagewidth function set (H = 1) bias system set VOP temperature control function set (H = 0) display control Y-address X-address MGT866 Fig.8 Serial data stream, example. • If SCE stays LOW after the last bit of a command/data byte, the serial interface expects bit 7 of the next byte at the next positive edge of SCLK (see Fig.11) Figures 9 and 10 show the serial bus protocol: • When SCE is HIGH, SCLK clock signals are ignored. During the HIGH time of SCE, the serial interface is initialized (see Fig.11) • A reset pulse with RES interrupts the transmission. No data are written into the RAM. The registers are cleared. If SCE is LOW after the positive edge of RES, the serial interface is ready to receive bit 7 of a command/data byte (see Fig.11). • SDIN is sampled at the positive edge of SCLK • D/C indicates, whether the byte is a command (D/C = LOW) or RAM data (D/C = HIGH); it is read with the eighth SCLK pulse handbook, full pagewidth SCE D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGT867 Fig.9 Serial bus protocol for transmission of one byte. 2001 Nov 14 11 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 handbook, full pagewidth SCE D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 MGT868 Fig.10 Serial bus protocol for transmission of several bytes. handbook, full pagewidth SCE D/C RES SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 MGT869 Fig.11 Serial bus reset function (SCE). handbook, full pagewidth SCE RES D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 MGT870 Fig.12 Serial bus interrupt function (RES). 2001 Nov 14 12 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver Table 1 OM6206 Instruction set INSTRUCTION DESCRIPTION PIN COMMAND BYTE D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LOW LOW 0 0 0 0 0 1 0 0 0 0 0 PD 0 V 0 H (H = 0 or 1) NOP Function set Write data no operation power down control; entry mode; extended instruction set control (H) writes data to display RAM HIGH do not use sets display configuration VLCD programming range select LOW LOW LOW 0 0 0 0 0 0 0 0 0 0 0 1 sets Y-address of RAM; 0≤Y≤8 sets X-address of RAM; 0 ≤ X ≤ 101 LOW 0 1 0 0 LOW 1 LOW LOW LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOW 0 0 0 0 1 LOW LOW LOW 0 0 1 0 1 0 X 1 X 0 X D7 D6 D5 D4 D3 D2 D1 D0 (H = 0) Reserved Display control Set HIGH or LOW program range VOP Set Y-address of RAM Set X-address of RAM X6 X5 X4 0 1 0 1 D 0 X 0 0 X E PRS Y3 Y2 Y1 Y0 X3 X2 X1 X0 0 0 1 0 1 TC1 1 X TC0 0 S1 S0 (H = 1) Reserved Temperature control HVgen stages Bias system Reserved Set VOP Table 2 do not use do not use set Temperature Coefficient (TCx) multiplication of high-voltage generator voltage (Sx) set Bias System (BSx) do not use (reserved for test) write VOPx to register VOP6 VOP5 VOP4 VOP3 BS2 BS1 BS0 X X X VOP2 VOP1 VOP0 Explanations for symbols in Table 1 BIT PD V H D and E PRS 2001 Nov 14 BIT VALUE DESCRIPTION 0 chip is active 1 chip is in Power-down mode 0 horizontal addressing 1 vertical addressing 0 use basic instruction set 1 use extended instruction set 00 display blank 10 normal mode 01 all display segments on 11 inverse video mode 0 VLCD programming range LOW 1 VLCD programming range HIGH RESET STATE 1 0 0 00 13 0 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver BIT TC1 and TC0 BIT VALUE OM6206 DESCRIPTION 00 VLCD temperature coefficient 0 01 VLCD temperature coefficient 1 10 VLCD temperature coefficient 2 11 VLCD temperature coefficient 3 00 2 × voltage multiplier 01 3 × voltage multiplier 10 4 × voltage multiplier 11 5 × voltage multiplier BS2 to BS0 − bias system VOP6 to VOP0 − VLCD programming S1 and S0 8.1 RESET STATE 00 00 000 Initialization 0000000 8.3 Function set Immediately following power-on, all internal registers as well as the RAM content are undefined. A RES pulse must be applied. 8.3.1 Reset is accomplished by applying an external reset pulse (active LOW) at pin RES. When reset occurs within the specified time, all internal registers are reset however the RAM is still undefined. The state after reset is described in Section 8.2. • Bias generator and VLCD generator off; VLCD can be disconnected When PD = 1 the chip is in Power-down mode: • All LCD outputs at VSS (display off) • Oscillator off (external clock possible) • Serial bus: command, function etc. RES input must be ≤0.3VDD when VDD reaches VDD(min) (or higher) within a maximal time tVHRL after VDD going HIGH (see Fig.16). 8.2 PD • RAM contents not cleared; RAM data can be written • VLCD discharged to VSS in Power-down mode. 8.3.2 Reset function V • Horizontal addressing (V = 0) When V = 0, the horizontal addressing is selected. The data is written into the DDRAM as shown in Fig.6. When V = 1, the vertical addressing is selected. The data is written into the DDRAM as shown in Fig.5. • Normal instruction set (H = 0) 8.3.3 After reset the LCD driver has the following state: • Power-down mode (PD = 1) • Display blank (E and D = 0) When H = 0 the commands ‘display control’, ‘set Y-address’, ‘set X-address’ and ‘set the PRS bit’ (LOW or HIGH range of the high-voltage generator) can be performed; when H = 1 the others can be executed. The commands ‘write data’ and ‘function set’ can be executed in both cases. • Address counter X6 to X0 = 0, Y3 to Y0 = 0 • Temperature control (TC1 and TC0 = 0) • Bias system (BS2 to BS0 = 0) • VLCD is equal to 0 V and the high-voltage generator is switched off (VOP6 to VOP0 = 0 and PRS = 0) • After power-on, RAM data are undefined, the reset signal does not change the content of the RAM 8.4 8.4.1 • All LCD outputs at VSS (display off). 2001 Nov 14 H Display control D AND E The bits D and E select the display mode (see Table 2). 14 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 8.5 OM6206 Set Y-address of RAM Y3 to Y0 define the Y-address vector address of the display RAM. Table 3 X/Y-address range Y3 Y2 Y1 Y0 BANK(1) ALLOWED X-RANGE 0 0 0 0 0 0 to 101 0 0 0 1 1 0 to 101 0 0 1 0 2 0 to 101 0 0 1 1 3 0 to 101 0 1 0 0 4 0 to 101 0 1 0 1 5 0 to 101 0 1 1 0 6 0 to 101 0 1 1 1 7 0 to 101 1 0 0 0 8; note 2 0 to 101 Notes 1. Display RAM. 2. Only the MSB is accessed. 8.6 Set X-address of RAM 8.8 The X-address points to the columns. The range of X is 0 to 101 (65H). 8.7 Bias system The bias voltage levels are set in the ratio of 1 R - R - nR - R - R giving a ------------- bias system. Different n+4 multiplex rates require different factors n (see Table 4). This is programmed by BS2 to BS0. For multiplex rate 1 : 65 the optimum bias value n is given by: Set high-voltage generator stages The OM6206 incorporates a software configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 2 × VDD2. Other voltage multiplier factors are set via the command ‘HVgen stages’ (see Tables 1 and 2). n = 65 – 3 = 5.062 = 5 (1) resulting in a 1/9 bias system. Table 4 Programming the required bias system BS2 BS1 BS0 n RECOMMENDED MULTIPLEX RATE 0 0 0 7 1 : 100 0 0 1 6 1 : 80 0 1 0 5 1 : 65 or 1 : 65 0 1 1 4 1 : 48 1 0 0 3 1 : 40 or 1 : 34 1 0 1 2 1 : 24 1 1 0 1 1 : 18 or 1 : 16 1 1 1 0 1 : 10 or 1 : 9 or 1 : 8 2001 Nov 14 15 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver Table 5 LCD bias voltage SYMBOL V1 BIAS VOLTAGE FOR 1⁄9 BIAS BIAS VOLTAGES VLCD VLCD V2 n+3 ------------n+4 V3 n+2 ------------n+4 V4 2 ------------n+4 V5 1 ------------n+4 V6 8.9 OM6206 VSS 8⁄ 9 × VLCD 7⁄ 9 × VLCD 2⁄ 9 × VLCD 1⁄ 9 × VLCD VSS Temperature control Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage VLCD must be increased with lower temperature to maintain optimal contrast. There are four temperature coefficients available in the OM6206 (see Fig.13). The coefficients are selected by the two bits TC1 and TC0. Table 6 shows the typical values of the temperature coefficients. The coefficients are proportional to the programmed VLCD at reference temperature. handbook, halfpage MGT871 VLCD (V) (1) (2) (3) (4) (1) TC0. (2) TC1. Tcut T (°C) (3) TC2. (4) TC3. Fig.13 Temperature coefficients behaviour. 2001 Nov 14 16 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver 8.10 OM6206 Set VOP value Two overlapping VLCD ranges are selectable via the command ‘set HIGH or LOW program range VOP’. The operation voltage VLCD can be set by software. The generated voltage is dependent on the programmed voltage at reference temperature (Tcut), the programmed Temperature Coefficient (TC) and the operating temperature (T). For the LOW range (bit PRS = 0) component a = a1 and for the HIGH range (bit PRS = 1) component a = a2. The steps in both ranges are equal to b. It should be noted that the charge pump is turned off if bits VOP6 to VOP0 and bit PRS are all set to zero (see Fig.14). The voltage at reference temperature can be calculated as: V LCD ( Tcut ) = a + b × V OP (2) For multiplexer rate 1 : 65 the optimum operation voltage of the liquid can be calculated as: The voltage at operating temperature can be calculated as: V LCD(T) = V LCD(Tcut) + ( T – T cut ) × TC (3) 1 + 65 V LCD = --------------------------------------- × V th = 6.85 × V th 1 2 × 1 – ---------- 65 (4) The parameters are explained in Table 6. where Vth is the threshold voltage of the liquid crystal material used. The maximum voltage that can be generated is depending on the VDD2 voltage and the display load current. Table 6 Typical values for parameters for the high-voltage generator programming SYMBOL VALUE UNIT a1 2.94 (PRS = 0) V a2 6.75 (PRS = 1) V b 0.03 V Tcut 27 °C Table 7 Temperature coefficients BIT NAME TC0 TC1 VALUE TC1 TC0 0 0 0 1 −0.00 × 10−3 × VLCD(Tcut) UNIT V/°C −0.76 × 10−3 × VLCD(Tcut) V/°C 10−3 TC2 1 0 −1.05 × × VLCD(Tcut) V/°C TC3 1 1 −2.10 × 10−3 × VLCD(Tcut) V/°C 2001 Nov 14 17 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 handbook, full pagewidth VLCD (V) a1 charge pump off b a2 a1 + b 00 01 02 03 04 05 06 . . . 5F 6F 7F 00 01 LOW (PRS = 0) 02 03 04 05 06 . . . 5F 6F 7F HIGH (PRS = 1) MGT878 VOP6 to VOP0 to be programmed (00H to 7FH), programming ranges LOW and HIGH. Fig.14 VOP programming at T = Tcut. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD (9.0 V) the user has to ensure while setting the VOP value and selecting the Temperature Coefficient (TC), that under all conditions and including all tolerances the VLCD remains below 9.0 V. 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); notes 1 and 2. SYMBOL PARAMETER MIN. MAX. UNIT VDD1 supply voltage 1 −0.5 +6.5 V VDD2,, VDD3 supply voltages 2 and 3 −0.5 +4.5 V VLCD supply voltage LCD −0.5 +9.0 V Vi all input voltages −0.5 VDD + 0.5 V ISS ground supply current −50 +50 mA II, IO DC input or output current −10 +10 mA Ptot total power dissipation − 300 mW P/out power dissipation per output − 30 mW Tstg storage temperature −65 +150 °C Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise specified. 2001 Nov 14 18 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”). 11 DC CHARACTERISTICS VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 2.5 − 5.5 V 2.5 − 4.5 V input supply voltage LCD LCD voltage externally supplied 4.5 (voltage generator disabled) − 9.0 V VLCDOUT output supply voltage LCD LCD voltage internally generated (voltage generator enabled); note 1 4.5 − 9.0 V IDD(tot) total supply current normal mode; VDD = 2.8 V; VLCD = 7.6 V; no serial clock; Tamb = 25 °C; no display load; 4 × charge pump; note 2 − 200 300 µA Power-down mode; with internal − or external VLCD; note 3 1.5 − µA − 30 − µA VSS − 0.3VDD V VDD1 supply voltage 1 VDD2, VDD3 supply voltages 2 and 3 LCD voltage internally generated (voltage generator enabled) VLCDIN ILCDIN supply current from external VLCD VDD = 2.8 V; VLCD = 7.6 V; no serial clock; Tamb = 25 °C; no display load; notes 2 and 4 Logic VIL LOW-level input voltage VIH HIGH-level input voltage IL leakage current 0.7VDD − VDD V VI = VDD or VSS −1 − +1 µA Column and row outputs Rcol output resistance of columns C0 to C101 VLCD = 7.6 V − 12 20 kΩ Rrow output resistance of rows R0 to R64 VLCD = 7.6 V − 12 20 kΩ Vcol bias tolerance voltage of columns C0 to C101 −100 0 +100 mV Vrow bias tolerance voltage of rows R0 to R64 −100 0 +100 mV LCD supply voltage generator ∆VLCD tolerance of internally generated VLCD VDD = 2.8 V; VLCD = 7.6 V; no serial clock; Tamb = 25 °C; display load is 10 µA; notes 5 and 6 −300 0 +300 mV TC0 VLCD temperature coefficient 0 note 7 − 0 × 10−3VLCD − V/°C 2001 Nov 14 19 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver SYMBOL PARAMETER OM6206 CONDITIONS MIN. TYP. 10−3V MAX. UNIT TC1 VLCD temperature coefficient 1 note 7 − −0.76 × − V/°C TC2 VLCD temperature coefficient 2 note 7 − −1.05 × 10−3VLCD − V/°C TC3 VLCD temperature coefficient 3 note 7 − −2.10 × 10−3VLCD − V/°C LCD Notes 1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock. 3. During Power-down mode, all static currents are switched off. 4. If external VLCD, the display load current is not transmitted to IDD. 5. Tolerance depends on the temperature; typical null at Tamb = 27 °C; maximum tolerance values are measured at the temperate range limit; maximum tolerance is proportional to VLCD. 6. For TC1 to TC3. 7. VDD = 2.8 V; no serial clock; Tamb = −20 to +70 °C; display load = 10 µA. 12 AC CHARACTERISTICS VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. VDD = 2.8 V; Tamb = −20 to +70 °C 22 TYP. MAX. UNIT fosc oscillator frequency fext external clock frequency 20 38 67 kHz fframe frame frequency fosc or fext = 38 kHz; note 1 − 73 − Hz tVHRL VDD HIGH to RES LOW time see Fig.16 0 (2) − 1 µs tRW RES LOW pulse width see Fig.16 100 − − ns 0 − 4 MHz 38 67 kHz Serial bus timing characteristics; see Fig.15 fSCLK clock frequency VDD = 3.0 V ±10%; note 3 tCYC SCLK clock cycle time 250 − − ns tPWH1 SCLK pulse width HIGH 100 − − ns tPWL1 SCLK pulse width LOW 100 − − ns tS2 SCE setup time 60 − − ns tH2 SCE hold time 100 − − ns tPWH2 SCE HIGH time 100 − − ns tH5 SCE start hold time 100 − − ns tS3 D/C setup time 100 − − ns tH3 D/C hold time 100 − − ns tS4 SDIN setup time 100 − − ns tH4 SDIN hold time 100 − − ns note 4 Notes 1. f ext f frame = --------520 2001 Nov 14 20 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 2. RES may be LOW before VDD goes HIGH. 3. All signal timing is based on 20% to 80% of VDD and a maximum rise and fall time of 10 ns. 4. tH5 is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE. t S2 handbook, full pagewidth t H2 t PWH2 SCE t S3 t H3 t H5 (t H5 ) D/C t CYC t PWL1 t S2 t PWH1 SCLK t S4 t H4 SDIN MGT872 Fig.15 Serial interface timing. handbook, full pagewidth VDD t RW t RW RES VDD t VHRL t RW t RW RES MGT873 Fig.16 Reset timing. 2001 Nov 14 21 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 13 APPLICATION INFORMATION 13.1 Programming example for the OM6206 Table 8 Programming example SERIAL BUS BYTE STEP DISPLAY D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 OPERATION SCE is going LOW 1 start 2 0 0 0 1 0 0 0 0 1 function set: PD = 0 and V = 0; select extended instruction set (H = 1) 3 0 1 0 0 1 0 0 0 0 set VOP: VOP is set to a +16 × b [V] 4 0 0 0 1 0 0 0 0 0 function set: PD = 0 and V = 0; select normal instruction set (H = 0) 5 0 0 0 0 0 1 1 0 0 display control: set normal mode (D = 1 and E = 0) 6 1 0 0 0 1 1 1 1 1 data write: Y and X are initialized to 0 by default, so they are not set here MGT144 7 1 0 0 0 0 0 1 0 1 data write MGT145 8 1 0 0 0 0 0 1 1 1 data write MGT146 9 1 0 0 0 0 0 0 0 0 data write MGT146 10 1 0 0 0 1 1 1 1 1 data write MGT148 11 1 0 0 0 0 0 1 0 0 data write MGT149 2001 Nov 14 22 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 SERIAL BUS BYTE STEP 12 DISPLAY D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 1 1 1 1 1 OPERATION data write MGT151 13 0 0 0 0 0 1 1 0 1 display control: set inverse video mode (D = 1 and E = 1) MGT152 14 0 1 0 0 0 0 0 0 0 set X-address of RAM: set address to ‘0000000’ MGT152 15 1 0 0 0 0 0 0 0 0 data write MGT874 13.2 Application diagrams handbook, full pagewidth LCD (65 × 102 pixels) 102 column drivers VSS1 VSS2 VDD2 VDD1 VDD3 OM6206 32 row drivers VLCDSENSE VLCDOUT VLCDIN 33 row drivers 5 (1) CVDD I/O VDD CVLCD VSS MGT875 (1) 6 if external oscillator is used. Fig.17 Application diagram: internal charge pump is used and a single supply VDD. 2001 Nov 14 23 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 handbook, full pagewidth LCD (65 × 102 pixels) 102 column drivers VSS1 VSS2 VDD1 VDD2 VDD3 OM6206 32 row drivers VLCDSENSE VLCDOUT VLCDIN 33 row drivers 5 (1) C VDD1 VDD1 I/O CVLCD CVDD2 MGT876 VSS VDD2 (1) 6 if external oscillator is used. Fig.18 Application diagram: internal charge pump is used and two separate supplies VDD1 and VDD2. handbook, full pagewidth LCD (65 × 102 pixels) 32 row drivers VLCDIN VSS1 VSS2 VDD1 VDD2 VDD3 OM6206 VLCDOUT 102 column drivers VLCDSENSE 33 row drivers 5 (1) CVDD I/O VDD VSS VLCDIN MGT877 (1) 6 if external oscillator is used. Fig.19 Application diagram: external supply VLCDIN is used. 2001 Nov 14 24 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 • CVDD, CVDD1 and CVDD2 > 1 µF To reduce the sensitivity of a reset to ESD/EMC disturbances for a chip-on-glass application, it is strongly recommended to implement on the glass (indium track resistance) a series input resistance in the reset line (recommended minimum value of 8 kΩ). Higher capacitor values are recommended for ripple reduction. 13.4 13.3 The OM6206 is manufactured in n-well CMOS technology. The substrate is on VSS potential. The required minimum value for the external capacitors in an application with the OM6206 are: • CVLCD > 100 µF Application for COG Chip information The pinning of the OM6206 is optimized for single plane wiring e.g. for Chip-On-Glass (COG) display modules with display size of 65 × 102 pixels. 14 BONDING PAD INFORMATION COORDINATES(1) SYMBOL COORDINATES(1) SYMBOL PAD PAD x y x y row10 28 −4305 −935 row11 29 −4235 −935 RES_B 1 −3870 +935 row32 2 −4270 +935 row12 30 −4165 −935 row31 3 −4340 +935 row13 31 −4095 −935 row30 4 −4410 +935 row14 32 −4025 −935 row29 5 −4480 +935 row15 33 −3955 −935 row28 6 −4550 +935 row16 34 −3885 −935 row27 7 −4620 +935 row17 35 −3815 −935 row26 8 −4690 +935 row18 36 −3745 −935 row25 9 −4760 +935 col0 37 −3605 −935 row24 10 −4830 +935 col1 38 −3535 −935 row23 11 −4900 +935 col2 39 −3465 −935 row22 12 −4970 +935 col3 40 −3395 −935 row21 13 −5040 +935 col4 41 −3325 −935 row20 14 −5110 +935 col5 42 −3255 −935 row19 15 −5180 +935 col6 43 −3185 −935 dummy pad 16 −5320 +935 col7 44 −3115 −935 dummy pad 17 −5355 −935 col8 45 −3045 −935 row0 18 −5005 −935 col9 46 −2975 −935 row1 19 −4935 −935 col10 47 −2905 −935 row2 20 −4865 −935 col11 48 −2835 −935 row3 21 −4795 −935 col12 49 −2765 −935 row4 22 −4725 −935 col13 50 −2695 −935 row5 23 −4655 −935 col14 51 −2625 −935 row6 24 −4585 −935 col15 52 −2555 −935 row7 25 −4515 −935 col16 53 −2485 −935 row8 26 −4445 −935 col17 54 −2415 −935 row9 27 −4375 −935 col18 55 −2345 −935 2001 Nov 14 25 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 COORDINATES(1) SYMBOL COORDINATES(1) PAD SYMBOL x y PAD x y col19 56 −2275 −935 col58 95 +595 −935 col20 57 −2205 −935 col59 96 +665 −935 col21 58 −2135 −935 col60 97 +735 −935 col22 59 −2065 −935 col61 98 +805 −935 col23 60 −1995 −935 col62 99 +875 −935 col24 61 −1925 −935 col63 100 +945 −935 col25 62 −1785 −935 col64 101 +1015 −935 col26 63 −1715 −935 col65 102 +1085 −935 col27 64 −1645 −935 col66 103 +1155 −935 col28 65 −1575 −935 col67 104 +1225 −935 col29 66 −1505 −935 col68 105 +1295 −935 col30 67 −1435 −935 col69 106 +1365 −935 col31 68 −1365 −935 col70 107 +1435 −935 col32 69 −1295 −935 col71 108 +1505 −935 col33 70 −1225 −935 col72 109 +1575 −935 col34 71 −1155 −935 col73 110 +1645 −935 col35 72 −1085 −935 col74 111 +1715 −935 col36 73 −1015 −935 col75 112 +1785 −935 col37 74 −945 −935 col76 113 +1925 −935 col38 75 −875 −935 col77 114 +1995 −935 col39 76 −805 −935 col78 115 +2065 −935 col40 77 −735 −935 col79 116 +2135 −935 col41 78 −665 −935 col80 117 +2205 −935 col42 79 −595 −935 col81 118 +2275 −935 col43 80 −525 −935 col82 119 +2345 −935 col44 81 −455 −935 col83 120 +2415 −935 col45 82 −385 −935 col84 121 +2485 −935 col46 83 −315 −935 col85 122 +2555 −935 col47 84 −245 −935 col86 123 +2625 −935 col48 85 −175 −935 col87 124 +2695 −935 col49 86 −105 −935 col88 125 +2765 −935 col50 87 +35 −935 col89 126 +2835 −935 col51 88 +105 −935 col90 127 +2905 −935 col52 89 +175 −935 col91 128 +2975 −935 col53 90 +245 −935 col92 129 +3045 −935 col54 91 +315 −935 col93 130 +3115 −935 col55 92 +385 −935 col94 131 +3185 −935 col56 93 +455 −935 col95 132 +3255 −935 col57 94 +525 −935 col96 133 +3325 −935 2001 Nov 14 26 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 COORDINATES(1) SYMBOL COORDINATES(1) PAD SYMBOL x y PAD x y col97 134 +3395 −935 dummy pad 173 +4050 +935 col98 135 +3465 −935 VDD1 174 +3890 +935 col99 136 +3535 −935 VDD1 175 +3810 +935 col100 137 +3605 −935 VDD1 176 +3730 +935 col101 138 +3675 −935 VDD1 177 +3650 +935 row50 139 +3815 −935 VDD1 178 +3570 +935 row49 140 +3885 −935 VDD1 179 +3490 +935 row48 141 +3955 −935 VDD3 180 +3250 +935 row47 142 +4025 −935 VDD2 181 +3090 +935 row46 143 +4095 −935 VDD2 182 +3010 +935 row45 144 +4165 −935 VDD2 183 +2930 +935 row44 145 +4235 −935 VDD2 184 +2850 +935 row43 146 +4305 −935 VDD2 185 +2770 +935 row42 147 +4375 −935 VDD2 186 +2690 +935 row41 148 +4445 −935 VDD2 187 +2610 +935 row40 149 +4515 −935 VDD2 188 +2530 +935 row39 150 +4585 −935 VDD2 189 +2450 +935 row38 151 +4655 −935 VDD2 190 +2370 +935 row37 152 +4725 −935 VDD2 191 +2290 +935 row36 153 +4795 −935 VDD2 192 +2210 +935 row35 154 +4865 −935 VDD2 193 +2130 +935 row34 155 +4935 −935 SCLK 194 +1890 +935 row33 156 +5005 −935 SDIN 195 +1650 +935 dummy pad 157 +5355 −935 DC_B 196 +1410 +935 dummy pad 158 +5320 +935 SCE_B 197 +1170 +935 row51 159 +5180 +935 T2 198 +930 +935 row52 160 +5110 +935 OSC 199 +690 +935 row53 161 +5040 +935 VSS2 200 +530 +935 row54 162 +4970 +935 VSS2 201 +450 +935 row55 163 +4900 +935 VSS2 202 +370 +935 row56 164 +4830 +935 VSS2 203 +290 +935 row57 165 +4760 +935 VSS2 204 +210 +935 row58 166 +4690 +935 VSS2 205 +130 +935 row59 167 +4620 +935 VSS2 206 +50 +935 row60 168 +4550 +935 VSS2 207 −30 +935 row61 169 +4480 +935 VSS2 208 −110 +935 row62 170 +4410 +935 VSS2 209 −190 +935 row63 171 +4340 +935 VSS2 210 −270 +935 row64 172 +4270 +935 VSS2 211 −350 +935 2001 Nov 14 27 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 Table 9 COORDINATES(1) SYMBOL x y VSS2 212 −430 +935 VSS2 213 −510 +935 VSS1 214 −670 +935 VSS1 215 −750 +935 VSS1 216 −830 +935 VSS1 217 −910 +935 T1 218 −1150 +935 T5 219 −1630 +935 T4 220 −2030 +935 VSS1 221 −2110 +935 VSS1 222 −2190 +935 T3 223 −2270 +935 VLCDIN 224 −2510 +935 VLCDIN 225 −2590 +935 VLCDIN 226 −2670 +935 VLCDIN 227 −2750 +935 VLCDIN 228 −2830 +935 VLCDIN 229 −2910 +935 VLCDOUT 230 −3070 +935 VLCDOUT 231 −3150 +935 VLCDOUT 232 −3230 +935 VLCDOUT 233 −3310 +935 VLCDOUT 234 −3390 +935 VLCDOUT 235 −3470 +935 VLCDOUT 236 −3550 +935 VLCDSENSE 237 −3630 +935 Circle 1 −5185 −910 Circle 2 +5185 −910 Circle 3 +4160 +910 Circle 4 −4160 +910 NAME Alignment marks Note 1. All x/y coordinates (in µm) are referenced to the centre of the chip (see Fig.20). 2001 Nov 14 Bonding pad dimensions PAD 28 DIMENSION Pad pitch 70 µm Pad size, aluminium 62 × 100 µm Bump dimensions 50 × 90 × 17.5 (±5) µm Wafer thickness (including bumps) maximum 430 µm Wafer thickness (without bumps) typical 380 µm This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... R51 dummy bump R64 dummy bump alignment mark (1) alignment mark (1) VDD1 VDD3 VDD2 SCLK SDIN D/C SCE T2 OSC VSS2 VSS1 T1 T5 T3 VSS1 T4 VLCDIN VLCDOUT RES VLCDSENSE pad 237 alignment mark (1) pad 1 row 32 dummy bump row 19 R33 C101 R50 C75 C76 C49 C50 C24 C25 . .. . .. . .. . .. dummy bump . .. . .. . .. . .. . .. . .. . .. . .. R18 C0 OM6206 R0 29 alignment mark (1) x Philips Semiconductors ... . .. . .. . .. 0, 0 65 × 102 pixels matrix LCD driver andbook, full pagewidth 2001 Nov 14 2.14 mm y dummy bump 10.94 mm MGT887 Product specification Fig.20 Bonding pad locations. OM6206 (1) The alignment marks are circles with a diameter of 100 µm. Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 15 DEVICE PROTECTION CIRCUITS SYMBOL VDD1 PAD INTERNAL CIRCUIT 174 to 179 VSS1 MGT879 VDD2 181 to 193 lfpage VSS1 VSS2 MGT880 VDD3 180 VSS1 MGT879 VSS1 214 to 217, 221, 222 VSS2 200 to 213 VSS2 MGT883 VLCDIN 224 to 229 VLCDSENSE 237 VLCDOUT 230 to 236 MGT879 T2 198 T3 223 VSS1 VDD1 MGT882 2001 Nov 14 VSS1 30 VSS1 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver SYMBOL PAD SDIN 195 SCLK 194 SCE 197 D/C 196 OSC 199 RES 1 T1 217 T4 218 T5 220 R0 to R64 2 to 15, 18 to 36, 139 to 156, 159 to 172 C0 to C101 OM6206 INTERNAL CIRCUIT VDD1 MGT884 VSS1 halfpage 37 to 138 VLCDIN 1 per block VSS1 MGT881 2001 Nov 14 31 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 16 TRAY INFORMATION x handbook, full pagewidth y G A C H D B F E MGT885 Fig.21 Tray details. handbook, halfpage OM6206 MGT886 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. Fig.22 Tray alignment. 2001 Nov 14 32 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 Table 10 Tray dimensions DIMENSIONS 2001 Nov 14 DESCRIPTION VALUE A pocket pitch; in the x direction 13.77 mm B pocket pitch; in the y direction 4.45 mm C pocket width; in the x direction 11.04 mm D pocket width; in the y direction 2.24 mm E tray width; in the x direction 50.8 mm F tray width; in the y direction 50.8 mm G distance from cut corner to pocket centre 11.63 mm H distance from cut corner to pocket centre 5.41 mm x number of pockets in the x direction 3 y number of pockets in the y direction 10 33 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 17 DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. 18 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products 2001 Nov 14 34 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver OM6206 NOTES 2001 Nov 14 35 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA73 © Koninklijke Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403506/01/pp36 Date of release: 2001 Nov 14 Document order number: 9397 750 07746