PHILIPS 74LVC1G00GF

74LVC1G00
Single 2-input NAND gate
Rev. 9 — 7 December 2011
Product data sheet
1. General description
The 74LVC1G00 provides the single 2-input NAND function.
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
 Wide supply voltage range from 1.65 V to 5.5 V
 High noise immunity
 Complies with JEDEC standard:
 JESD8-7 (1.65 V to 1.95 V)
 JESD8-5 (2.3 V to 2.7 V)
 JESD8-B/JESD36 (2.7 V to 3.6 V)
 24 mA output drive (VCC = 3.0 V)
 CMOS low power consumption
 Latch-up performance exceeds 250 mA
 Direct interface with TTL levels
 Inputs accept voltages up to 5 V
 Multiple package options
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 Specified from 40 C to +85 C and 40 C to +125 C
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC1G00GW
40 C to +125 C
TSSOP5
plastic thin shrink small outline package;
5 leads; body width 1.25 mm
SOT353-1
74LVC1G00GV
40 C to +125 C
SC-74A
plastic surface-mounted package; 5 leads
SOT753
74LVC1G00GM
40 C to +125 C
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1  1.45  0.5 mm
SOT886
74LVC1G00GF
40 C to +125 C
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1  1  0.5 mm
SOT891
74LVC1G00GN
40 C to +125 C
XSON6
extremely thin small outline package; no leads; SOT1115
6 terminals; body 0.9  1.0  0.35 mm
74LVC1G00GS
40 C to +125 C
XSON6
extremely thin small outline package; no leads; SOT1202
6 terminals; body 1.0  1.0  0.35 mm
4. Marking
Table 2.
Marking codes
Type number
Marking[1]
74LVC1G00GW
VA
74LVC1G00GV
V00
74LVC1G00GM
VA
74LVC1G00GF
VA
74LVC1G00GN
VA
74LVC1G00GS
VA
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
B
1
B
2
A
1
Y
4
&
4
Y
2
A
mna097
Fig 1.
Logic symbol
74LVC1G00
Product data sheet
mna099
mna098
Fig 2.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 7 December 2011
Fig 3.
Logic diagram
© NXP B.V. 2011. All rights reserved.
2 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
6. Pinning information
6.1 Pinning
74LVC1G00
74LVC1G00
B
1
A
2
GND
3
5
VCC
B
1
6
VCC
A
2
5
n.c.
GND
4
Y
4
Y
B
1
6
VCC
A
2
5
n.c.
GND
3
4
Y
001aaf051
001aab603
Transparent top view
001aab608
Fig 4.
3
74LVC1G00
Pin configuration
SOT353-1 and SOT753
Fig 5.
Pin configuration SOT886
Transparent top view
Fig 6.
Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
B
1
1
data input
A
2
2
data input
GND
3
3
ground (0 V)
SOT353-1, SOT753 SOT886, SOT891, SOT1115 and SOT1202
Y
4
4
data output
n.c.
-
5
not connected
VCC
5
6
supply voltage
7. Functional description
Table 4.
Function table[1]
Inputs
Outputs
A
B
L
L
H
L
H
H
H
L
H
H
H
L
[1]
Y
H = HIGH voltage level; L = LOW voltage level.
74LVC1G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
3 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
IO
output current
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
Max
Unit
0.5
+6.5
V
50
-
mA
0.5
+6.5
V
-
50
mA
Active mode
[1][2]
0.5
VCC + 0.5
V
Power-down mode
[1][2]
0.5
+6.5
V
-
50
mA
-
+100
mA
100
-
mA
-
250
mW
65
+150
C
VO > VCC or VO < 0 V
output voltage
VO
Min
VO = 0 V to VCC
Tamb = 40 C to +125 C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VCC
Conditions
Min
Typ
Max
Unit
supply voltage
1.65
-
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
Active mode
0
-
VCC
V
VCC = 0 V; Power-down mode
0
-
5.5
V
40
-
+125
C
VCC = 1.65 V to 2.7 V
-
-
20
ns/V
VCC = 2.7 V to 5.5 V
-
-
10
ns/V
Tamb
ambient temperature
t/V
input transition rise and fall rate
74LVC1G00
Product data sheet
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Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
4 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
HIGH-level
input voltage
VIH
LOW-level
input voltage
VIL
VOH
40 C to +85 C
Conditions
VCC = 1.65 V to 1.95 V
Min
Max
Min
Max
Unit
0.65VCC
-
-
0.65VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
0.7VCC
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
-
0.3VCC
V
VCC  0.1
-
-
VCC  0.1
-
V
IO = 4 mA; VCC = 1.65 V
1.2
-
-
0.95
-
V
HIGH-level
VI = VIH or VIL
output voltage
IO = 100 A;
VCC = 1.65 V to 5.5 V
0.35VCC V
IO = 8 mA; VCC = 2.3 V
1.9
-
-
1.7
-
V
IO = 12 mA; VCC = 2.7 V
2.2
-
-
1.9
-
V
IO = 24 mA; VCC = 3.0 V
2.3
-
-
2.0
-
V
IO = 32 mA; VCC = 4.5 V
3.8
-
-
3.4
-
V
-
-
0.1
-
0.1
V
-
-
0.45
-
0.70
V
LOW-level
VI = VIH or VIL
output voltage
IO = 100 A;
VCC = 1.65 V to 5.5 V
VOL
40 C to +125 C
Typ[1]
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
0.3
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
-
0.60
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.80
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
-
0.80
V
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
-
0.1
5
-
100
A
IOFF
power-off
leakage
current
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
200
A
ICC
supply current VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
-
0.1
10
-
200
A
ICC
additional
VCC = 2.3 V to 5.5 V;
supply current VI = VCC  0.6 V; IO = 0 A;
per pin
-
5
500
-
5000
A
CI
input
capacitance
-
5
-
-
-
pF
[1]
VCC = 3.3 V; VI = GND to VCC
All typical values are measured at VCC = 3.3 V and Tamb = 25 C.
74LVC1G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
5 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 8.
Symbol Parameter
40 C to +85 C
Conditions
power dissipation
capacitance
CPD
Unit
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
1.0
3.3
8.0
1.0
10.5
ns
VCC = 2.3 V to 2.7 V
0.5
2.2
5.5
0.5
7.0
ns
VCC = 2.7 V
0.5
2.6
5.8
0.5
7.5
ns
VCC = 3.0 V to 3.6 V
0.5
2.2
4.7
0.5
6.0
ns
VCC = 4.5 V to 5.5 V
0.5
1.8
4.0
0.5
5.5
ns
-
14
-
-
-
pF
[2]
propagation delay A, B to Y; see Figure 7
tpd
40 C to +125 C
Typ[1]
[3]
VI = GND to VCC;
VCC = 3.3 V
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2]
tpd is the same as tPLH and tPHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
12. Waveforms
VI
VM
A, B input
GND
t PHL
t PLH
VOH
VM
Y output
mna612
VOL
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output.
Fig 7.
The input (A and B) to output (Y) propagation delay times
74LVC1G00
Product data sheet
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Rev. 9 — 7 December 2011
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74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
1.65 V to 1.95 V
0.5VCC
0.5VCC
2.3 V to 2.7 V
0.5VCC
0.5VCC
2.7 V
1.5 V
1.5 V
3.0 V to 3.6 V
1.5 V
1.5 V
4.5 V to 5.5 V
0.5VCC
0.5VCC
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8.
Table 10.
Test circuit for measuring switching times
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr = tf
CL
RL
tPLH, tPHL
1.65 V to 1.95 V
VCC
 2.0 ns
30 pF
1 k
open
2.3 V to 2.7 V
VCC
 2.0 ns
30 pF
500 
open
2.7 V
2.7 V
 2.5 ns
50 pF
500 
open
3.0 V to 3.6 V
2.7 V
 2.5 ns
50 pF
500 
open
4.5 V to 5.5 V
VCC
 2.5 ns
50 pF
500 
open
74LVC1G00
Product data sheet
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Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
7 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
E
D
SOT353-1
A
X
c
y
HE
v M A
Z
5
4
A2
A
(A3)
A1
θ
1
Lp
3
L
e
w M
bp
detail X
e1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
e1
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.1
0
1.0
0.8
0.15
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
0.65
1.3
2.25
2.0
0.425
0.46
0.21
0.3
0.1
0.1
0.60
0.15
7°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT353-1
Fig 9.
REFERENCES
IEC
JEDEC
JEITA
MO-203
SC-88A
EUROPEAN
PROJECTION
ISSUE DATE
00-09-01
03-02-19
Package outline SOT353-1 (TSSOP5)
74LVC1G00
Product data sheet
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Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
8 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
Plastic surface-mounted package; 5 leads
SOT753
D
E
B
y
A
X
HE
5
v M A
4
Q
A
A1
c
1
2
3
Lp
detail X
bp
e
w M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
c
D
E
e
HE
Lp
Q
v
w
y
mm
1.1
0.9
0.100
0.013
0.40
0.25
0.26
0.10
3.1
2.7
1.7
1.3
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT753
JEITA
SC-74A
EUROPEAN
PROJECTION
ISSUE DATE
02-04-16
06-03-16
Fig 10. Package outline SOT753 (SC-74A)
74LVC1G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
9 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L1
e
6
5
4
e1
e1
6×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
1.5
1.4
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE
VERSION
SOT886
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-07-15
04-07-22
MO-252
Fig 11. Package outline SOT886 (XSON6)
74LVC1G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
10 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
1
SOT891
b
3
2
4×
(1)
L
L1
e
6
5
4
e1
e1
6×
A
(1)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.20
0.12
1.05
0.95
1.05
0.95
0.55
0.35
0.35
0.27
0.40
0.32
Note
1. Can be visible in some manufacturing processes.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-04-06
07-05-15
SOT891
Fig 12. Package outline SOT891 (XSON6)
74LVC1G00
Product data sheet
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Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
11 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
1
SOT1115
b
3
2
(4×)(2)
L
L1
e
6
5
4
e1
e1
(6×)(2)
A1
A
D
E
terminal 1
index area
0
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
b
D
E
e
e1
max 0.35 0.04 0.20 0.95 1.05
nom
0.15 0.90 1.00 0.55
min
0.12 0.85 0.95
0.3
L
L1
0.35 0.40
0.30 0.35
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1115_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-07
SOT1115
Fig 13. Package outline SOT1115 (XSON6)
74LVC1G00
Product data sheet
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Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
12 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
1
SOT1202
b
3
2
(4×)(2)
L
L1
e
6
5
4
e1
e1
(6×)(2)
A1
A
D
E
terminal 1
index area
0
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
b
D
E
e
e1
L
L1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
nom
0.15 1.00 1.00 0.55 0.35 0.30 0.35
min
0.12 0.95 0.95
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1202_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-06
SOT1202
Fig 14. Package outline SOT1202 (XSON6)
74LVC1G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
13 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC1G00 v.9
20111207
Product data sheet
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74LVC1G00 v.8
Modifications:
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Legal pages updated.
74LVC1G00 v.8
20101020
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20070717
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20060915
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20040907
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20021115
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20020515
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20001108
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74LVC1G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
14 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
74LVC1G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
15 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LVC1G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 7 December 2011
© NXP B.V. 2011. All rights reserved.
16 of 17
74LVC1G00
NXP Semiconductors
Single 2-input NAND gate
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 7 December 2011
Document identifier: 74LVC1G00