PHILIPS P89LPC916

P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
2 kB 3 V Flash with 8-bit A/D converter
Rev. 04 — 17 December 2004
Product data
1. General description
The P89LPC915/916/917 are single-chip microcontrollers in low-cost 14-pin and
16-pin packages, based on a high performance processor architecture that executes
instructions in two to four clocks, six times the rate of standard 80C51 devices. Many
system level functions have been incorporated into the P89LPC915/916/917 in order
to reduce component count, board space, and system cost.
2. Features
■ 2 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.
■ 256-byte RAM data memory.
■ Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC917) may be configured
to toggle a port output upon timer overflow or to become a PWM output.
■ 23-bit system timer that can also be used as a Real-Time clock.
■ 4-input multiplexed 8-bit A/D converter/single DAC output. Two analog
comparators with selectable reference.
■ Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
■ SPI communication port (P89LPC916).
■ Internal RC oscillator option allows operation without external oscillator
components. The RC oscillator (factory calibrated to ±1 %) option is selectable
and fine tunable.
■ 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
■ Up to 14 I/O pins when using internal oscillator and reset options (P89LPC916,
P89LPC917).
3. Additional features
• 14-pin (P89LPC915) and 16-pin (P89LPC916, P89LPC917) TSSOP packages.
• A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz.
This is six times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
• In-Application Programming (IAP-Lite) and byte erase allows code memory to be
used for non-volatile data storage.
• Serial Flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
• Watchdog timer with separate on-chip oscillator, requiring no external
components. The Watchdog prescaler is selectable from 8 values.
• Low-voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt.
• Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a low interrupt input starts execution). Typical power-down
current is 1 µA (total power-down with voltage comparators disabled).
• Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.
• Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
• Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value
of the pins match or do not match a programmable pattern.
• LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
• Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
• Only power and ground connections are required to operate the
P89LPC915/916/917 when internal reset option is selected.
• Four interrupt priority levels.
• Five (P89LPC916), six (P89LPC915), or seven (P89LPC917) keypad interrupt
inputs.
• Second data pointer.
• Schmitt trigger port inputs.
• Emulation support.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
2 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
4. Ordering information
Table 1:
Ordering information
Type number
Package
Name
Description
Version
P89LPC915FDH
TSSOP14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
P89LPC915HDH
TSSOP14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
P89LPC916FDH
TSSOP16
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT403-1
P89LPC917FDH
TSSOP16
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT403-1
4.1 Ordering options
Table 2:
Ordering options[1]
Type number
Temperature range
Frequency
P89LPC915HDH
−40 °C to +125 °C
0 MHz to 18 MHz
P89LPC915FDH
−40 °C to +85 °C
P89LPC916FDH
P89LPC917FDH
[1]
Please contact your local Philips sales office for availability of extended temperature
(−40 °C to +125 °C) versions of the P89LPC916 and P89LPC917 devices.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
3 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
5. Block diagram
P89LPC915
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
2 kB
CODE FLASH
256-BYTE
DATA RAM
UART
INTERNAL
BUS
I2C
PORT 1
CONFIGURABLE I/Os
ADC1/DAC1
PORT 0
CONFIGURABLE I/Os
REAL-TIME CLOCK/
SYSTEM TIMER
KEYPAD
INTERRUPT
TIMER 0
TIMER 1
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
external
clock
input
ANALOG
COMPARATORS
CPU
CLOCK
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
ON-CHIP RC
OSCILLATOR
002aaa822
Fig 1. P89LPC915 block diagram.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
4 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC916
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
2 kB
CODE FLASH
256-BYTE
DATA RAM
UART
INTERNAL
BUS
I2C
PORT 2
CONFIGURABLE I/Os
ADC1/DAC1
PORT 1
CONFIGURABLE I/Os
SPI
PORT 0
CONFIGURABLE I/Os
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
external
clock
input
ANALOG
COMPARATORS
CPU
CLOCK
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
ON-CHIP RC
OSCILLATOR
002aaa823
Fig 2. P89LPC916 block diagram.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
5 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC917
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
2 kB
CODE FLASH
256-BYTE
DATA RAM
UART
INTERNAL
BUS
I2C
PORT 2
CONFIGURABLE I/Os
ADC1/DAC1
PORT 1
CONFIGURABLE I/Os
REAL-TIME CLOCK/
SYSTEM TIMER
PORT 0
CONFIGURABLE I/Os
TIMER 0
TIMER 1
KEYPAD
INTERRUPT
ANALOG
COMPARATORS
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
external
clock
input
CPU
CLOCK
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
ON-CHIP RC
OSCILLATOR
CLKOUT
002aaa824
Fig 3. P89LPC917 block diagram.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
6 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
6. Pinning information
6.1 Pinning
CIN2B/KBI1/AD10/P0.1
1
14 P0.2/CIN2A/KBI2/AD11
KBI0/CMP2/P0.0
2
13 P0.3/CIN1B/KBI3/AD12
RST/P1.5
3
VSS
4
INT1/P1.4
5
10 VDD
SDA/INT0/P1.3
6
9
P1.0/TXD
SCL/T0/P1.2
7
8
P1.1/RXD
12 P0.4/CIN1A/KBI4/AD13/DAC1
LPC915
11 P0.5/CMPREF/KBI5/CLKIN
002aaa825
Fig 4. P89LPC915 TSSOP14 pin configuration.
CIN2B/KBI1/AD10/P0.1
1
16 P0.2/CIN2A/KBI2/AD11
SS/P2.4
2
15 P0.3/CIN1B/KB13/AD12
RST/P1.5
3
14 P0.4/CIN1A/KBI4/AD13/DAC1
VSS
4
MISO/P2.3
5
MOSI/P2.2
6
12 VDD
11 P2.5/SPICLK
SDA/INT0/P1.3
7
10 P1.0/TXD
SCL/T0/P1.2
8
LPC916
13 P0.5/CMPREF/KBI5/CLKIN
9
P1.1/RXD
002aaa826
Fig 5. P89LPC916 TSSOP16 pin configuration.
CIN2B/KBI1/AD10/P0.1
1
16 P0.2/CIN2A/KBI2/AD11
KBI0/CMP2/P0.0
2
15 P0.3/CIN1B/KB13/AD12
RST/P1.5
3
14 P0.4/CIN1A/KBI4/AD13/DAC1
VSS
4
MOSI/P2.2
5
INT1/P1.4
6
12 VDD
11 P0.7/T1/KBI7/CLKOUT
SDA/INT0/P1.3
7
10 P1.0/TXD
SCL/T0/P1.2
8
9
LPC917
13 P0.5/CMPREF/KBI5/CLKIN
P1.1/RXD
002aaa827
Fig 6. P89LPC917 TSSOP16 pin configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
7 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
6.2 Pin description
Table 3:
P89LPC915 pin description
Symbol
Pin
P0.0 to P0.5
Type
Description
I/O
Port 0: Port 0 is a 6-bit I/O port with user-configurable outputs. During reset Port 0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 9.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
2
1
14
13
12
11
I/O
P0.0 — Port 0 bit 0.
I
CMP2 — Comparator 2 output.
I
KBI0 — Keyboard input 0.
I/O
P0.1 — Port 0 bit 1.
I
CIN2B — Comparator 2 positive input B.
I
KBI1 — Keyboard input 1.
I
AD10 — A/D channel 1, input 0
I/O
P0.2 — Port 0 bit 2.
I
CIN2A — Comparator 2 positive input A.
I
KBI2 — Keyboard input 2.
I
AD11 — A/D channel 1, input 1
I/O
P0.3 — Port 0 bit 3.
I
CIN1B — Comparator 1 positive input B.
I
KBI3 — Keyboard input 3.
I
AD12 — A/D channel 1, input 2.
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input A.
I
KBI4 — Keyboard input 4.
I
AD13 — A/D channel 1, input 3.
O
DAC1 — Digital to analog converter 1 output.
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
I
CLKIN — External clock input.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
8 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 3:
P89LPC915 pin description…continued
Symbol
Pin
P1.0 to P1.5
Type
Description
I/O
Port 1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port 1
(P1.2); latches are configured in the input only mode with the internal pull-up disabled. The
I (P1.5) operation of the inputs and outputs depends upon the port configuration selected.
Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details. P1.2 is an open drain when used as an output. P1.5 is
input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
9
8
7
6
5
3
I/O
P1.0 — Port 1 bit 0
O
TxD — Serial port transmitter data.
I/O
P1.1 — Port 1 bit 0
I
RxD — Serial port receiver data.
I/O
P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O
T0 — Timer/counter 0 external count input, overflow output, or PWM output.
I/O
SCL — I2C-bus serial clock input/output.
I/O
P1.3 — Port 1 bit 2. (Open drain when used as an output.)
I/O
INT0 — External interrupt 0 input.
I/O
SDA — I2C-bus serial data input/output.
I/O
P1.4 — Port 1 bit 2.
I/O
INT1 — External interrupt 1input.
I
P1.5 — Port 1 bit 5. (Input only.)
I
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level.
When system power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.
Also used during a power-on sequence to force In-System Programming mode.
VSS
4
I
Ground: 0 V reference.
VDD
10
I
Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
9 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 4:
P89LPC916 pin description
Symbol
Pin
P0.1 to P0.5
Type
Description
I/O
Port 0: Port 0 is a 5-bit I/O port with user-configurable outputs. During reset Port 0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 9.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
1
16
15
14
13
I/O
P0.1 — Port 0 bit 1.
I
CIN2B — Comparator 2 positive input B.
I
KBI1 — Keyboard input 1.
I
AD10 — A/D channel 1, input 0
I/O
P0.2 — Port 0 bit 2.
I
CIN2A — Comparator 2 positive input A.
I
KBI2 — Keyboard input 2.
I
AD11 — A/D channel 1, input 1
I/O
P0.3 — Port 0 bit 3.
I
CIN1B — Comparator 1 positive input B.
I
KBI3 — Keyboard input 3.
I
AD12 — A/D channel 1, input 2.
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input A.
I
KBI4 — Keyboard input 4.
I
AD13 — A/D channel 1, input 3.
O
DAC1 — Digital to analog converter 1 output.
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
I
CLKIN — External clock input.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
10 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 4:
P89LPC916 pin description…continued
Symbol
Pin
P1.0 to P1.5
Type
Description
I/O
Port 1: Port 1 is a 5-bit I/O port with user-configurable outputs. During reset Port 1
(P1.2); latches are configured in the input only mode with the internal pull-up disabled. The
I (P1.5) operation of the P1.2 input and outputs depends upon the port configuration selected.
Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details. P1.2 is an open drain when used as an output. P1.5 is
input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
10
9
8
7
3
I/O
P1.0 — Port 1 bit 0
O
TxD — Serial port transmitter data.
I/O
P1.1 — Port 1 bit 0
I
RxD — Serial port receiver data.
I/O
P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O
T0 — Timer/counter 0 external count input, overflow output, or PWM output.
I/O
SCL — I2C-bus serial clock input/output.
I/O
P1.3 — Port 1 bit 2. (Open drain when used as an output.)
I/O
INT0 — External interrupt 0 input.
I/O
SDA — I2C-bus serial data input/output.
I
P1.5 — Port 1 bit 5. (Input only.)
I
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level.
When system power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.
Also used during a power-on sequence to force In-System Programming mode.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
11 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 4:
P89LPC916 pin description…continued
Symbol
Pin
P2.2 to P2.5
Type
Description
I/O
Port 2: Port 2 is a 4-bit I/O port having user-configurable output types. During reset
Port 1 latches are configured in the input only mode with the internal pull-up disabled.
The operation of the P2 input and outputs depends upon the port configuration
selected. Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
6
5
2
11
I/O
P2.2 — Port 2 bit 2.
O
MOSI — SPI master out slave in. When configured as a master this pin is an output.
When configured as a slave, this pin is an input.
I/O
P2.3 — Port 2 bit 3.
I
MISO — SPI master in slave out. When configured as a master this pin is an input.
When configured as a slave, this pin is an output.
I/O
P2.4 — Port 2 bit 4.
I/O
SS — SPI Slave select.
I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — When configured as a master this pin is an output. When configured as a
slave, this pin is an input.
VSS
4
I
Ground: 0 V reference.
VDD
12
I
Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
12 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 5:
P89LPC917 pin description
Symbol
Pin
P0.0 to P0.5
Type
Description
I/O
Port 0: Port 0 is a 7-bit I/O port with user-configurable outputs. During reset Port 0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 9.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
2
1
16
15
14
13
11
I/O
P0.0 — Port 0 bit 0.
I
CMP2 — Comparator 2 output.
I
KBI0 — Keyboard input 0.
I/O
P0.1 — Port 0 bit 1.
I
CIN2B — Comparator 2 positive input B.
I
KBI1 — Keyboard input 1.
I
AD10 — A/D channel 1, input 0
I/O
P0.2 — Port 0 bit 2.
I
CIN2A — Comparator 2 positive input A.
I
KBI2 — Keyboard input 2.
I
AD11 — A/D channel 1, input 1
I/O
P0.3 — Port 0 bit 3.
I
CIN1B — Comparator 1 positive input B.
I
KBI3 — Keyboard input 3.
I
AD12 — A/D channel 1, input 2.
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input A.
I
KBI4 — Keyboard input 4.
I
AD13 — A/D channel 1, input 3.
O
DAC1 — Digital to analog converter 1 output.
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
I
CLKIN — External clock input.
I/O
P0.7 — Port 0 bit 7.
I
T1 — Timer/counter 1 external count input, overflow output, or PWM output.
I
KBI7 — Keyboard input 7.
I
CLKOUT — Clock output.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
13 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 5:
P89LPC917 pin description…continued
Symbol
Pin
P1.0 to P1.5
Type
Description
I/O
Port 1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port 1
(P1.2); latches are configured in the input only mode with the internal pull-up disabled. The
I (P1.5) operation of the outputs depends upon the port configuration selected. Refer to
Section 9.12.1 “Port configurations” and Table 13 “DC electrical characteristics” for
details. P1.2 and P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
10
9
8
7
6
3
P2.2
5
I/O
P1.0 — Port 1 bit 0.
O
TxD — Serial port transmitter data.
I/O
P1.1 — Port 1 bit 1.
I
RxD — Serial port receiver data.
I/O
P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O
T0 — Timer/counter 0 external count input, overflow, or PWM output.
I/O
SCL — I2C-bus serial clock input/output.
I/O
P1.3 — Port 1 bit 3. (Open drain when used as an output.)
I/O
INT0 — External interrupt 0 input.
I/O
SDA — I2C-bus serial data input/output.
I/O
P1.4 — Port 1 bit 4.
I/O
INT1 — External interrupt 1input.
I
P1.5 — Port 1 bit 5. (Input only.)
I
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level.
When system power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.
Also used during a power-on sequence to force In-System Programming mode.
I/O
Port 2: Port 2.2 is a single-bit I/O port with a user-configurable output. During reset
the Port 2.2 latch is configured in the input only mode with the internal pull-up
disabled. The operation of the output depends upon the port configuration selected.
Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details.
This pin has a Schmitt triggered input.
VSS
4
I
Ground: 0 V reference.
VDD
12
I
Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
14 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
7. Logic symbols
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
VSS
P89LPC915
PORT 1
DAC1
AD10
AD11
AD12
AD13
CLKIN
PORT 0
VDD
TxD
RxD
T0
INT0
INT1
RST
SCL
SDA
002aaa828
Fig 7. P89LPC915 logic symbol.
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
P89LPC916
TxD
RxD
T0
INT0
SCL
SDA
RST
PORT 2
KBI1
KBI2
KBI3
KBI4
KBI5
PORT 0
DAC1
AD10
AD11
AD12
AD13
CLKIN
VSS
PORT 1
VDD
MOSI
MISO
SS
SPICLK
002aaa829
Fig 8. P89LPC916 logic symbol.
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI7
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
T1
VSS
P89LPC917
PORT 1
DAC1
AD10
AD11
AD12
AD13
CLKIN
CLKOUT
PORT 0
VDD
TxD
RxD
T0
INT0
INT1
RST
SCL
SDA
PORT 2
002aaa830
Fig 9. P89LPC917 logic symbol.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
15 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
7.1 Product comparison
Table 6 highlights the differences between these three devices. For a complete list of
device features, please see Section 2 “Features” on page 1.
Table 6:
Product comparison
Type number
Comp 2
output
SPI
T1 PWM
output
CLKOUT
INT1
KBI
P89LPC915
X
-
-
-
X
6
P89LPC916
-
X
-
-
-
5
P89LPC917
X
-
X
X
X
7
8. Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.
– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
16 of 72
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors
9397 750 14397
Product data
Table 7:
P89LPC915 Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr.
MSB
Bit address
E7
E6
E5
Reset value
LSB
E4
E3
E2
E1
Hex
Binary
00
00000000
ADCS10 00
00000000
E0
Accumulator
E0H
ADCON1
A/D control register 1
97H
ENBI1
ENADCI
1
TMM1
EDGE1
ADCI1
ADINS
A/D input select
A3H
ADI13
ADI12
ADI11
ADI10
-
-
-
-
00
00000000
ADMODA
A/D mode register A
C0H
BNDI1
BURST1
SCC1
SCAN1
-
-
-
-
00
00000000
ADMODB
A/D mode register B
A1H
CLK2
CLK1
CLK0
-
ENDAC1
-
BSA1
-
00
000x0000
AD1BH
A/D_1 boundary high register
C4H
FF
11111111
AD1BL
A/D_1 boundary low register
BCH
00
00000000
AD1DAT0
A/D_1 data register 0
D5H
00
00000000
AD1DAT1
A/D_1 data register 1
D6H
00
00000000
AD1DAT2
A/D_1 data register 2
D7H
00
00000000
AD1DAT3
A/D_1 data register 3
F5H
00
00000000
AUXR1
Auxiliary function register
A2H
00
000000x0
Bit address
ENADC1 ADCS11
CLKLP
EBRR
-
ENT0
SRST
0
-
DPS
F7
F6
F5
F4
F3
F2
F1
F0
B register
F0H
00
00000000
BRGR0[2]
Baud rate generator rate low
BEH
00
00000000
BRGR1[2]
Baud rate generator rate high
BFH
00
00000000
BDH
BRGEN
00[2]
xxxxxx00
xx000000
BRGCON
Baud rate generator control
-
-
-
-
-
-
SBRGS
17 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
CMP1
Comparator 1 control register
ACH
-
-
CE1
CP1
CN1
-
CO1
CMF1
00[1]
CMP2
Comparator 2 control register
ADH
-
-
CE2
CP2
CN2
OE2
CO2
CMF2
00[1]
xx000000
DIVM
CPU clock divide-by-M
control
95H
00
00000000
DPTR
Data pointer (2 bytes)
DPH
Data pointer high
83H
00
00000000
DPL
Data pointer low
82H
00
00000000
FMADRH
Program Flash address high
E7H
00
00000000
FMADRL
Program Flash address low
E6H
00
00000000
-
-
-
-
-
-
P89LPC915/916/917
B*
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
ACC*
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
FMCON
Description
SFR Bit functions and addresses
addr.
MSB
Program Flash Control
(Read)
E4H
Program Flash Control (Write)
FMDATA
Program Flash data
E5H
I2ADR
I2C-bus
DBH
slave address
Philips Semiconductors
9397 750 14397
Product data
Table 7:
P89LPC915 Special function registers…continued
* indicates SFRs that are bit addressable.
Reset value
LSB
BUSY
-
-
-
HVA
HVE
SV
OI
FMCMD.
7
FMCMD.
6
FMCMD.
5
FMCMD.
4
FMCMD.
3
FMCMD.
2
FMCMD.
1
FMCMD.
0
I2ADR.6
I2ADR.5
I2ADR.4
I2ADR.3
I2ADR.2
I2ADR.1
I2ADR.0
GC
DF
DE
DD
DC
DB
DA
D9
D8
-
I2EN
STA
STO
SI
AA
-
CRSEL
Hex
Binary
70
01110000
00
00000000
00
00000000
00
x00000x0
register
Bit address
D8H
I2DAT
data register
DAH
I2SCLH
Serial clock generator/SCL
duty cycle register high
DDH
00
00000000
I2SCLL
Serial clock generator/SCL
duty cycle register low
DCH
00
00000000
I2STAT
I2C-bus status register
D9H
F8
11111000
IEN0*
Interrupt enable 0
00
00000000
00[1]
00x00000
Bit address
A8H
Bit address
IEN1*
Interrupt enable 1
IP0*
Interrupt priority 0
E8H
Bit address
18 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
IP0H
Interrupt priority 0 high
B8H
B7H
Bit address
STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0
AF
AE
AD
AC
AB
AA
A9
A8
EA
EWDRT
EBO
ES/ESR
ET1
EX1
ET0
EX0
EF
EE
ED
EC
EB
EA
E9
E8
EAD
EST
-
-
-
EC
EKBI
EI2C
BF
BE
BD
BC
BB
BA
B9
B8
-
PWDRT
PBO
PS/PSR
PT1
PX1
PT0
PX0
00[1]
x0000000
00[1]
x0000000
-
PWDRT
H
PBOH
PSH/
PSRH
PT1H
PX1H
PT0H
PX0H
FF
FE
FD
FC
FB
FA
F9
F8
IP1*
Interrupt priority 1
F8H
PAD
PST
-
-
-
PC
PKBI
PI2C
00[1]
00x00000
IP1H
Interrupt priority 1 high
F7H
PADH
PSTH
-
-
-
PCH
PKBIH
PI2CH
00[1]
00x00000
KBIF
00[1]
xxxxxx00
KBCON
Keypad control register
94H
-
-
-
-
-
-
PATN
_SEL
KBMASK
Keypad interrupt mask
register
86H
00
00000000
KBPATN
Keypad pattern register
93H
FF
11111111
P89LPC915/916/917
control register
I2C-bus
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
I2CON*
I2C-bus
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR Bit functions and addresses
addr.
MSB
Bit address
P0*
Port 0
80H
Bit address
Reset value
LSB
87
86
85
84
83
82
81
80
-
-
CMPREF
/KBI5
CIN1A
/KBI4
CIN1B
/KBI3
CIN2A
/KBI2
CIN2B
/KBI1
CMP2
/KBI0
97
96
95
94
93
92
91
90
RST
INT1
INT0/
SDA
T0/SCL
RXD
TXD
Hex
Binary
[1]
[1]
P1*
Port 1
90H
-
-
P0M1
Port 0 output mode 1
84H
-
-
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1]
11111111
P0M2
Port 0 output mode 2
85H
-
-
(P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1]
00000000
-
(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0)
D3[1]
11x1xx11
(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0)
00[1]
00x0xx00
P1M1
Port 1 output mode 1
Port 1 output mode 2
PCON
PCONA
-
92H
-
-
-
Power control register
87H
SMOD1
SMOD0
BOPD
BOI
GF1
GF0
PMOD1
PMOD0
Power control register A
B5H
RTCPD
-
VCPD
ADPD
I2PD
-
SPD
-
D7
D6
D5
D4
D3
D2
D1
D0
D0H
CY
AC
F0
RS1
RS0
OV
F1
Bit address
PSW*
Program status word
PT0AD
Port 0 digital input disable
F6H
-
-
RSTSRC
Reset source register
DFH
-
-
RTCCON
Real-time clock control
BOF
POF
R_BK
R_WD
R_SF
00000000
00000000
P
00
00000000
-
00
xx00000x
[3]
R_EX
60[1][6]
011xxx00
D2H
00[6]
00000000
00000000
D1H
Real-time clock register high
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
00
00[1]
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
19 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
RTCL
Real-time clock register low
D3H
00[6]
SADDR
Serial port address register
A9H
00
00000000
SADEN
Serial port address enable
B9H
00
00000000
SBUF
Serial Port data buffer register
99H
xx
xxxxxxxx
9F
9E
9D
9C
9B
9A
99
98
SCON*
Serial port control
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
00
00000000
SSTAT
Serial port extended status
register
BAH
DBMOD
INTLO
CIDIS
DBISEL
FE
BR
OE
STINT
00
00000000
SP
Stack pointer
81H
07
00000111
TAMOD
Timer 0 and 1 auxiliary mode
8FH
-
-
-
-
-
-
-
T0M2
00
xxx0xxx0
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00
00000000
Bit address
Bit address
TCON*
Timer 0 and 1 control
88H
P89LPC915/916/917
RTCH
-
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
P1M2
91H
Philips Semiconductors
9397 750 14397
Product data
Table 7:
P89LPC915 Special function registers…continued
* indicates SFRs that are bit addressable.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR Bit functions and addresses
addr.
MSB
Reset value
LSB
Hex
Binary
TH0
Timer 0 high
8CH
00
00000000
TH1
Timer 1 high
8DH
00
00000000
TL0
Timer 0 low
8AH
00
00000000
TL1
Timer 1 low
8BH
00
00000000
TMOD
Timer 0 and 1 mode
89H
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
00
00000000
Internal oscillator trim register
96H
RCCLK
-
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4] [6]
WDL
Watchdog load
C1H
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
[4]
[5]
[6]
FF
11111111
All ports are in input only (high impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other
resets will not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset
P89LPC915/916/917
20 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
TRIM
[5] [6]
[1]
[2]
[3]
Philips Semiconductors
9397 750 14397
Product data
Table 7:
P89LPC915 Special function registers…continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors
9397 750 14397
Product data
Table 8:
P89LPC916 Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr.
MSB
Bit address
E7
E6
E5
Reset value
LSB
E4
E3
E2
E1
Hex
Binary
00
00000000
ADCS10 00
00000000
E0
Accumulator
E0H
ADCON1
A/D control register 1
97H
ENBI1
ENADCI
1
TMM1
EDGE1
ADCI1
ADINS
A/D input select
A3H
ADI13
ADI12
ADI11
ADI10
-
-
-
-
00
00000000
ADMODA
A/D mode register A
C0H
BNDI1
BURST1
SCC1
SCAN1
-
-
-
-
00
00000000
ADMODB
A/D mode register B
A1H
CLK2
CLK1
CLK0
-
ENDAC1
-
BSA1
-
00
000x0000
AD1BH
A/D_1 boundary high register
C4H
FF
11111111
AD1BL
A/D_1 boundary low register
BCH
00
00000000
AD1DAT0
A/D_1 data register 0
D5H
00
00000000
AD1DAT1
A/D_1 data register 1
D6H
00
00000000
AD1DAT2
A/D_1 data register 2
D7H
00
00000000
AD1DAT3
A/D_1 data register 3
F5H
00
00000000
AUXR1
Auxiliary function register
A2H
00
000000x0
Bit address
ENADC1 ADCS11
CLKLP
EBRR
-
ENT0
SRST
0
-
DPS
F7
F6
F5
F4
F3
F2
F1
F0
B register
F0H
00
00000000
BRGR0[2]
Baud rate generator rate low
BEH
00
00000000
BRGR1[2]
Baud rate generator rate high
BFH
00
00000000
BDH
BRGEN
00[2]
xxxxxx00
xx000000
BRGCON
Baud rate generator control
-
-
-
-
-
-
SBRGS
21 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
CMP1
Comparator 1 control register
ACH
-
-
CE1
CP1
CN1
-
CO1
CMF1
00[1]
CMP2
Comparator 2 control register
ADH
-
-
CE2
CP2
CN2
OE2
CO2
CMF2
00
xx000000
DIVM
CPU clock divide-by-M
control
95H
00
00000000
DPTR
Data pointer (2 bytes)
DPH
Data pointer high
83H
00
00000000
DPL
Data pointer low
82H
00
00000000
FMADRH
Program Flash address high
E7H
00
00000000
FMADRL
Program Flash address low
E6H
00
00000000
-
-
-
-
-
-
P89LPC915/916/917
B*
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
ACC*
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
FMCON
Description
SFR Bit functions and addresses
addr.
MSB
Program Flash Control
(Read)
E4H
Program Flash Control (Write)
FMDATA
Program Flash data
E5H
I2ADR
I2C-bus
DBH
slave address
Philips Semiconductors
9397 750 14397
Product data
Table 8:
P89LPC916 Special function registers…continued
* indicates SFRs that are bit addressable.
Reset value
LSB
BUSY
-
-
-
HVA
HVE
SV
OI
FMCMD.
7
FMCMD.
6
FMCMD.
5
FMCMD.
4
FMCMD.
3
FMCMD.
2
FMCMD.
1
FMCMD.
0
I2ADR.6
I2ADR.5
I2ADR.4
I2ADR.3
I2ADR.2
I2ADR.1
I2ADR.0
GC
DF
DE
DD
DC
DB
DA
D9
D8
-
I2EN
STA
STO
SI
AA
-
CRSEL
Hex
Binary
70
01110000
00
00000000
00
00000000
00
x00000x0
register
Bit address
D8H
I2DAT
data register
DAH
I2SCLH
Serial clock generator/SCL
duty cycle register high
DDH
00
00000000
I2SCLL
Serial clock generator/SCL
duty cycle register low
DCH
00
00000000
I2STAT
I2C-bus status register
D9H
F8
11111000
IEN0*
Interrupt enable 0
00
00000000
00[1]
00x00000
Bit address
A8H
Bit address
IEN1*
Interrupt enable 1
IP0*
Interrupt priority 0
E8H
Bit address
22 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
IP0H
Interrupt priority 0 high
B8H
B7H
Bit address
STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0
AF
AE
AD
AC
AB
AA
A9
A8
EA
EWDRT
EBO
ES/ESR
ET1
-
ET0
EX0
EF
EE
ED
EC
EB
EA
E9
E8
EAD
EST
-
-
ESPI
EC
EKBI
EI2C
BF
BE
BD
BC
BB
BA
B9
B8
-
PWDRT
PBO
PS/PSR
PT1
-
PT0
PX0
00[1]
x0000000
00[1]
x0000000
-
PWDRT
H
PBOH
PSH/
PSRH
PT1H
-
PT0H
PX0H
FF
FE
FD
FC
FB
FA
F9
F8
IP1*
Interrupt priority 1
F8H
PAD
PST
-
-
PSPI
PC
PKBI
PI2C
00[1]
00x00000
IP1H
Interrupt priority 1 high
F7H
PADH
PSTH
-
-
PSPIH
PCH
PKBIH
PI2CH
00[1]
00x00000
KBIF
00[1]
xxxxxx00
KBCON
Keypad control register
94H
-
-
-
-
-
-
PATN
_SEL
KBMASK
Keypad interrupt mask
register
86H
00
00000000
KBPATN
Keypad pattern register
93H
FF
11111111
P89LPC915/916/917
control register
I2C-bus
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
I2CON*
I2C-bus
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR Bit functions and addresses
addr.
MSB
Bit address
P0*
Port 0
80H
Bit address
P1*
Port 1
P2*
Port 2
90H
Bit address
P0M1
P0M2
A0H
Port 0 output mode 1
84H
Port 0 output mode 2
85H
Reset value
LSB
87
86
85
84
83
82
81
80
-
-
CMPREF
/KBI5
CIN1A
/KBI4
CIN1B
/KBI3
CIN2A
/KBI2
CIN2B
/KBI1
-
97
96
95
94
93
92
91
90
-
-
RST
-
INT0/
SDA
T0/SCL
RXD
TXD
97
96
95
94
93
92
91
90
-
-
SPICLK
SS
MISO
MOSI
-
-
-
-
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1)
(P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1)
Hex
Binary
[1]
[1]
[1]
11111111
-
00[1]
00000000
D3[1]
11x1xx11
Port 1 output mode 1
91H
-
-
-
-
(P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0)
P1M2
Port 1 output mode 2
92H
-
-
-
-
(P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00[1]
00x0xx00
-
FF[1]
11111111
-
-
00[1]
00000000
Port 2 output mode 1
P2M2
Port 2 output mode 2
PCON
PCONA
A4H
-
-
Power control register
87H
SMOD1
SMOD0
BOPD
BOI
GF1
GF0
PMOD1
PMOD0
Power control register A
B5H
RTCPD
-
VCPD
ADPD
I2PD
SPPD
SPD
-
D7
D6
D5
D4
D3
D2
D1
D0
D0H
CY
AC
F0
RS1
RS0
OV
F1
Program status word
PT0AD
Port 0 digital input disable
F6H
-
-
RSTSRC
Reset source register
DFH
-
-
23 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
RTCH
Real-time clock control
BOF
POF
R_BK
R_WD
R_SF
00000000
00000000
P
00
00000000
-
00
xx00000x
[3]
R_EX
60[1][6]
011xxx00
D2H
00[6]
00000000
00000000
D1H
Real-time clock register high
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
00
00[1]
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
RTCL
Real-time clock register low
D3H
00[6]
SADDR
Serial port address register
A9H
00
00000000
SADEN
Serial port address enable
B9H
00
00000000
SBUF
Serial Port data buffer register
99H
xx
xxxxxxxx
9F
9E
9D
9C
9B
9A
99
98
SCON*
Serial port control
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
00
00000000
SSTAT
Serial port extended status
register
BAH
DBMOD
INTLO
CIDIS
DBISEL
FE
BR
OE
STINT
00
00000000
Bit address
P89LPC915/916/917
-
PSW*
(P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2)
-
A5H
Bit address
RTCCON
(P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2)
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
-
FF[1]
P1M1
P2M1
Philips Semiconductors
9397 750 14397
Product data
Table 8:
P89LPC916 Special function registers…continued
* indicates SFRs that are bit addressable.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR Bit functions and addresses
addr.
MSB
Reset value
LSB
Hex
Binary
07
00000111
Stack pointer
81H
SPCTL
SPI control register
E2H
SSIG
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
04
00000100
SPSTAT
SPI status register
E1H
SPIF
WCOL
-
-
-
-
-
-
00
00xxxxxx
SPDAT
SPI data register
E3H
00
00000000
TAMOD
Timer 0 and 1 auxiliary mode
8FH
00
xxx0xxx0
TCON*
Timer 0 and 1 control
88H
00
00000000
TH0
Timer 0 high
8CH
00
00000000
TH1
Timer 1 high
8DH
00
00000000
TL0
Timer 0 low
8AH
00
00000000
TL1
Timer 1 low
8BH
00
00000000
TMOD
Timer 0 and 1 mode
89H
Bit address
-
-
-
-
-
-
T0M2
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
-
-
IE0
IT0
Rev. 04 — 17 December 2004
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
00
00000000
TRIM
Internal oscillator trim register
96H
RCCLK
-
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
[5] [6]
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4] [6]
WDL
Watchdog load
C1H
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
24 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[4]
[5]
[6]
11111111
All ports are in input only (high impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other
resets will not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset.
P89LPC915/916/917
[1]
[2]
[3]
FF
8-bit microcontrollers with accelerated two-clock 80C51 core
SP
-
Philips Semiconductors
9397 750 14397
Product data
Table 8:
P89LPC916 Special function registers…continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors
9397 750 14397
Product data
Table 9:
P89LPC917 Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr.
MSB
Bit address
E7
E6
E5
Reset value
LSB
E4
E3
E2
E1
Hex
Binary
00
00000000
ADCS10 00
00000000
E0
Accumulator
E0H
ADCON1
A/D control register 1
97H
ENBI1
ENADCI
1
TMM1
EDGE1
ADCI1
ADINS
A/D input select
A3H
ADI13
ADI12
ADI11
ADI10
-
-
-
-
00
00000000
ADMODA
A/D mode register A
C0H
BNDI1
BURST1
SCC1
SCAN1
-
-
-
-
00
00000000
ADMODB
A/D mode register B
A1H
CLK2
CLK1
CLK0
-
ENDAC1
-
BSA1
-
00
000x0000
AD1BH
A/D_1 boundary high register
C4H
FF
11111111
AD1BL
A/D_1 boundary low register
BCH
00
00000000
AD1DAT0
A/D_1 data register 0
D5H
00
00000000
AD1DAT1
A/D_1 data register 1
D6H
00
00000000
AD1DAT2
A/D_1 data register 2
D7H
00
00000000
AD1DAT3
A/D_1 data register 3
F5H
00
00000000
AUXR1
Auxiliary function register
A2H
00
000000x0
Bit address
ENADC1 ADCS11
CLKLP
EBRR
ENT1
ENT0
SRST
0
-
DPS
F7
F6
F5
F4
F3
F2
F1
F0
B register
F0H
00
00000000
BRGR0[2]
Baud rate generator rate low
BEH
00
00000000
BRGR1[2]
Baud rate generator rate high
BFH
00
00000000
BDH
BRGEN
00[2]
xxxxxx00
xx000000
BRGCON
Baud rate generator control
-
-
-
-
-
-
SBRGS
25 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
CMP1
Comparator 1 control register
ACH
-
-
CE1
CP1
CN1
-
CO1
CMF1
00[1]
CMP2
Comparator 2 control register
ADH
-
-
CE2
CP2
CN2
OE2
CO2
CMF2
00[1]
xx000000
DIVM
CPU clock divide-by-M
control
95H
00
00000000
DPTR
Data pointer (2 bytes)
DPH
Data pointer high
83H
00
00000000
DPL
Data pointer low
82H
00
00000000
FMADRH
Program Flash address high
E7H
00
00000000
FMADRL
Program Flash address low
E6H
00
00000000
-
-
-
-
-
-
P89LPC915/916/917
B*
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
ACC*
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
FMCON
Description
SFR Bit functions and addresses
addr.
MSB
Program Flash Control
(Read)
E4H
Program Flash Control (Write)
FMDATA
Program Flash data
E5H
I2ADR
I2C-bus
DBH
slave address
Philips Semiconductors
9397 750 14397
Product data
Table 9:
P89LPC917 Special function registers…continued
* indicates SFRs that are bit addressable.
Reset value
LSB
BUSY
-
-
-
HVA
HVE
SV
OI
FMCMD.
7
FMCMD.
6
FMCMD.
5
FMCMD.
4
FMCMD.
3
FMCMD.
2
FMCMD.
1
FMCMD.
0
I2ADR.6
I2ADR.5
I2ADR.4
I2ADR.3
I2ADR.2
I2ADR.1
I2ADR.0
GC
DF
DE
DD
DC
DB
DA
D9
D8
-
I2EN
STA
STO
SI
AA
-
CRSEL
Hex
Binary
70
01110000
00
00000000
00
00000000
00
x00000x0
register
Bit address
D8H
I2DAT
data register
DAH
I2SCLH
Serial clock generator/SCL
duty cycle register high
DDH
00
00000000
I2SCLL
Serial clock generator/SCL
duty cycle register low
DCH
00
00000000
I2STAT
I2C-bus status register
D9H
F8
11111000
IEN0*
Interrupt enable 0
00
00000000
00[1]
00x00000
Bit address
A8H
Bit address
IEN1*
Interrupt enable 1
IP0*
Interrupt priority 0
E8H
Bit address
26 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
IP0H
Interrupt priority 0 high
B8H
B7H
Bit address
STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0
AF
AE
AD
AC
AB
AA
A9
A8
EA
EWDRT
EBO
ES/ESR
ET1
EX1
ET0
EX0
EF
EE
ED
EC
EB
EA
E9
E8
EAD
EST
-
-
-
EC
EKBI
EI2C
BF
BE
BD
BC
BB
BA
B9
B8
-
PWDRT
PBO
PS/PSR
PT1
PX1
PT0
PX0
00[1]
x0000000
00[1]
x0000000
-
PWDRT
H
PBOH
PSH/
PSRH
PT1H
PX1H
PT0H
PX0H
FF
FE
FD
FC
FB
FA
F9
F8
IP1*
Interrupt priority 1
F8H
PAD
PST
-
-
-
PC
PKBI
PI2C
00[1]
00x00000
IP1H
Interrupt priority 1 high
F7H
PADH
PSTH
-
-
-
PCH
PKBIH
PI2CH
00[1]
00x00000
KBIF
00[1]
xxxxxx00
KBCON
Keypad control register
94H
-
-
-
-
-
-
PATN
_SEL
KBMASK
Keypad interrupt mask
register
86H
00
00000000
KBPATN
Keypad pattern register
93H
FF
11111111
P89LPC915/916/917
control register
I2C-bus
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
I2CON*
I2C-bus
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR Bit functions and addresses
addr.
MSB
Bit address
P0*
Port 0
80H
Bit address
Reset value
LSB
87
86
85
84
83
82
81
80
T1/KBI7/
CLKOUT
-
CMPREF
/KBI5
CIN1A
/KBI4
CIN1B
/KBI3
CIN2A
/KBI2
CIN2B
/KBI1
CMP2
/KBI0
97
96
95
94
93
92
91
90
RST
INT1
INT0/
SDA
T0/SCL
RXD
TXD
Hex
Binary
[1]
[1]
P1*
Port 1
90H
-
-
P0M1
Port 0 output mode 1
84H
(P0M1.7)
-
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1]
11111111
P0M2
Port 0 output mode 2
85H
(P0M2.7)
-
(P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1]
00000000
-
(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0)
D3[1]
11x1xx11
(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0)
00[1]
00x0xx00
P1M1
Port 1 output mode 1
Port 1 output mode 2
PCON
PCONA
-
92H
-
-
-
Power control register
87H
SMOD1
SMOD0
BOPD
BOI
GF1
GF0
PMOD1
PMOD0
Power control register A
B5H
RTCPD
-
VCPD
ADPD
I2PD
-
SPD
-
D7
D6
D5
D4
D3
D2
D1
D0
D0H
CY
AC
F0
RS1
RS0
OV
F1
Bit address
PSW*
Program status word
PT0AD
Port 0 digital input disable
F6H
-
-
RSTSRC
Reset source register
DFH
-
-
RTCCON
Real-time clock control
BOF
POF
R_BK
R_WD
R_SF
00000000
00000000
P
00
00000000
-
00
xx00000x
[3]
R_EX
60[1][6]
011xxx00
D2H
00[6]
00000000
00000000
D1H
Real-time clock register high
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
00
00[1]
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
27 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
RTCL
Real-time clock register low
D3H
00[6]
SADDR
Serial port address register
A9H
00
00000000
SADEN
Serial port address enable
B9H
00
00000000
SBUF
Serial Port data buffer register
99H
xx
xxxxxxxx
9F
9E
9D
9C
9B
9A
99
98
SCON*
Serial port control
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
00
00000000
SSTAT
Serial port extended status
register
BAH
DBMOD
INTLO
CIDIS
DBISEL
FE
BR
OE
STINT
00
00000000
SP
Stack pointer
81H
07
00000111
TAMOD
Timer 0 and 1 auxiliary mode
8FH
-
-
-
T1M2
-
-
-
T0M2
00
xxx0xxx0
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00
00000000
Bit address
Bit address
TCON*
Timer 0 and 1 control
88H
P89LPC915/916/917
RTCH
-
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
P1M2
91H
Philips Semiconductors
9397 750 14397
Product data
Table 9:
P89LPC917 Special function registers…continued
* indicates SFRs that are bit addressable.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Name
Description
SFR Bit functions and addresses
addr.
MSB
Reset value
LSB
Hex
Binary
TH0
Timer 0 high
8CH
00
00000000
TH1
Timer 1 high
8DH
00
00000000
TL0
Timer 0 low
8AH
00
00000000
TL1
Timer 1 low
8BH
00
00000000
TMOD
Timer 0 and 1 mode
89H
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
00
00000000
Internal oscillator trim register
96H
RCCLK
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4] [6]
WDL
Watchdog load
C1H
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
[4]
[5]
[6]
FF
11111111
All ports are in input only (high impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other
resets will not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset.
P89LPC915/916/917
28 of 72
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8-bit microcontrollers with accelerated two-clock 80C51 core
Rev. 04 — 17 December 2004
TRIM
[5] [6]
[1]
[2]
[3]
Philips Semiconductors
9397 750 14397
Product data
Table 9:
P89LPC917 Special function registers…continued
* indicates SFRs that are bit addressable.
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
9. Functional description
Remark: Please refer to the P89LPC915/916/917 User’s Manual for a more detailed
functional description.
9.1 Enhanced CPU
The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at 6 times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles,
and most instructions execute in one or two machine cycles.
9.2 Clocks
9.2.1
Clock definitions
The P89LPC915/916/917 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of three
clock sources (see Figure 10) and can also be optionally divided to a slower
frequency (see Section 9.7 “CPU Clock (CCLK) modification: DIVM register”).
Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
9.2.2
CPU clock (OSCCLK)
The P89LPC915/916/917 provide user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the FLASH is programmed and
include an on-chip Watchdog oscillator, an on-chip RC oscillator, and an external
clock input.
9.2.3
Clock output (P89LPC917)
The P89LPC917 supports a user selectable clock output function on the CLKOUT
pin. This allows external devices to synchronize to the P89LPC917. This output is
enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is
1⁄ that of the CCLK. If the clock output is not needed in Idle mode, it may be turned
2
off prior to entering Idle, saving additional power.
9.3 On-chip RC oscillator option
The P89LPC915/916/917 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1 % at room
temperature. End-user applications can write to the TRIM register to adjust the
on-chip RC oscillator to other frequencies.
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9.4 Watchdog oscillator option
The Watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.
9.5 External clock input option
In this configuration, the processor clock is derived from an external source driving
the CLKIN pin. The rate may be from 0 Hz up to 18 MHz. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reached its specified level. When system power is removed VDD will fall below
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage.
RTCS1:0
XCLK
RTC
RCCLK
CLKOUT
OSCCLK
CLKIN
CCLK
DIVM
RC
OSCILLATOR
CPU
RCCLK
ADC1/DAC1
(7.3728 MHz)
÷2
PCLK
WDT
WATCHDOG
OSCILLATOR
peripheral clock
PCLK
(400 kHz)
BAUD RATE
GENERATOR
UART
TIMERS 1 & 0
I2C
SPI
(P89LPC916)
002aaa831
Fig 10. Block diagram of oscillator control.
9.6 CPU Clock (CCLK) wake-up delay
The P89LPC915/916/917 has an internal wake-up timer that delays the clock until it
stabilizes. The delay is 224 OSCCLK cycles plus 60 to 100 µs.
9.7 CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
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the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
9.8 Low power select
The P89LPC915/916/917 are designed to run at 18 MHz (CCLK) maximum.
However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to
logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
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9.9 A/D converter
9.9.1
General description
The P89LPC915/916/917 has an 8-bit, 4-channel multiplexed successive
approximation analog-to-digital converter. A block diagram of the A/D converter is
shown in Figure 11. The A/D consists of a 4-input multiplexer which feeds a
sample-and-hold circuit providing an input signal to one of two comparator inputs.
The control logic in combination with the successive approximation register (SAR)
drives a digital-to-analog converter which provides the other input to the comparator.
The output of the comparator is fed to the SAR.
COMP
INPUT
MUX
+
SAR
–
8
DAC1
CONTROL
LOGIC
CCLK
002aaa783
Fig 11. ADC block diagram.
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9.9.2
Features
• An 8-bit, 4-channel multiplexed input, successive approximation A/D converter
• Four A/D result registers
• Six operating modes
– Fixed channel, single conversion mode
– Fixed channel, continuous conversion mode
– Auto scan, single conversion mode
– Auto scan, continuous conversion mode
– Dual channel, continuous conversion mode
– Single step mode
• Three conversion start modes
– Timer triggered start
– Start immediately
– Edge triggered
•
•
•
•
•
•
9.9.3
8-bit conversion time of ≥3.9 µs at an ADC clock of 3.3 MHz
Interrupt or polled operation
Boundary limits interrupt
DAC output to a port pin with high output impedance
Clock divider
Power-down mode
A/D operating modes
Fixed channel, single conversion mode: A single input channel can be selected for
conversion. A single conversion will be performed and the result placed in the result
register which corresponds to the selected input channel. An interrupt, if enabled, will
be generated after the conversion completes.
Fixed channel, continuous conversion mode: A single input channel can be
selected for continuous conversion. The results of the conversions will be sequentially
placed in the four result registers. An interrupt, if enabled, will be generated after
every four conversions. Additional conversion results will again cycle through the four
result registers, overwriting the previous results. Continuous conversions continue
until terminated by the user.
Auto scan, single conversion mode: Any combination of the four input channels
can be selected for conversion. A single conversion of each selected input will be
performed and the result placed in the result register which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after all selected
channels have been converted. If only a single channel is selected this is equivalent
to single channel, single conversion mode.
Auto scan, continuous conversion mode: Any combination of the four input
channels can be selected for conversion. A conversion of each selected input will be
performed and the result placed in the result register which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after all selected
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channels have been converted. The process will repeat starting with the first selected
channel. Additional conversion results will again cycle through the four result
registers, overwriting the previous results. Continous conversions continue until
terminated by the user.
Dual channel, continuous conversion mode: This is a variation of the auto scan
continuous conversion mode where conversion occurs on two user-selectable inputs.
The result of the conversion of the first channel is placed in result register, AD1DAT0.
The result of the conversion of the second channel is placed in result register,
AD1DAT1. The first channel is again converted and its result stored in AD1DAT2. The
second channel is again converted and its result placed in AD1DAT3. An interrupt is
generated, if enabled, after every set of four conversions (two conversions per
channel).
Single step mode: This special mode allows ‘single-stepping’ in an auto scan
conversion mode. Any combination of the four input channels can be selected for
conversion. After each channel is converted, an interrupt is generated, if enabled,
and the A/D waits for the next start condition. May be used with any of the start
modes.
9.9.4
Conversion start modes
Timer triggered start: An A/D conversion is started by the overflow of Timer 0. Once
a conversion has started, additional Timer 0 triggers are ignored until the conversion
has completed. The Timer triggered start mode is available in all A/D operating
modes.
Start immediately: Programming this mode immediately starts a conversion. This
start mode is available in all A/D operating modes.
Edge triggered: (P89LPC915/917) An A/D conversion is started by rising or falling
edge of P1.4. Once a conversion has started, additional edge triggers are ignored
until the conversion has completed. The edge triggered start mode is available in all
A/D operating modes.
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9.9.5
Boundary limits interrupt
The A/D converters have both a high and low boundary limit register. After the four
MSBs have been converted, these four bits are compared with the four MSBs of the
boundary high and low registers. If the four MSBs of the conversion are outside the
limit an interrupt will be generated, if enabled. If the conversion result is within the
limits, the boundary limits will again be compared after all 8 bits have been converted.
An interrupt will be generated, if enabled, if the result is outside the boundary limits.
The boundary limit may be disabled by clearing the boundary limit interrupt enable.
9.9.6
DAC output to a port pin with high output impedance
The A/D converter’s DAC block can be output to a port pin. In this mode, the
AD1DAT3 register is used to hold the value fed to the DAC. After a value has been
written to AD1DAT3, the DAC output will appear on the channel 3 pin.
9.9.7
Clock divider
The A/D converter requires that its internal clock source be in the range of 500 kHz to
3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock
from 1 to 8 is provided for this purpose.
9.9.8
Power-down and Idle mode
In Idle mode the A/D converter, if enabled, will continue to function and can cause the
device to exit Idle mode when the conversion is completed if the A/D interrupt is
enabled. In Power-down mode or Total power-down mode, the A/D does not function.
If the A/D is enabled, it will consume power. Power can be reduced by disabling the
A/D.
9.10 Memory organization
The various P89LPC915/916/917 memory spaces are as follows:
• DATA
256 bytes of internal data memory space (00h:FFh) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC915/916/917 has 2 kB of on-chip Code memory.
9.11 Interrupts
The P89LPC915/916/917 uses a four priority level interrupt structure. This allows
great flexibility in controlling the handling of the many interrupt sources.
The P89LPC915 and P89LPC917 support 13 interrupt sources: external interrupts 0
and 1, timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx and Tx,
brownout detect, Watchdog/Real-Time clock, I2C, keyboard, comparators 1 and 2,
and the A/D converter.
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The P89LPC916supports 14 interrupt sources: external interrupt 0, timers 0 and 1,
serial port Tx, serial port Rx, combined serial port Rx and Tx, brownout detect,
Watchdog/Real-Time clock, I2C, keyboard, comparators 1 and 2, SPI, and the A/D
converter.
Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
9.11.1
External interrupt inputs
The P89LPC915 and P89LPC917 have two external interrupt inputs as well as the
Keypad Interrupt function. The P89LPC916 has one external interrupt input as well as
the Keypad Interrupt function These external interrupt inputs are identical to those
present on the standard 80C51 microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.
If an external interrupt is enabled when the P89LPC915/916/917 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and
resume operation. Refer to Section 9.14 “Power reduction modes” for details.
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IE0
EX0
(P89LPC915/917)
IE1
EX1
BOF
EBO
RTCF
ERTC
(RTCCON.1)
WDOVF
WAKE-UP
(IF IN POWER-DOWN)
KBIF
EKBI
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF0
ET0
TF1
ET1
TI & RI/RI
ES/ESR
TI
EST
INTERRUPT
TO CPU
SI
EI2C
(P89LPC916)
SPIF
ESPI
ENADCI1
ADCI1
ENBI1
BNDI1
EAD
002aaa833
Fig 12. Interrupt sources, interrupt enables, and power-down wake-up sources.
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9.12 I/O ports
The P89LPC916 and P89LPC917 devices have three I/O ports: Port 0, Port 1, and
Port 2. The exact number of I/O pins available depends on the clock and reset options
chosen, as shown in Table 10.
Table 10:
Number of I/O pins available (P89LPC916, P89LPC917)
Clock source
Reset option
Number of
I/O pins
(16-pin
package)
RC oscillator or Watchdog oscillator No external reset (except during
power-up)
External clock input
[1]
14
External RST pin supported
13
No external reset (except during
power-up)
13
External RST pin supported[1]
12
Required for operation above 12 MHz.
The P89LPC915 has 2I/O ports: Port 0, and Port 1. The exact number of I/O pins
available depends on the reset option chosen, as shown in Table 11.
Table 11:
Number of I/O pins available (P89LPC915)
Clock source
Reset option
Number of
I/O pins
(14-pin
package)
RC oscillator or Watchdog oscillator No external reset (except during
power-up)
External clock input
[1]
9.12.1
12
External RST pin supported
11
No external reset (except during
power-up)
11
External RST pin supported[1]
10
Required for operation above 12 MHz.
Port configurations
Except as listed below, every I/O pin on the P89LPC915/916/917 may be configured
by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional
(standard 80C51 port outputs), push-pull, open drain, and input-only. Two
configuration registers for each port select the output type for each port pin.
P1.5/RST can only be an input and cannot be configured.
SCL/T0/P1.2 and SDA/INTO/P1.3 may only be configured to be either input-only or
open drain.
9.12.2
Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the
need to reconfigure the port. This is possible because when the port outputs a logic
HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the
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pin is driven LOW, it is driven strongly and able to sink a fairly large current. These
features are somewhat similar to an open-drain output except that there are three
pull-up transistors in the quasi-bidirectional output that serve different purposes.
The P89LPC915/916/917 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current
flowing from the pin to VDD, causing extra power consumption. Therefore, applying
5 V in quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch
suppression circuit.
9.12.3
Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic 0. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to VDD.
An open-drain port pin has a Schmitt triggered input that also has a glitch
suppression circuit.
9.12.4
Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt triggered input
that also has a glitch suppression circuit.
9.12.5
Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic 1. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt triggered input that also has a glitch suppression circuit.
9.12.6
Port 0 analog functions
The P89LPC915/916/917 incorporates two Analog Comparators. In order to give the
best analog function performance and to minimize power consumption, pins that are
being used for analog functions must have the digital outputs and digital inputs
disabled.
Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in Section 9.12.4 “Input-only configuration”.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On
any reset, the PT0AD bits default to logic 0s to enable digital functions.
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9.12.7
Additional port features
After power-up, all pins are in Input-Only mode. After power-up all I/O pins except
P1.5, may be configured by software.
• Pin P1.5 is input only.
• SCL/T0/P1.2 and SDA/INTO/P1.3 may only be configured to be either input-only or
open drain.
Every output on the P89LPC915/916/917 has been designed to sink typical LED
drive current. However, there is a maximum total output current for all ports which
must not be exceeded. Please refer to Table 13 “DC electrical characteristics” for
detailed specifications.
All port pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
9.13 Power monitoring functions
The P89LPC915/916/917 incorporates power monitoring functions designed to
prevent incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on detect and
Brownout detect.
9.13.1
Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however, it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If Brownout detection is enabled, the brownout condition occurs when VDD falls below
the brownout trip voltage, VBO (see Table 13 “DC electrical characteristics”), and is
negated when VDD rises above VBO. If the P89LPC915/916/917 device is to operate
with a power supply that can be below 2.7 V, BOE should be left in the
unprogrammed state so that the device can operate at 2.4 V, otherwise continuous
brownout reset may prevent the device from operating.
For correct activation of Brownout detect, the VDD rise and fall times must be
observed. Please see Table 13 “DC electrical characteristics” for specifications.
9.13.2
Power-on detection
The Power-on detect has a function similar to the Brownout detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.
9.14 Power reduction modes
The P89LPC915/916/917 supports three different power reduction modes. These
modes are Idle mode, Power-down mode, and total Power-down mode.
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9.14.1
Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.
9.14.2
Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC915/916/917 exits Power-down mode via any reset, or certain interrupts.
In Power-down mode, the power supply voltage may be reduced to the RAM
keep-alive voltage VRAM. This retains the RAM contents at the point where
Power-down mode was entered. SFR contents are not guaranteed after VDD has
been lowered to VRAM, therefore it is highly recommended to wake up the processor
via reset in this case. VDD must be raised to within the operating range before the
Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock and the
RTC is enabled.
9.14.3
Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
9.15 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables
the external reset input function on P1.5. When cleared, P1.5 may be used as an
input pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
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Reset can be triggered from the following sources:
• External reset pin (during power-up or if user configured via UCFG1. This option
must be used for an oscillator frequency above 12 MHz.)
•
•
•
•
•
Power-on detect
Brownout detect
Watchdog Timer
Software reset
UART break character detect reset.
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit
may be set:
• During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
• For any other reset, previously set flag bits that have not been cleared will remain
set.
9.16 Timers/counters 0 and 1
The P89LPC915/916/917 devices have two general purpose counter/timers which
are upward compatible with the standard 80C51 Timer 0 and Timer 1. An option to
automatically toggle the T0 pin upon timer overflow has been added. In addition an
option to toggle the T1 pin upon overflow has been added on the P89LPC917. In the
‘Timer’ function, the register is incremented every machine cycle. In the ‘Counter’
function, the register of Timer 0 is incremented in response to a 1-to-0 transition at its
external input pin. This external input is sampled once very machine cycle.
Timer 0 has five operating modes (modes 0, 1, 2, 3, and 6).
Timer 1 has four operating modes (modes 0, 1, 2, and 3), except on the P89LPC917
where Timer 1 also has mode 6. Modes 0, 1, and 2 are the same for both
Timers/Counters. Mode 3 is different.
9.16.1
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured
as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
9.16.2
Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
9.16.3
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload.
Mode 2 operation is the same for Timer 0 and Timer 1.
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9.16.4
Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When
Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
9.16.5
Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
9.16.6
Timer overflow toggle output
Timer 0 (and Timer 1 on the P89LPC917) can be configured to automatically toggle
the timer output pin, Tx, whenever a timer overflow occurs. The same device pin that
is used for the count input is also used for the timer toggle output. The port output will
be a logic 1 prior to the first timer overflow when this mode is turned on.
9.17 Real-Time clock/system timer
The P89LPC915/916/917 devices have a simple Real-Time clock that allows a user
to continue running an accurate timer while the rest of the device is powered-down.
The Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is
a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down
counter. When it reaches all logic 0s, the counter will be reloaded again and the
RTCF flag will be set.
The clock source for this counter can either be the CPU clock (CCLK) or the external
clock input, provided that the external clock input is not being used as the CPU clock.
If the external clock input is used as the CPU clock, then the RTC will use CCLK as its
clock source.
Only power-on reset will reset the Real-Time clock and its associated SFRs to the
default state.
9.18 UART
The P89LPC915/916/917 has an enhanced UART that is compatible with the
conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud
rate source. The P89LPC915/916/917 does include an independent Baud Rate
Generator. The baud rate can be selected from CCLK (divided by a constant),
Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud
rate generation, enhancements over the standard 80C51 UART include Framing
Error detection, automatic address recognition, selectable double buffering and
several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit
UART, 9-bit UART, and CCLK/32 or CCLK/16.
9.18.1
Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock
frequency.
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9.18.2
Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is
stored in RB8 in Special Function Register SCON. The baud rate is variable and is
determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 9.18.5 “Baud rate generator and selection”).
9.18.3
Mode 2
11 bits are transmitted (through TxD) or received (through RxD): start bit (logic 0),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When
data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of
logic 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8.
When data is received, the 9th data bit goes into RB8 in Special Function Register
SCON, while the stop bit is not saved. The baud rate is programmable to either 1⁄16 or
1⁄ of the CCLK frequency, as determined by the SMOD1 bit in PCON.
32
9.18.4
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact,
Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in
Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate
Generator (described in section Section 9.18.5 “Baud rate generator and selection”).
9.18.5
Baud rate generator and selection
The P89LPC915/916/917 has an independent Baud Rate Generator. The baud rate
is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs
which together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing
functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 13).
Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses CCLK.
Timer 1 Overflow
(PCLK-based)
SMOD1 = 1
¸2
SBRGS = 0
Baud Rate Modes 1 and 3
SMOD1 = 0
Baud Rate Generator
(CCLK-based)
SBRGS = 1
002aaa419
Fig 13. Baud rate sources for UART (Modes 1, 3).
9.18.6
Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is logic 1, framing errors can be made available in SCON.7, respectively. If
SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1
(SCON.7:6) are set up when SMOD0 is logic 0.
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9.18.7
Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device.
9.18.8
Double buffering
The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the first character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = 0).
9.18.9
Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
9.18.10
The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.
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9.19 I2C-bus serial interface
I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bi-directional data transfer between masters and slaves
• Multi master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer
• The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 14. The P89LPC915/916/917
device provides a byte-oriented I2C-bus interface that supports data transfers up to
400 kHz.
RP
RP
SDA
I2C-BUS
SCL
P1.3/SDA
P1.2/SCL
P89LPC915/916/917
OTHER DEVICE
WITH I2C-BUS
INTERFACE
OTHER DEVICE
WITH I2C-BUS
INTERFACE
002aaa834
Fig 14. I2C-bus configuration.
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8
I2ADR
ADDRESS REGISTER
INTERNAL BUS
P1.3
COMPARATOR
INPUT
FILTER
P1.3/SDA
SHIFT REGISTER
OUTPUT
STAGE
ACK
I2DAT
8
BIT COUNTER /
ARBITRATION &
SYNC LOGIC
INPUT
FILTER
P1.2/SCL
SERIAL CLOCK
GENERATOR
OUTPUT
STAGE
CCLK
TIMING
&
CONTROL
LOGIC
INTERRUPT
TIMER 1
OVERFLOW
P1.2
I2CON
I2SCLH
I2SCLL
CONTROL REGISTERS &
SCL DUTY CYCLE REGISTERS
8
STATUS BUS
I2STAT
STATUS
DECODER
STATUS REGISTER
8
002aaa421
Fig 15. I2C-bus serial interface block diagram.
9.20 Serial Peripheral Interface (SPI - P89LPC916)
The P89LPC916 provides another high-speed serial communication interface—the
SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with
two operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be
supported in either Master or 3.0 Mbit/s in Slave mode. It has a Transfer Completion
Flag and Write Collision Flag Protection.
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S
M
READ DATA BUFFER
DIVIDER
BY 4, 16, 64, 128
clock
SPI clock (master)
MSTR
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
SPR0
SPR1
CPOL
CPHA
MSTR
SPEN
SSIG
WCOL
SPI STATUS REGISTER
DORD
MSTR
SPEN
SPI CONTROL
SPIF
S
M
CLOCK LOGIC
SPR0
SPR1
SELECT
PIN CONTROL LOGIC
M
S
8-BIT SHIFT REGISTER
MISO
P2.3
SPEN
CPU clock
SPI CONTROL REGISTER
SPI
interrupt
request
internal
data
bus
002aaa497
Fig 16. SPI block diagram (P89LPC916).
The SPI interface has four pins: SPICLK, MOSI, MISO, and SS:
• SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and
flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal
is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port
functions.
• SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave
device uses its SS pin to determine whether it is selected.
Typical connections are shown in Figure 17, 18, and 19.
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9.20.1
Typical SPI configurations
Master
8-BIT SHIFT
REGISTER
Slave
MISO
MISO
MOSI
MOSI
SPICLK
SPI CLOCK
GENERATOR
8-BIT SHIFT
REGISTER
SPICLK
PORT
SS
002aaa435
Fig 17. SPI single master single slave configuration.
Master
8-BIT SHIFT
REGISTER
Slave
MISO
MISO
MOSI
MOSI
SPICLK
SPI CLOCK
GENERATOR
8-BIT SHIFT
REGISTER
SPICLK
port
SS
Slave
MISO
MOSI
8-BIT SHIFT
REGISTER
SPICLK
port
SS
002aaa437
Fig 18. SPI single master multiple slaves configuration.
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Master
8-BIT SHIFT
REGISTER
Slave
MISO
MISO
MOSI
MOSI
SPICLK
SPI CLOCK
GENERATOR
SS
8-BIT SHIFT
REGISTER
SPICLK
SS
SPI CLOCK
GENERATOR
002aaa499
Fig 19. SPI dual device configuration, where either can be a master or a slave.
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9.21 Analog comparators
Two analog comparators are provided on the P89LPC915/916/917. Input and output
options allow use of the comparators in a number of different configurations.
Comparator operation is such that the output is a logic 1 when the positive input is
greater than the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. Each comparator may be configured to
cause an interrupt when the output value changes. Comparator 1 may be output to a
port pin.
The overall connections to both comparators are shown in Figure 20. The
comparators function to VDD = 2.4 V.
When each comparator is first enabled, the comparator output and interrupt flag are
not guaranteed to be stable for 10 microseconds. The corresponding comparator
interrupt should not be enabled during that time, and the comparator interrupt flag
must be cleared before the interrupt is enabled in order to prevent an immediate
interrupt service.
CP1
Comparator 1
(P0.4) CIN1A
(P0.3) CIN1B
CO1
(P0.5) CMPREF
Change Detect
VREF
CMF1
CN1
Interrupt
Change Detect
CP2
Comparator 2
EC
CMF2
(P0.2) CIN2A
(P0.1) CIN2B
CMP2 (P0.0)
CO2
(P89LPC915/917)
OE2
002aaa835
CN2
Fig 20. Comparator input and output connections.
9.22 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to
as VREF, is 1.23 V ±10 %.
9.23 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag
is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt. The two comparators use one
common interrupt vector. If both comparators enable interrupts, after entering the
interrupt service routine, the user needs to read the flags to determine which
comparator caused the interrupt.
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Possible comparator configurations are shown in Figure 20.
9.24 Comparator and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down
mode.
If a comparator interrupt is enabled (except in Total Power-down mode), a change of
the comparator output state will generate an interrupt and wake up the processor. If
the comparator output to a pin is enabled, the pin should be configured in the
push-pull mode in order to obtain fast switching times while in Power-down mode.
The reason is that with the oscillator stopped, the temporary strong pull-up that
normally occurs during switching on a quasi-bidirectional port pin does not take
place.
Comparators consume power in Power-down and Idle modes, as well as in the
normal operating mode. This fact should be taken into account when system power
consumption is an issue. To minimize power consumption, the user can disable the
comparators via PCONA.5, or put the device in Total Power-down mode.
9.25 Keypad interrupt (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can
be used for bus address recognition or keypad recognition. The user can configure
the port via SFRs for different tasks.
The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)
is used to define a pattern that is compared to the value of Port 0. The Keypad
Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when
the condition is matched while the Keypad Interrupt function is active. An interrupt will
be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register
(KBCON) is used to define equal or not-equal for the comparison.
In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x
series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then
any key connected to Port 0 which is enabled by the KBMASK register will cause the
hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt
may be used to wake up the CPU from Idle or Power-down modes. This feature is
particularly useful in handheld, battery-powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
In order to set the flag and cause an interrupt, the pattern on Port 0 must be held
longer than six CCLKs.
9.26 Watchdog timer
The Watchdog timer causes a system reset when it underflows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer
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can only be reset by a power-on reset. When the Watchdog feature is disabled, it can
be used as an interval timer and may generate an interrupt. Figure 21 shows the
Watchdog timer in Watchdog mode. Feeding the Watchdog requires a two-byte
sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,
the Watchdog is disabled. The Watchdog timer has a time-out period that ranges
from a few µs to a few seconds. Please refer to the P89LPC915/916/917 User’s
Manual for more details.
WDL (C1H)
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
Watchdog
oscillator
PCLK
÷32
8-BIT DOWN
COUNTER
PRESCALER
RESET
see note (1)
SHADOW
REGISTER
FOR WDCON
CONTROL REGISTER
WDCON (A7H)
PRE2
PRE1
PRE0
–
–
WDRUN
WDTOF
WDCLK
002aaa423
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 21. Watchdog timer in Watchdog mode (WDTE = 1).
9.27 Additional features
9.27.1
Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or Watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
9.27.2
Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that
the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing
the AUXR1 register, without the possibility of inadvertently altering other bits in the
register.
9.28 Flash program memory
9.28.1
General description
The P89LPC915/916/917 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be erased, read, and written as bytes. The Sector and
Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The
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Chip Erase operation will erase the entire program memory. In-Circuit Programming
using standard commercial programmers is available. In addition, In-Application
Programming (IAP-Lite) and byte erase allows code memory to be used for
non-volatile data storage. On-chip erase and write timing generation contribute to a
user-friendly programming interface. The P89LPC915/916/917 Flash reliably stores
memory contents even after 100,000 erase and program cycles. The cell is designed
to optimize the erase and programming mechanisms. The P89LPC915/916/917 uses
VDD as the supply voltage to perform the Program/Erase algorithms.
9.28.2
Features
•
•
•
•
•
•
•
•
9.28.3
Programming and erase over the full operating voltage range.
Byte-erase allowing code memory to be used for data storage.
Read/Programming/Erase using ICP.
Any flash program operation in 4 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the Flash for each sector.
More than 100,000 minimum erase/program cycles for each byte.
10-year minimum data retention.
Flash organization
The P89LPC915/916/917 program memory consists of eight 256- byte sectors. Each
sector can be further divided into sixteen 16-byte pages. In addition to sector erase,
page erase, and byte erase, a 16-byte page register is included which allows from
1 to 16 bytes of a given page to be programmed at the same time, substantially
reducing overall programming time. In addition, erasing and reprogramming of
user-programmable configuration bytes including UCFG1, the Boot Status Bit, and
the Boot Vector is supported.
9.28.4
Flash programming and erasing
Different methods of erasing or programming of the Flash are available. The Flash
may be programmed or erased in the end-user application (IAP-Lite) under control of
the application’s firmware. Another option is to use the In-Circuit Programming (ICP)
mechanism. This ICP system provides for programming through a serial clock- serial
data interface using a commercially available EPROM programmer which supports
this device. This device does not provide for direct verification of code memory
contents. Instead this device provides a 32-bit CRC result on either a sector or the
entire 2 kB of user code space.
9.28.5
In-circuit programming (ICP)
In-Circuit Programming is performed without removing the microcontroller from the
system. The In-Circuit Programming facility consists of internal hardware resources
to facilitate remote programming of the P89LPC915/916/917 through a two-wire
serial interface. The Philips In-Circuit Programming facility has made in-circuit
programming in an embedded application, using commercially available
programmers, possible with a minimum of additional expense in components and
circuit board area. The ICP function uses five pins. Only a small connector (with VDD,
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VSS, RST, clock, and data signals) needs to be available to interface your application
to a commercial programmer in order to use this feature. Additional details may be
found in the P89LPC915/916/917 User’s Manual.
9.28.6
In-application programming (IAP-Lite)
In-Application Programming is performed in the application under the control of the
microcontroller’s firmware. The IAP-Lite facility consists of internal hardware
resources to facilitate programming and erasing. The Philips In-Application
Programming Lite has made in-application programming in an embedded application
possible without additional components. This is accomplished through the use of four
SFRs consisting of a control/status register, a data register, and two address
registers. Additional details may be found in the P89LPC915/916/917 User’s Manual.
9.28.7
Using flash as data storage
The Flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a
MOVC instruction is not allowed to read code memory contents of a secured sector).
Thus any byte in a non-secured sector may be used for non-volatile data storage.
9.28.8
User configuration bytes
Some user-configurable features of the P89LPC915/916/917 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the Flash byte UCFG1. Please see the
P89LPC915/916/917 User’s Manual for additional details.
9.28.9
User sector security bytes
There are eight User Sector Security Bytes, each corresponding to one sector.
Please see the P89LPC915/916/917 User’s Manual for additional details.
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10. Limiting values
Table 12: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Tamb(bias)
Min
Max
Unit
operating bias ambient temperature
−55
+125
°C
Tstg
storage temperature range
−65
+150
°C
Vn
voltage on any pin to VSS
−0.5
+5.5
V
IOH(I/O)
high-level output current per I/O pin
-
8
mA
IOL(I/O)
low-level output current per I/O pin
-
20
mA
II/O(tot)(max)
maximum total I/O current
-
120
mA
Ptot(pack)
total power dissipation per package
-
1.5
W
[1]
Conditions
based on package heat
transfer, not device power
consumption
The following applies to Limiting values:
a) Stresses above those listed under Table 12 may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any conditions other than those described in Table 13 “DC electrical characteristics”, Table 14 “AC
characteristics”and Table 15 “AC characteristics” of this specification are not implied.
b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
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Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
11. Static characteristics
Table 13: DC electrical characteristics
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C extended, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
power supply current,
operating
3.6 V; 12 MHz
[2]
-
7
13
mA
3.6 V; 18 MHz
[2]
-
11
16
mA
power supply current, Idle
mode
3.6 V; 12 MHz
[2]
-
3.6
4.8
mA
3.6 V; 18 MHz
[2]
-
4
6
mA
power supply current,
Power-down mode, voltage
comparators powered-down
3.6 V, industrial
[2]
-
45
70
µA
3.6 V, extended
[2]
-
-
150
µA
power supply current, total
Power-down mode
3.6 V, industrial
[2]
-
< 0.1
5
µA
3.6 V, extended
[2]
-
-
50
µA
(dVDD/dt)r VDD rise rate
-
-
2
mV/µs
(dVDD/dt)f
VDD fall rate
-
-
50
mV/µs
VRAM
RAM keep-alive voltage
1.5
-
-
V
Vth(HL)
negative-going threshold
voltage (Schmitt trigger input)
0.22VDD
0.4VDD
-
V
Vth(LH)
positive-going threshold
voltage (Schmitt trigger input)
-
0.6VDD
0.7VDD
V
Vhys
hysteresis voltage
-
0.2VDD
-
V
VOL
low-level output voltage,
all ports
IOL = 20 mA
-
0.6
1.0
V
IOL = 10 mA
-
0.3
0.5
V
IOL = 3.2 mA
-
0.2
0.3
V
IOH = −8 mA;
push-pull mode
VDD − 1
-
-
V
IOH = −3.2 mA;
push-pull mode
VDD − 0.7
VDD − 0.4
-
V
IOH = −20 µA;
quasi-bidirectional mode
VDD − 0.3
VDD − 0.2
-
V
IDD(oper)
IDD(idle)
IDD(PD)
IDD(TPD)
VOH
high-level output voltage,
all ports
input-ground capacitance
[3]
-
-
15
pF
IIL
logical 0 input current,
all ports
[4]
-
-
−80
µA
ILI
input leakage current, all ports VIN = VIL or VIH
[5]
-
-
± 10
µA
−30
-
−450
µA
10
-
30
kΩ
2.40
-
2.70
V
Cig
ITL
logical 1-to-0 transition
current, all ports
RRST
internal reset pull-up resistor
VBO
brownout trip voltage with
BOV = 1, BOPD = 0
VIN = 0.4 V
VIN = 2.0 V at
VDD = 3.6 V
[6][7]
2.4 V < VDD < 3.6 V
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9397 750 14397
Product data
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P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 13: DC electrical characteristics…continued
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C extended, unless otherwise specified.
Min
Typ[1]
Max
Unit
band gap reference voltage
1.11
1.23
1.34
V
band gap temperature
coefficient
-
10
20
ppm/
°C
Symbol
Parameter
VREF
TC(VREF)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Conditions
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
The IDD(oper), IDD(idle), and IDD(PD) specifications are measured using an external clock with the following functions disabled: comparators,
brownout detect, ADC, I2C-bus, UART, SPI, and Watchdog timer.
Pin capacitance is characterized but not tested.
Measured with port in quasi-bidirectional mode.
Measured with port in high-impedance mode.
Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups)
Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when VIN is approximately 2 V.
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9397 750 14397
Product data
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P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
12. Dynamic characteristics
Table 14: AC characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C extended, unless otherwise specified.[1]
Symbol
Parameter
fRCOSC
industrial
internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed extended
to ± 1 % at Tamb = 25 °C
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
fWDOSC
Conditions
Variable clock
fosc = 12 MHz
Unit
Min
Max
Min
Max
7.189
7.557
7.189
7.557
MHz
7.004
7.741
7.004
7.741
MHz
320
520
320
520
kHz
External clock input
fosc
oscillator frequency
VDD = 2.4 V to
3.6 V
0
12
-
-
MHz
tCLCL
clock cycle
see Figure 27
83
-
-
-
ns
fCLKP
CLKLP active frequency
0
8
-
-
MHz
tCHCX
high time
see Figure 27
22
tCLCL − tCLCX
22
-
ns
tCLCX
low time
see Figure 27
22
tCLCL − tCHCX
22
-
ns
tCLCH
rise time
see Figure 27
-
8
-
8
ns
tCHCL
fall time
see Figure 27
-
8
-
8
ns
glitch rejection, P1.5/RST pin
-
50
-
50
ns
signal acceptance, P1.5/RST pin
125
-
125
-
ns
glitch rejection, any pin except
P1.5/RST
-
15
-
15
ns
signal acceptance, any pin except
P1.5/RST
50
-
50
-
ns
Glitch filter
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
see Figure 26
16tCLCL
-
1333
-
ns
tQVXH
output data set-up to clock rising
edge
see Figure 26
13tCLCL
-
1083
-
ns
tXHQX
output data hold after clock rising
edge
see Figure 26
-
tCLCL + 20
-
103
ns
tXHDX
input data hold after clock rising
edge
see Figure 26
-
0
-
0
ns
tDVXH
input data valid to clock rising edge see Figure 26
150
-
150
-
ns
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Product data
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P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 14: AC characteristics…continued
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C extended, unless otherwise specified.[1]
Symbol
Parameter
Conditions
Variable clock
fosc = 12 MHz
Unit
Min
Max
Min
Max
0
CCLK⁄
6
0
2.0
MHz
-
CCLK⁄
4
-
-
MHz
SPI interface
fSPI
Operating frequency
2.0 MHz (Slave)
3.0 MHz (Master)
tSPICYC
tSPILEAD
Cycle time
see Figure 22,
23, 24, 25
2.0 MHz (Slave)
6⁄
CCLK
-
500
-
ns
3.0 MHz (Master)
4⁄
CCLK
-
-
-
ns
250
-
250
-
ns
250
-
250
-
ns
Master
2⁄
CCLK
-
340
-
ns
Slave
3⁄
CCLK
-
190
-
ns
Master
2⁄
CCLK
-
340
-
ns
Slave
3⁄
CCLK
-
190
-
ns
Enable lead time (Slave)
see Figure 24,
25
2.0 MHz
tSPILAG
Enable lag time (Slave)
see Figure 24,
25
2.0 MHz
tSPICLKH
tSPICLKL
SPICLK high time
SPICLK low time
see Figure 22,
23, 24, 25
see Figure 22,
23, 24, 25
tSPIDSU
Data set-up time (Master or Slave) see Figure 22,
23, 24, 25
100
-
100
-
ns
tSPIDH
Data hold time (Master or Slave)
see Figure 22,
23, 24, 25
100
-
100
-
ns
tSPIA
Access time (Slave)
see Figure 24,
25
0
120
0
120
ns
tSPIDIS
Disable time (Slave)
see Figure 24,
25
0
240
-
240
ns
2.0 MHz
0
240
-
240
ns
3.0 MHz
0
167
-
167
ns
0
-
0
-
ns
2.0 MHz
tSPIDV
tSPIOH
Enable to output data valid
Output data hold time
see Figure 22,
23, 24, 25
see Figure 22,
23, 24, 25
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Product data
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P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 14: AC characteristics…continued
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C extended, unless otherwise specified.[1]
Symbol
tSPIR
tSPIF
[1]
Parameter
Variable clock
fosc = 12 MHz
Min
Max
Min
Max
SPI outputs (SPICLK, MOSI,
MISO)
-
100
-
100
ns
SPI inputs (SPICLK, MOSI,
MISO, SS)
-
2000
-
2000
ns
SPI outputs (SPICLK, MOSI,
MISO)
-
100
-
100
ns
SPI inputs (SPICLK, MOSI,
MISO, SS)
-
2000
-
2000
ns
Rise time
Fall time
Conditions
Unit
see Figure 22,
23, 24, 25
see Figure 22,
23, 24, 25
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
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Product data
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P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 15: AC characteristics
VDD = 3.0 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C extended, unless otherwise specified.[1]
Symbol
fRCOSC
fWDOSC
Parameter
Conditions
Variable clock
fosc = 18 MHz
Min
Max
Min
Max
Unit
industrial
internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed extended
to ± 1 % at Tamb = 25 °C
7.189
7.557
7.189
7.557
MHz
7.004
7.741
7.004
7.741
MHz
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
320
520
320
520
kHz
0
18
-
-
MHz
see Figure 27
55
-
-
-
ns
External clock input
fosc
oscillator frequency
tCLCL
clock cycle
[1]
fCLKP
CLKLP active frequency
0
8
-
-
MHz
tCHCX
high time
see Figure 27
22
tCLCL − tCLCX
22
-
ns
tCLCX
low time
see Figure 27
22
tCLCL − tCHCX
22
-
ns
tCLCH
rise time
see Figure 27
-
5
-
5
ns
tCHCL
fall time
see Figure 27
-
5
-
5
ns
-
50
-
50
ns
Glitch filter
glitch rejection, P1.5/RST pin
signal acceptance, P1.5/RST pin
125
-
125
-
ns
glitch rejection, any pin except
P1.5/RST
-
15
-
15
ns
signal acceptance, any pin except
P1.5/RST
50
-
50
-
ns
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
see Figure 26
16tCLCL
-
888
-
ns
tQVXH
output data set-up to clock rising
edge
see Figure 26
13tCLCL
-
722
-
ns
tXHQX
output data hold after clock rising
edge
see Figure 26
-
tCLCL + 20
-
103
ns
tXHDX
input data hold after clock rising
edge
see Figure 26
-
0
-
0
ns
tDVXH
input data valid to clock rising edge see Figure 26
150
-
150
-
ns
0
CCLK⁄
6
0
3
MHz
-
CCLK⁄
4
-
4.5
MHz
CCLK
-
333
-
ns
CCLK
-
222
-
ns
SPI interface
fSPI
Operating frequency
3.0 MHz (Slave)
4.5 MHz (Master)
tSPICYC
Cycle time
see Figure 22,
23, 24, 25
3.0 MHz (Slave)
6⁄
4.5 MHz (Master)
4⁄
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Product data
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P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 15: AC characteristics…continued
VDD = 3.0 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C extended, unless otherwise specified.[1]
Symbol
tSPILEAD
Parameter
Variable clock
fosc = 18 MHz
Min
Max
Min
Max
250
-
250
-
ns
250
-
250
-
ns
Master
2⁄
CCLK
-
111
-
ns
Slave
3⁄
CCLK
-
167
-
ns
Master
2⁄
CCLK
-
111
-
ns
Slave
3⁄
CCLK
-
167
-
ns
Enable lead time (Slave)
Conditions
see Figure 24,
25
3.0 MHz
tSPILAG
Enable lag time (Slave)
tSPICLKH
SPICLK high time
see Figure 24,
25
3.0 MHz
tSPICLKL
SPICLK low time
Unit
see Figure 22,
23, 24, 25
see Figure 22,
23, 24, 25
tSPIDSU
Data set-up time (Master or Slave) see Figure 22,
23, 24, 25
100
-
100
-
ns
tSPIDH
Data hold time (Master or Slave)
see Figure 22,
23, 24, 25
100
-
100
-
ns
tSPIA
Access time (Slave)
see Figure 24,
25
0
80
0
80
ns
tSPIDIS
Disable time (Slave)
see Figure 24,
25
0
160
-
160
ns
3.0 MHz
0
160
-
160
ns
4.5 MHz
0
111
-
111
ns
0
-
0
-
ns
SPI outputs (SPICLK, MOSI,
MISO)
-
100
-
100
ns
SPI inputs (SPICLK, MOSI,
MISO, SS)
-
2000
-
2000
ns
3.0 MHz
tSPIDV
Enable to output data valid
see Figure 22,
23, 24, 25
tSPIOH
Output data hold time
see Figure 22,
23, 24, 25
tSPIR
Rise time
see Figure 22,
23, 24, 25
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9397 750 14397
Product data
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P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 15: AC characteristics…continued
VDD = 3.0 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C extended, unless otherwise specified.[1]
Symbol
tSPIF
[1]
[2]
Parameter
Conditions
Variable clock
fosc = 18 MHz
Min
Max
Min
Max
SPI outputs (SPICLK, MOSI,
MISO)
-
100
-
100
ns
SPI inputs (SPICLK, MOSI,
MISO, SS)
-
2000
-
2000
ns
Fall time
Unit
see Figure 22,
23, 24, 25
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the
minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
SS
tCLCL
tSPIF
tSPICLKH
SPICLK
(CPOL = 0)
(output)
tSPIF
tSPICLKL
tSPICLKL
tSPIR
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(output)
tSPIDSU
MISO
(input)
tSPIDH
tSPIDV
MOSI
(output)
LSB/MSB in
MSB/LSB in
tSPIOH
tSPIDV
tSPIR
tSPIF
Master MSB/LSB out
Master LSB/MSB out
002aaa156
Fig 22. SPI master timing (CPHA = 0).
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8-bit microcontrollers with accelerated two-clock 80C51 core
SS
tCLCL
tSPIF
tSPICLKL
SPICLK
(CPOL = 0)
(output)
tSPIR
tSPICLKH
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(output)
tSPIDSU
MISO
(input)
tSPIDH
LSB/MSB in
MSB/LSB in
tSPIDV
MOSI
(output)
tSPIDV
tSPIOH
tSPIDV
tSPIR
tSPIF
Master MSB/LSB out
Master LSB/MSB out
002aaa157
Fig 23. SPI master timing (CPHA = 1).
SS
tSPIR
tSPILEAD
tSPIF
tSPICLKH
SPICLK
(CPOL = 0)
(input)
tSPIF
tSPIR
tCLCL
tSPICLKL
tSPICLKL
tSPIR
tSPILAG
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(input)
tSPIOH
tSPIA
MISO
(output)
tSPIDV
MOSI
(input)
tSPIDH
tSPIDIS
tSPIDV
Slave MSB/LSB out
tSPIDSU
tSPIOH
tSPIOH
Slave LSB/MSB out
tSPIDSU
tSPIDSU
MSB/LSB in
Not defined
tSPIDH
LSB/MSB in
002aaa158
Fig 24. SPI slave timing (CPHA = 0).
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Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
SS
tSPIR
tSPILEAD
tSPIF
tSPICLKH
SPICLK
(CPOL = 0)
(input)
tSPIR
tCLCL
tSPIF
tSPICLKL
tSPICLKL
tSPIR
tSPILAG
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(input)
tSPIOH
tSPIOH
tSPIDV
tSPIOH
tSPIDV
tSPIDIS
tSPIDV
tSPIA
MISO
(output)
Not defined
Slave LSB/MSB out
Slave MSB/LSB out
tSPIDSU
MOSI
(input)
tSPIDH
tSPIDSU
tSPIDSU
MSB/LSB in
tSPIDH
LSB/MSB in
002aaa159
Fig 25. SPI slave timing (CPHA = 1).
tXLXL
Clock
tXHQX
tQVXH
Output Data
0
Write to SBUF
Input Data
1
2
3
4
5
6
7
Valid
Valid
Valid
Valid
Valid
Valid
tXHDX
tXHDV
Set TI
Valid
Valid
Clear RI
Set RI
002aaa425
Fig 26. Shift register mode timing.
VDD - 0.5 V
0.45 V
0.2 VDD + 0.9
0.2 VDD - 0.1 V
tCHCX
tCHCL
tCLCX
tCLCH
tC
002aaa416
Fig 27. External clock timing.
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Product data
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P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
13. Comparator electrical characteristics
Table 16: Comparator electrical characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial, unless otherwise specified.
Symbol
Parameter
VIO
VCR
CMRR
common mode rejection ratio
Conditions
Min
Typ
Max
offset voltage comparator inputs
-
-
± 20
mV
common mode range comparator inputs
0
-
VDD − 0.3
V
-
-
−50
dB
-
250
500
ns
[1]
response time
comparator enable to output valid
input leakage current, comparator
IIL
[1]
0 < VIN < VDD
Unit
-
-
10
µs
-
-
± 10
µA
This parameter is characterized, but not tested in production.
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Product data
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P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
14. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
SOT402-1
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 28. SOT402-1 (TSSOP14).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
68 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
SOT403-1
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 29. SOT403-1 (TSSOP16).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
69 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
15. Revision history
Table 17:
Revision history
Rev Date
04
20041217
CPCN
Description
-
Product data (9397 750 14397)
Modifications:
•
•
Added extended temperature device (P89LPC915HDH).
Added 18 MHz information.
03
20040701
-
Preliminary data (9397 750 13522)
02
20040512
-
Preliminary data (9397 750 13278)
01
20040408
-
Preliminary data (9397 750 12986)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Product data
Rev. 04 — 17 December 2004
70 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
16. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Disclaimers
19. Licenses
Purchase of Philips I2C components
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected]
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14397
Rev. 04 — 17 December 2004
71 of 72
P89LPC915/916/917
Philips Semiconductors
8-bit microcontrollers with accelerated two-clock 80C51 core
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
8
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
9.9.8
9.10
9.11
9.11.1
9.12
9.12.1
9.12.2
9.12.3
9.12.4
9.12.5
9.12.6
9.12.7
9.13
9.13.1
9.13.2
9.14
9.14.1
9.14.2
9.14.3
9.15
9.16
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Product comparison . . . . . . . . . . . . . . . . . . . . . . . . . 16
Special function registers. . . . . . . . . . . . . . . . . . . . . 16
Functional description . . . . . . . . . . . . . . . . . . . . . . . 29
Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Clock definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 29
Clock output (P89LPC917) . . . . . . . . . . . . . . . . . . . 29
On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 29
Watchdog oscillator option . . . . . . . . . . . . . . . . . . . . 30
External clock input option . . . . . . . . . . . . . . . . . . . . 30
CPU Clock (CCLK) wake-up delay. . . . . . . . . . . . . . 30
CPU Clock (CCLK) modification: DIVM register . . . 30
Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General description . . . . . . . . . . . . . . . . . . . . . . . . . 32
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
A/D operating modes . . . . . . . . . . . . . . . . . . . . . . . . 33
Conversion start modes . . . . . . . . . . . . . . . . . . . . . . 34
Boundary limits interrupt . . . . . . . . . . . . . . . . . . . . . 35
DAC output to a port pin with high output impedance 35
Clock divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power-down and Idle mode . . . . . . . . . . . . . . . . . . . 35
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
External interrupt inputs . . . . . . . . . . . . . . . . . . . . . . 36
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Quasi-bidirectional output configuration. . . . . . . . . . 38
Open-drain output configuration. . . . . . . . . . . . . . . . 39
Input-only configuration . . . . . . . . . . . . . . . . . . . . . . 39
Push-pull output configuration . . . . . . . . . . . . . . . . . 39
Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 39
Additional port features . . . . . . . . . . . . . . . . . . . . . . 40
Power monitoring functions . . . . . . . . . . . . . . . . . . . 40
Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 40
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Total Power-down mode . . . . . . . . . . . . . . . . . . . . . . 41
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 42
© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 17 December 2004
Document order number: 9397 750 14397
9.16.1
9.16.2
9.16.3
9.16.4
9.16.5
9.16.6
9.17
9.18
9.18.1
9.18.2
9.18.3
9.18.4
9.18.5
9.18.6
9.18.7
9.18.8
9.18.9
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Timer overflow toggle output. . . . . . . . . . . . . . . . . . . 43
Real-Time clock/system timer. . . . . . . . . . . . . . . . . . 43
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Baud rate generator and selection . . . . . . . . . . . . . . 44
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Transmit interrupts with double buffering
enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . 45
9.18.10
The 9th bit (bit 8) in double buffering (Modes 1, 2 and
3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.19
I2C-bus serial interface . . . . . . . . . . . . . . . . . . . . . . . 46
9.20
Serial Peripheral Interface (SPI - P89LPC916). . . . . 47
9.20.1
Typical SPI configurations. . . . . . . . . . . . . . . . . . . . . 49
9.21
Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.22
Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 51
9.23
Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 51
9.24
Comparator and power reduction modes . . . . . . . . . 52
9.25
Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 52
9.26
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.27
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.27.1
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.27.2
Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.28
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 53
9.28.1
General description. . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.28.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.28.3
Flash organization . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.28.4
Flash programming and erasing . . . . . . . . . . . . . . . . 54
9.28.5
In-circuit programming (ICP). . . . . . . . . . . . . . . . . . . 54
9.28.6
In-application programming (IAP-Lite) . . . . . . . . . . . 55
9.28.7
Using flash as data storage . . . . . . . . . . . . . . . . . . . 55
9.28.8
User configuration bytes . . . . . . . . . . . . . . . . . . . . . . 55
9.28.9
User sector security bytes . . . . . . . . . . . . . . . . . . . . 55
10
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11
Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 57
12
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 59
13
Comparator electrical characteristics . . . . . . . . . . . 67
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
19
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71