TDA8950 2 × 150 W class-D power amplifier Rev. 01 — 9 September 2008 Preliminary data sheet 1. General description The TDA8950 is a high efficiency class-D audio power amplifier. The typical output power is 2 × 150 W with a speaker load impedance of 4 Ω. The TDA8950 is available in the HSOP24 power package and DBS23P power package. The amplifier operates over a wide supply voltage range from ±12.5 V to ±40 V and consumes a low quiescent current. 2. Features n Pin compatible with TDA8920B for both HSOP24 and DBS23P packages n Symmetrical high operating supply voltage range from ±12.5 V to ±40 V n Stereo full differential inputs, usable as stereo Single-Ended (SE) or mono Bridge-Tied Load (BTL) amplifier n High output power at typical applications: u SE 2 × 150 W, RL = 4 Ω (VP = ±37 V) u SE 2 × 170 W, RL = 4 Ω (VP = ±39 V) u SE 2 × 100 W, RL = 6 Ω (VP = ±37 V) u BTL 1 × 300 W, RL = 8 Ω (VP = ±37 V) n Low noise in BTL due to BD-modulation n Smooth pop noise-free start-up and switch down n Zero dead time Pulse Width Modulation (PWM) output switching n Fixed frequency n Internal or external clock switching frequency n High efficiency n Low quiescent current n Advanced protection strategy: voltage protection and output current limiting n Thermal foldback n Fixed gain of 30 dB in SE and 36 dB in BTL n Full short-circuit proof across load 3. Applications n n n n DVD Mini and micro receiver Home Theater In A Box (HTIAB) system High power speaker system TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit ±12.5 ±35 ±40 V General, VP = ±35 V VP supply voltage VP(ovp) overvoltage protection supply voltage non-operating; VDD − VSS 85 - 90 V Iq(tot) total quiescent current Operating mode; no load; no filter; no RC-snubber network connected - 50 75 mA RL = 4 Ω; THD = 10 %; VP = ±39 V - 170 - W RL = 4 Ω; THD = 10 %; VP = ±37 V - 150 - W RL = 6 Ω; THD = 10 %; VP = ±37 V - 100 - W - 300 - W Stereo single-ended configuration Po output power Mono bridge-tied load configuration Po output power RL = 8 Ω; THD = 10 %; VP = ±37 V 5. Ordering information Table 2. Ordering information Type number Package Name Description TDA8950J DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 TDA8950TH HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height Version TDA8950_1 Preliminary data sheet SOT566-3 © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 2 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 6. Block diagram VDDA 3 (20) IN1M IN1P n.c. OSC MODE SGND n.c. 10 (4) VDDP2 STABI PROT 18 (12) 13 (7) 23 (16) IN2M 14 (8) 15 (9) BOOT1 9 (3) PWM MODULATOR INPUT STAGE 8 (2) SWITCH1 CONTROL AND HANDSHAKE mute 11 (5) DRIVER HIGH 16 (10) OUT1 DRIVER LOW STABI VSSP1 7 (1) 6 (23) OSCILLATOR MANAGER MODE TEMPERATURE SENSOR CURRENT PROTECTION VOLTAGE PROTECTION TDA8950TH (TDA8950J) VDDP2 22 (15) BOOT2 2 (19) mute IN2P VDDP1 CONTROL SWITCH2 AND HANDSHAKE 5 (22) 4 (21) INPUT STAGE 1 (18) VSSA PWM MODULATOR 12 (6) n.c. 24 (17) VSSD 19 (-) n.c. DRIVER HIGH 21 (14) OUT2 DRIVER LOW 17 (11) VSSP1 20 (13) 001aah653 VSSP2 The pin numbers in parenthesis refer to type number TDA8950J. Fig 1. Block diagram TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 3 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 7. Pinning information 7.1 Pinning OSC 1 IN1P 2 IN1M 3 n.c. 4 n.c. 5 n.c. 6 PROT 7 VDDP1 8 BOOT1 9 OUT1 10 VSSP1 11 VSSD 24 1 VSSA STABI 12 VDDP2 23 2 SGND VSSP2 13 BOOT2 22 3 VDDA OUT2 21 4 IN2M BOOT2 15 VSSP2 20 5 IN2P VDDP2 16 n.c. 19 6 MODE 7 OSC VSSA 18 8 IN1P SGND 19 9 IN1M VDDA 20 STABI 18 TDA8950TH VSSP1 17 OUT1 16 TDA8950J OUT2 14 VSSD 17 BOOT1 15 10 n.c. VDDP1 14 11 n.c. IN2P 22 PROT 13 12 n.c. MODE 23 IN2M 21 001aah654 Fig 2. Pin configuration TDA8950TH 001aah655 Fig 3. Pin configuration TDA8950J TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 4 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 7.2 Pin description Table 3. Pin description Symbol Pin Description TDA8950TH TDA8950J VSSA 1 18 negative analog supply voltage SGND 2 19 signal ground VDDA 3 20 positive analog supply voltage IN2M 4 21 negative audio input for channel 2 IN2P 5 22 positive audio input for channel 2 MODE 6 23 mode selection input: Standby, Mute or Operating mode OSC 7 1 oscillator frequency adjustment or tracking input IN1P 8 2 positive audio input for channel 1 IN1M 9 3 negative audio input for channel 1 n.c. 10 4 not connected n.c. 11 5 not connected n.c. 12 6 not connected PROT 13 7 decoupling capacitor for protection (OCP) VDDP1 14 8 positive power supply voltage for channel 1 BOOT1 15 9 bootstrap capacitor for channel 1 OUT1 16 10 PWM output from channel 1 VSSP1 17 11 negative power supply voltage for channel 1 STABI 18 12 decoupling of internal stabilizer for logic supply n.c. 19 - not connected VSSP2 20 13 negative power supply voltage for channel 2 OUT2 21 14 PWM output from channel 2 BOOT2 22 15 bootstrap capacitor for channel 2 VDDP2 23 16 positive power supply voltage for channel 2 VSSD 24 17 negative digital supply voltage 8. Functional description 8.1 General The TDA8950 is a two-channel audio power amplifier using class-D technology. The audio input signal is converted into a digital pulse width modulated signal via an analog input stage and PWM modulator, see Figure 1. To enable the output power transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. In this way a level shift is performed from the low power digital PWM signal (at logic levels) to a high power PWM signal that switches between the main supply lines. A 2nd-order low-pass filter converts the PWM signal to an analog audio signal across the loudspeakers. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 5 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier The TDA8950 one-chip class-D amplifier contains high power switches, drivers, timing and handshaking between the power switches and some control logic. Also an advanced protection strategy is implemented which contains several voltage protections, temperature protections and a maximum current protection to secure maximum system robustness. The two audio channels of the TDA8950 each contain a PWM modulator, an analog feedback loop and a differential input stage. It also contains circuits common to both channels such as the oscillator, all reference sources, the mode interface and a digital timing manager. The TDA8950 contains two independent amplifier channels with high output power, high efficiency, low distortion and low quiescent current. The amplifier channels can be connected in the following configurations: • Mono Bridge-Tied Load (BTL) amplifier • Stereo Single-Ended (SE) amplifiers The amplifier system can be switched to one of three operating modes by pin MODE: • Standby mode; with a very low supply current • Mute mode; the amplifiers are operational, but the audio signal at the output is suppressed by disabling the VI-converter input stages • Operating mode; the amplifiers are fully operational To ensure pop noise-free start-up, the DC output offset voltage is applied gradually to the output at a level between Mute mode and Operating mode levels. The bias current setting of the VI converters is related to the voltage on pin MODE; in Mute mode the bias current setting of the VI converters is zero (VI converters disabled) and in Operating mode the bias current is at maximum. The time constant required to apply the DC output offset voltage gradually between Mute and Operating mode levels can be generated via an RC-network on pin MODE. An example of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor C is left out of the application, the voltage on pin MODE will be applied with a much smaller time-constant, which might result in audible pop noises during start-up (depending on DC output offset voltage and loudspeaker used). +5 V standby/ mute R MODE pin R C mute/on SGND 001aab172 Fig 4. Example of mode selection circuit TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 6 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier In order to fully charge the coupling capacitors at the inputs, the amplifier will remain automatically in the Mute mode before switching to the Operating mode. A complete overview of the start-up timing is given in Figure 5. audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.2 V mute 2.2 V < VMODE < 3 V 0 V (SGND) standby > 350 ms 100 ms time 50 ms audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.2 V mute 2.2 V < VMODE < 3 V 0 V (SGND) standby > 350 ms 100 ms 50 ms time 001aah657 (1) First 1⁄4 pulse down. Upper diagram: When switching from standby to mute, there is a delay of approximately 100 ms before the output starts switching. The audio signal is available after VMODE has been set to operating, but not earlier than 150 ms after switching to mute. For pop noise-free start-up it is recommended that the time constant applied to pin MODE is at least 350 ms for the transition between mute and operating. Lower diagram: When switching directly from standby to operating, there is a first delay of 100 ms before the outputs starts switching. The audio signal is available after a second delay of 50 ms. For pop noise-free start-up it is recommended that the time constant applied to pin MODE is at least 500 ms for the transition between standby and operating. Fig 5. Timing on mode selection input TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 7 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 8.2 Pulse width modulation frequency The output signal of the amplifier is a PWM signal with a carrier frequency that typically lies between 300 kHz and 400 kHz. Using a 2nd-order LC demodulation filter in the application results in an analog audio signal across the loudspeaker. The carrier frequency is determined by an external resistor ROSC, connected between pin OSC and pin VSSA. An optimal setting for the carrier frequency is between 300 kHz and 400 kHz. Using an external resistor of 30 kΩ on pin OSC, the carrier frequency is set to 345 kHz. For more details see Table 8. If two or more class-D amplifiers are used in the same audio application, it is recommended that all devices operate at the same switching frequency by using an external clock circuit. Due to an internal clock divider: • The external applied clock frequency must have the double frequency of the output PWM frequency. • The duty cycle of the external clock is not critical for product performance. 8.3 Protections The following protections are included in TDA8950: • Thermal protections: – Thermal FoldBack (TFB) – OverTemperature Protection (OTP) • OverCurrent Protection (OCP, diagnostic via pin PROT) • Window Protection (WP) • Supply voltage protections: – UnderVoltage Protection (UVP) – OverVoltage Protection (OVP) – UnBalance Protection (UBP) The reaction of the device to the different fault conditions differs per protection. 8.3.1 Thermal protection In the TDA8950 an advanced thermal protection strategy is implemented. It consists of a TFB function that gradually reduces the out put power within a certain temperature range. When temperature is still rising an OTP is implemented which shuts down the device completely. 8.3.1.1 Thermal FoldBack (TFB) If the junction temperature Tj exceeds a defined threshold value, the gain is gradually reduced. This will result in a smaller output signal and less dissipation. Eventually the temperature will stabilize. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 8 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier TFB is specified at the temperature value Tact(th_fold) where the closed loop voltage gain is reduced with 6 dB. The range of the TFB is: Tact(th_fold) − 5 °C < Tact(th_fold) < Tact(th_prot). For the TDA8950 the value of Tact(th_fold) is about +153 °C. For more details see: Table 7. 8.3.1.2 OverTemperature Protection (OTP) If, despite the TFB function, the junction temperature Tj of the TDA8950 continues rising and exceeds the threshold Tact(th_prot) the amplifier will shutdown immediately. The amplifier resumes switching approximately 100 ms after the temperature drops below Tact(th_prot). In Figure 6 the thermal behavior is visualized. Gain (dB) 30 dB 24 dB 0 dB (Tact(th_fold) − 5°C) 1 Tact(th_prot) Tact(th_fold) 2 Tj (°C) 3 001aah656 (1) Duty cycle of PWM output modulated according audio input signal. (2) Duty cycle of PWM output reduced due to TFB. (3) Amplifier is switched off due to OTP. Fig 6. Behavior of TFB and OTP 8.3.2 OverCurrent Protection (OCP) If a short-circuit is applied to one of the demodulated outputs of the amplifier, the OCP will detect this. If the output current exceeds the maximum of 9.2 A, it is automatically limited to its maximum value by the OCP protection circuit. The amplifier outputs remain switching (the amplifier is NOT shut-down completely). If the active current limiting continues longer than time τ, the TDA8950 shuts down. Activation of current limiting and the triggering of the OCP are observed at pin PROT. The amplifier can distinguish between an impedance drop of the loudspeaker and a low-ohmic short-circuit across the load. In the TDA8950 the impedance threshold (Zth) depends on the supply voltage used. When a short-circuit is made across the load, causing the impedance to drop below the threshold level (<Zth), the amplifier is switched off completely and, after a time of 100 ms, it will try to restart. If the short-circuit condition is still present after this time, the cycle will be repeated. The average dissipation will be low because of this low duty cycle. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 9 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier Should there be an impedance drop (e.g. due to dynamic behavior of the loudspeaker) the same protection will be activated. The maximum output current will again be limited to 9.2 A, but the amplifier will not switch-off completely (thus preventing audio holes from occurring). The result will be a clipping output signal. See Section 13.7 for more information on this maximum output current limiting feature. 8.3.3 Window Protection (WP) The WP checks the conditions at the output terminals of the power stage and is activated: • During the start-up sequence, when pin MODE is switched from standby to mute. In the event of a short-circuit at one of the output terminals to pin VDDPn or pin VSSPn the start-up procedure is interrupted and the TDA8950 waits until the short-circuit to the supply lines has been removed. Because the test is done before enabling the power stages, no large currents will flow in an event of short-circuit. • When the amplifier is completely shut-down due to activation of the OCP because a short-circuit to one of the supply lines is made, then during restart (after 100 ms) the WP will be activated. As a result the amplifier will not start-up until the short-circuit to the supply lines is removed. 8.3.4 Supply voltage protections If the supply voltage drops below minimum supply voltage, the UVP circuit is activated and the system will shutdown correctly. If the internal clock is used, this switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level, the system is restarted again after 100 ms. If the supply voltage exceeds maximum supply voltage, the OVP circuit is activated and the power stages will shutdown. When the supply voltage drops below the threshold level, the system is restarted again after 100 ms. An additional UBP circuit compares the positive analog (voltage on pin VDDA) and the negative analog (voltage on pin VSSA) supply voltage and is triggered if the voltage difference exceeds a factor of two. When the supply voltage difference drops below the threshold level, the system is restarted again after 100 ms. Example: With a symmetrical supply of ±30 V, the protection circuit will be triggered if the unbalance exceeds approximately 15 V. See Section 13.7. In Table 4 an overview is given of all protections and their respective effects on the output signal. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 10 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier Table 4. Overview of TDA8950 protections Protection name Complete shutdown Restart directly Restart after 100 ms Pin PROT detection TFB[1] N N N N OTP Y N Y N OCP Y[2] N[2] Y[2] Y WP N[3] Y N N UVP Y N Y N OVP Y N Y N UBP Y N Y N [1] Amplifier gain will depend on junction temperature and heatsink size. [2] Only complete shutdown of amplifier if short-circuit impedance is below threshold of 1 Ω. In all other cases current limiting results in clipping of the output signal. [3] Fault condition detected during (every) transition between standby-to-mute and during restart after activation of OCP (short-circuit to one of the supply lines). 8.4 Differential audio inputs For a high common mode rejection ratio and a maximum of flexibility in the application, the audio inputs are fully differential. There are two possibilities: • For stereo operation it is advised to use the inputs in anti phase and also to connect the speakers in anti phase (to avoid acoustical phase differences). This construction has several advantages: – The peak current in the power supply is minimized – The supply pumping effect is minimized, especially at low audio frequencies • For mono BTL operation it is required that the inputs are connected in anti parallel. The output of one of the channels is inverted and the speaker load is now connected between the two outputs of the TDA8950. In principle the output power to the speaker can be significantly boosted to two times the output power in single ended stereo. The input configuration for a mono BTL application is illustrated in Figure 7. OUT1 IN1P IN1M Vin SGND IN2P IN2M OUT2 power stage mbl466 Fig 7. Input configuration for mono BTL application TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 11 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VP supply voltage non-operating mode; VDD − VSS - 90 V IORM repetitive peak output current maximum output current limiting 9.2 - A Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 150 °C VMODE voltage on pin MODE 0 6 V VOSC voltage on pin OSC 0 SGND V +6 VI input voltage −5 +5 V VPROT voltage on pin PROT referenced to voltage on pin VSSD 0 12 V Vesd electrostatic discharge voltage Human Body Model (HBM); pin VSSP1 with respect to other pins −1800 +1800 V HBM; all other pins −2000 +2000 V Machine Model (MM); all pins −200 +200 V Charged Device Model (CDM) −500 +500 V Operating mode; no load; no filter; no RC-snubber network connected - 75 mA Iq(tot) referenced to SGND referenced to SGND; pin IN1P; IN1M; IN2P and IN2M total quiescent current 10. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient in free air Rth(j-c) thermal resistance from junction to case TDA8950_1 Preliminary data sheet Typ Unit 40 K/W 1.1 K/W © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 12 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 11. Static characteristics Table 7. Static characteristics VP = ±35 V; fosc = 345 kHz; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply ±12.5 ±35 ±40 V 85 - 90 V undervoltage protection supply voltage VDD − VSS 20 - 25 V Iq(tot) total quiescent current - 50 75 mA Istb standby current - 480 600 µA [2] 0 - 6.0 V Standby mode [2][3] 0 - 0.8 V Mute mode [2][3] 2.2 - 3.0 V Operating mode [2][3] 4.2 - 6.0 V - 110 150 µA [2] - 0 - V - - ±15 mV [4] - - ±150 mV - - ±21 mV - - ±210 mV 9.3 9.8 10.3 V - 154 - °C - 153 - °C [1] VP supply voltage VP(ovp) overvoltage protection supply voltage VP(uvp) non-operating; VDD − VSS Operating mode; no load; no filter; no RC-snubber network connected Mode select input; pin MODE VMODE voltage on pin MODE referenced to SGND input current II VI = 5.5 V Audio inputs; pins IN1M, IN1P, IN2P and IN2M input voltage VI DC input Amplifier outputs; pins OUT1 and OUT2 VO(offset) output offset voltage SE; mute SE; operating BTL; mute BTL; operating [4] Stabilizer output; pin STABI VO(STABI) output voltage on pin STABI mute and operating; with respect to VSSP1 Temperature protection Tact(th_prot) thermal protection activation temperature Tact(th_fold) thermal foldback activation temperature closed loop SE voltage gain reduced with 6 dB [5] [1] The circuit is DC adjusted at VP = ±12.5 V to ±42.5 V. [2] With respect to SGND (0 V). [3] The transition between Standby and Mute mode has hysteresis, while the slope of the transition between Mute and Operating mode is determined by the time-constant of the RC-network on pin MODE; see Figure 8. [4] DC output offset voltage is gradually applied to the output during the transition between the Mute and Operating modes. The slope caused by any DC output offset is determined by the time-constant of the RC-network on pin MODE. [5] At a junction temperature of approximately Tact(th_fold) − 5 °C the gain reduction will commence and at a junction temperature of approximately Tact(th_prot) the amplifier switches off. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 13 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier slope is directly related to the time-constant of the RC network on the MODE pin VO (V) VO(offset)(on) Standby Mute On VO(offset)(mute) 0 0.8 2.2 3.0 4.2 5.5 VMODE (V) coa021 Fig 8. Behavior of mode selection pin MODE 12. Dynamic characteristics 12.1 Switching characteristics Table 8. Dynamic characteristics VP = ±35 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ROSC = 30.0 kΩ 325 345 365 kHz 250 - 450 kHz Internal oscillator fosc(typ) typical oscillator frequency fosc oscillator frequency External oscillator or frequency tracking VOSC voltage on pin OSC SGND + 4.5 SGND + 5 Vtrip(OSC) trip voltage on pin OSC ftrack [1] tracking frequency - SGND + 2.5 - V 250 - kHz 450 When using an external oscillator, the fosc(ext) frequency (500 kHz minimum, 900 kHz maximum) will result in a PWM frequency ftrack (250 kHz minimum, 450 kHz maximum) due to the internal clock divider. See Section 8.2. TDA8950_1 Preliminary data sheet [1] SGND + 6 V © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 14 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 12.2 Stereo and dual SE application characteristics Table 9. Dynamic characteristics VP = ±35 V; RL = 4 Ω; fi = 1 kHz; fosc = 345 kHz; RsL < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified. Symbol Po Parameter Conditions Min Typ Max Unit output power L = 22 µH; C = 680 nF; Tj = 85 °C RL = 4 Ω; THD = 0.5 %; VP = ±37 V - 100 - W RL = 4 Ω; THD = 10 %; VP = ±37 V - 150 - W RL = 6 Ω; THD = 10 %; VP = ±37 V - 100 - W [2] RL = 4 Ω; THD = 10 %; VP = ±39 V THD total harmonic distortion Gv(cl) closed-loop voltage gain SVRR supply voltage ripple rejection - 170 - W Po = 1 W; fi = 1 kHz [3] - 0.05 - % Po = 1 W; fi = 6 kHz [3] - 0.05 - % 29 30 31 dB between pin VDDPn and SGND operating; fi = 100 Hz [4] - 90 - dB operating; fi = 1 kHz [4] - 70 - dB mute; fi = 100 Hz [4] - 75 - dB standby; fi = 100 Hz [4] - 120 - dB operating; fi = 100 Hz [4] - 80 - dB operating; fi = 1 kHz [4] - 60 - dB mute; fi = 100 Hz [4] - 80 - dB standby; fi = 100 Hz [4] between pin VSSPn and SGND Zi input impedance between the input pins and SGND Vn(o) output noise voltage operating; Rs = 0 Ω mute αcs channel separation |∆Gv| voltage gain difference - 115 - dB 45 63 - kΩ [5] - 160 - µV [6] - 85 - µV [7] - 70 - dB - - 1 dB - 75 - dB αmute mute attenuation fi = 1 kHz; Vi = 2 V (RMS) CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) - 75 - dB ηpo output power efficiency SE, RL = 4 Ω - 88 - % SE, RL = 6 Ω - 90 - [8] BTL, RL = 8 Ω RDSon(hs) RDSon(ls) - 88 - % high-side drain-source on-state resistance [9] - 200 - mΩ low-side drain-source on-state resistance [9] - 190 - mΩ [1] RsL is the series resistance of inductor of low-pass LC filter in the application. [2] Output power is measured indirectly; based on RDSon measurement. See also Section 13.3. [3] THD is measured in a bandwidth of 22 Hz to 20 kHz, using AES17 20 kHz brickwall filter. Maximum limit is not guaranteed100 % tested. [4] Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω. Measured independently between VDDPn and SGND and between VSSPn and SGND. [5] B = 22 Hz to 20 kHz, using AES17 20 kHz brickwall filter. [6] B = 22 Hz to 22 kHz, using AES17 20 kHz brickwall filter; independent of Rs. [7] Po = 1 W; Rs = 0 Ω; fi = 1 kHz. [8] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz. [9] Leads and bond wires included. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 15 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 12.3 Mono BTL application characteristics Table 10. Dynamic characteristics VP = ±35 V; RL = 8 Ω; fi = 1 kHz; fosc = 345 kHz; RsL < 0.1 Ω [1]; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions output power Po Min Typ Max Unit THD = 10 %; VP = ±39 V - 340 - W THD = 10 %; VP = ±37 V - 300 - W L = 22 µH; C = 680 nF; Tj = 85 °C; RL = 8 Ω [2] THD = 0.5 %; VP = ±37 V THD total harmonic distortion Gv(cl) closed-loop voltage gain SVRR supply voltage ripple rejection - 200 - W Po = 1 W; fi = 1 kHz [3] - 0.05 - % Po = 1 W; fi = 6 kHz [3] - 0.05 - % - 36 - dB between pin VDDPn and SGND operating; fi = 100 Hz [4] - 80 - dB operating; fi = 1 kHz [4] - 80 - dB mute; fi = 100 Hz [4] - 95 - dB standby; fi = 100 Hz [4] - 120 - dB operating; fi = 100 Hz [4] - 75 - dB operating; fi = 1 kHz [4] - 75 - dB mute; fi = 100 Hz [4] - 90 - dB standby; fi = 100 Hz [4] between pin VSSPn and SGND Zi input impedance measured between the input pins and SGND Vn(o) output noise voltage operating; Rs = 0 Ω 130 - dB 63 - kΩ [5] - 190 - µV - 45 - µV - 82 - dB - 75 - dB mute [6] αmute mute attenuation fi = 1 kHz; Vi = 2 V (RMS) [7] CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) [1] RsL is the series resistance of inductor of low-pass LC filter in the application. [2] Output power is measured indirectly; based on RDSon measurement. See also Section 13.3. [3] Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, using an AES17 20 kHz brickwall filter. Maximum limit is guaranteed but may not be 100 % tested. [4] Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω. [5] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall filter. Low noise due to BD modulation. [6] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall filter; independent of Rs. [7] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz. TDA8950_1 Preliminary data sheet 45 © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 16 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 13. Application information 13.1 Mono BTL application When using the power amplifier in a mono BTL application the inputs of both channels must be connected in parallel and the phase of one of the inputs must be inverted (see Figure 7). In principle the loudspeaker can be connected between the outputs of the two single-ended demodulation filters. 13.2 Pin MODE For pop noise-free start-up, an RC time-constant must be applied on pin MODE. The bias-current setting of the VI-converter input is directly related to the voltage on pin MODE. In turn the bias-current setting of the VI converters is directly related to the DC output offset voltage. Thus a slow dV/dt on pin MODE results in a slow dV/dt for the DC output offset voltage, resulting in pop noise-free start-up. A time-constant of 500 ms is sufficient to guarantee pop noise-free start-up (see also Figure 4, 5 and 8). 13.3 Output power estimation 13.3.1 SE Maximum output power: P o ( 0.5% ) 2 RL ----------------------------------------------------- × V P × ( 1 – t min × 0.5 f osc ) R L + R DSon ( hs ) + R sL = ---------------------------------------------------------------------------------------------------------------------------------2R L (1) Maximum current internally limited to 9.2 A: V P × ( 1 – t min × 0.5 f osc ) I o ( peak ) = -------------------------------------------------------------R L + R DSon ( hs ) + R sL (2) Variables: • • • • • • • RL: load impedance RsL: series impedance of the filter coil RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) fosc: oscillator frequency tmin: minimum pulse width (typical 150 ns, temp. dependent) VP: single-sided supply voltage (or 0.5 × (VDD + |VSS|)) Po(0.5 %): output power at the onset of clipping Note that Io(peak) should be below 9.2 A (Section 8.3.2). Io(peak)M is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and voltage drop over the coil. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 17 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 13.3.2 Bridge-Tied Load (BTL) Maximum output power: P o ( 0.5% ) 2 RL ------------------------------------------------------------------ × 2V P × ( 1 – t min × 0.5 f osc ) R L + R DSon ( hs ) + R dson ( ls ) = -------------------------------------------------------------------------------------------------------------------------------------------------2R L (3) Maximum current internally limited to 9.2 A: 2V P × ( 1 – t min × 0.5 f osc ) I o ( peak ) = ------------------------------------------------------------------------------------------R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R sL (4) Variables: • • • • • • • • RL: load impedance RsL: series impedance of the filter coil RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) RDSon(ls): low-side RDSson of power stage output DMOS (temperature. dependent) fosc: oscillator frequency tmin: minimum pulse width (typical 150 ns, temp. dependent) VP: single-sided supply voltage (or 0.5 × (VDD + |VSS|)) Po(0.5 %): output power at the onset of clipping Note that Io(peak)M should be below 9.2 A (Section 8.3.2). Io(peak) is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and voltage drop over the coil. 13.4 External clock For duty cycle independent operation of the device, the external clock input frequency is internally divided by two. This implies that the frequency of the external clock is as twice as high as the internal clock (typical 2 × 345 kHz = 690 kHz). If two or more class-D amplifiers are used it is recommended that all devices run at the same switching frequency. This can be realized by connecting all OCS pins together and feeding them from an external oscillator. When applying an external oscillator, it is necessary to force pin OSC to a DC level above SGND. The internal oscillator is disabled and the PWM modulator will switch with half the externally applied frequency. The internal oscillator requires an external resistor Rext(OSC) and capacitor COSC between pin OSC and PIN VSSA. The noise contribution of the internal oscillator is supply voltage dependent. An external low noise oscillator is recommended for low noise applications running at high supply voltage. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 18 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 13.5 Noise Noise should be measured using a high order low-pass filter with a cut-off frequency of 20 kHz. The standard audio band pass filters, used in audio analyzers, do not suppress the residue of the carrier frequency sufficiently to ensure a reliable measurement of the audible noise. Noise measurements should preferably be carried out using AES 17 (‘brickwall’) filters or an audio precision AUX 0025 filter, which was designed specifically for measuring class-D switching amplifiers. 13.6 Heatsink requirements In many applications it may be necessary to connect an external heatsink to the TDA8950. Equation 5 shows the relationship between the maximum power dissipation, before activation of the TFB, and the total thermal resistance from junction to ambient T j – T amb R th ( j – a ) = ----------------------P diss (5) Power dissipation (Pdiss) is determined by the efficiency of the TDA8950. The efficiency measured as a function of output power is given in Figure 21. The power dissipation can be derived as a function of output power (Figure 20). mbl469 30 P (W) (1) 20 (2) 10 (3) (4) (5) 0 0 20 40 60 80 100 Tamb (°C) (1) Rth(j-a) = 5 K/W. (2) Rth(j-a) = 10 K/W. (3) Rth(j-a) = 15 K/W. (4) Rth(j-a) = 20 K/W. (5) Rth(j-a) = 35 K/W. Fig 9. De-rating curves for power dissipation as a function of maximum ambient temperature In the following example, a heatsink calculation is made for an 8 Ω BTL application with a ±35 V supply: TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 19 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier The audio signal has a crest factor of 10 (the ratio between peak power and average power (20 dB)), this means that the average output power is 1⁄10 of the peak power. In this case, the peak RMS output power level would be the 0.5 % THD level, i.e. 220 W. The average power would then be 1⁄10 × 220 W = 22 W. The dissipated power at an output power of 22 W is approximately 5 W. When the maximum expected ambient temperature is 85 °C, the total Rth(j-a) would then ( 140 – 85 ) become ------------------------- = 11 K/W 5 Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a) Rth(j-c) = 1.1 K/W Rth(c-h) = 0.5 K/W to 1 K/W (dependent on mounting) So the thermal resistance between heatsink and ambient temperature is: Rth(h-a) = 11 − (1.1 + 1) = 8.9 K/W The de-rating curves (given for several values of Rth(j-a)) are illustrated in Figure 9. A maximum junction temperature Tj = 150 °C is taken into account. From Figure 9 the maximum allowable power dissipation for a given heatsink size can be derived or the required heatsink size can be determined at a required dissipation level. 13.7 Output current limiting To guarantee the robustness of the TDA8950, the maximum output current that can be delivered by the output stage is limited. An advanced OverCurrent Protection (OCP) is included for each output power switch. When the current flowing through any of the power switches exceeds the defined internal threshold current of 9.2 A (e.g. in case of a short-circuit to the supply lines or a short-circuit across the load), the maximum output current of the amplifier will be regulated to 9.2 A. The TDA8950 amplifier can distinguish between a low-ohmic short-circuit condition and other over current conditions like dynamic impedance drops of the loudspeakers used. The impedance threshold (Zth) depends on the supply voltage used. Depending on the impedance of the short-circuit, the amplifier will react as follows: • Short-circuit impedance > Zth: The maximum output current of the amplifier is regulated to 9.2 A, but the amplifier will not shut-down its PWM outputs. Effectively this results in a clipping output signal across the load (behavior is very similar to voltage clipping). • Short-circuit impedance < Zth: The amplifier will limit the maximum output current to 9.2 A and at the same time the capacitor on pin PROT is discharged. When the voltage across this capacitor drops below an internal threshold voltage, the amplifier will shutdown completely and an internal timer will be started. A typical value for the capacitor on pin PROT is 220 pF. After a fixed time of 100 ms the amplifier is switched on again. If the requested output current is still too high, the amplifier will switch-off again. Thus the amplifier will try to switch to the Operating mode every TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 20 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 100 ms. The average dissipation will be low in this situation because of this low duty cycle. If the over current condition is removed the amplifier will remain in Operating mode after being restarted. In this way the TDA8950 amplifier is fully protected against short-circuit conditions while at the same time so-called audio holes, as a result of loudspeaker impedance drops, are eliminated. 13.8 Pumping effects In a typical stereo half-bridge SE application the TDA8950 is supplied by a symmetrical voltage (e.g. VDD = +35 V and VSS = −35 V). When the amplifier is used in an SE configuration, a ‘pumping effect’ can occur. During one switching interval, energy is taken from one supply (e.g. VDD), while a part of that energy is returned to the other supply line (e.g. VSS) and vice versa. When the voltage supply source cannot sink energy, the voltage across the output capacitors of that voltage supply source will increase and the supply voltage is pumped to higher levels. The voltage increase caused by the pumping effect depends on: • • • • • Speaker impedance Supply voltage Audio signal frequency Value of decoupling capacitors on supply lines Source and sink currents of other channels When applying the TDA8950, measures must be taken within the application to minimize the pumping effect and prevent malfunctions of either the audio amplifier and/or the voltage supply source. Amplifier malfunction due to the pumping effect can cause triggering of the UVP, OVP or UBP. The best remedy against pumping effects is to use the TDA8950 in a mono full-bridge application or, in the case of stereo half-bridge applications, adapt the power supply (e.g. increase supply decoupling capacitors). 13.9 Application schematics Notes for the application schematic: • A solid ground plane connected to VSS around the switching amplifier is necessary to prevent emission. • 100 nF capacitors must be placed as close as possible to the power supply pins of the TDA8950. • The internal heat spreader of the TDA8950 is internally connected to VSS. • The external heatsink must be connected to the ground plane. • Use a thermally conductive, electrically non-conductive, Sil-Pad between the backside of the TDA8950 and a small external heatsink. • The differential inputs enable the best system level audio performance with unbalanced signal sources. In case of hum, due to floating inputs, connect the shielding or source ground to the amplifier ground. Jumpers J1 and J2 are open on set level and are closed on the stand-alone demo board. • Minimum total required capacitance per power supply line is 3300 µF. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 21 of 39 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TDA8950_1 VDDA 10 Ω SINGLE ENDED OUTPUT FILTER VALUES LOAD Llc Clc VDDP Cvddp 470 µF Cvp 22 µF GND Cvssp 470 µF VSSA VSSP VDDP VSSP Rvssa Rev. 01 — 9 September 2008 + Cin 4 IN1P OSC n.c. n.c. n.c. 6 5 1 Cvddp Cvp Cvssp 100 nF 100 nF 100 nF 23 8 10 Ω Csn 220 pF VSSP 8 10 IN1N Csn 220 pF 11 IN1 Cin 9 9 470 nF OUT1 Llc BOOT1 Cbo Clc 15 nF SGND − Cin 19 15 nF IN2 + 14 IN2N Llc OUT2 VDDP 21 Cvssa 100 nF 100 nF Cstab 470 nF VSSP VSSA 13 Rsn VSSP2 VSSD Cprot 100 nF 16 10 Ω Cvddp Cvp Cvssp 100 nF 100 nF 100 nF VDDP VSSP Clc Rzo 22 Ω − Czo + 100 nF Csn 220 pF VSSP 001aai420 TDA8950 22 of 39 © NXP B.V. 2008. All rights reserved. VSSA 17 PROT STABI VSSA Cvdda Fig 10. Simplified application diagram 7 VDDP2 12 18 VDDA 20 Csn 220 pF 2 × 150 W class-D power amplifier 470 nF VDDA + − Czo 100 nF BOOT2 Cbo 22 470 nF Cin Rzo 22 Ω TDA8950J 15 IN2P 1000 nF 680 nF 470 nF VDDP Rsn 470 nF − 10 µH 15 µH 22 µH VSSP VDDP1 Rosc 30 kΩ VSSA 10 Ω 2Ω-3Ω 3Ω-6Ω 4Ω-8Ω mode control VSSP1 VDDP MODE Preliminary data sheet Rvdda TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 13.10 Layout and grounding To obtain a high-level system performance, certain grounding techniques are essential. The input reference grounds have to be tied with their respective source grounds and must have separate tracks from the power ground tracks. This will prevent the large (output) signal currents from interfering with the small AC input signals. The small-signal ground tracks should be physically located as far as possible from the power ground tracks. Supply and output tracks should be as wide as possible for delivering maximum output power. R20, R21 ground R19 FBGND 001aai421 Fig 11. Printed-circuit board layout (quasi-single-sided); components view TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 23 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 13.11 Curves measured in reference design 001aai422 10 THD (%) 1 (2) 10−1 (1) 10−2 (3) 10−3 10−2 10−1 1 10 102 103 Po (W) VP = ±35 V, 2 × 4 Ω SE configuration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz Fig 12. THD as a function of output power, SE configuration with 2 × 4 Ω load 001aai700 10 THD (%) 1 (2) 10−1 (1) 10−2 (3) 10−3 10−2 10−1 1 10 102 103 Po (W) VP = ±35 V, 2 × 6 Ω SE configuration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz Fig 13. THD as a function of output power, SE configuration with 2 × 6 Ω load TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 24 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 001aai423 10 THD (%) 1 (1) 10−1 (2) 10−2 (3) 10−3 10−2 10−1 1 102 10 103 PO (W) VP = ±35 V, fosc = 350 kHz, 1 × 8 Ω BTL configuration. (1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz Fig 14. THD as a function of output power, BTL configuration with 1 × 8 Ω load 001aai424 10 THD (%) 1 10−1 (1) 10−2 (2) 10−3 10 102 103 104 fi (Hz) 105 VP = ±35 V, 2 × 4 Ω SE configuration. (1) OUT2, PO = 1 W (2) OUT2, PO = 10 W Fig 15. THD as a function of frequency, SE configuration with 2 × 4 Ω load TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 25 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 001aai701 10 THD (%) 1 10−1 (1) 10−2 (2) 10−3 10 102 103 104 fi (Hz) 105 VP = ±35 V, 2 × 6 Ω SE configuration. (1) OUT2, Po = 1 W (2) OUT2, Po = 10 W Fig 16. THD as a function of frequency, SE configuration with 2 × 6 Ω load 001aai702 10 THD (%) 1 10−1 (1) 10−2 (2) 10−3 10 102 103 104 f (Hz) 105 VP = ±35 V, 1 × 8 Ω BTL configuration (1) Po = 1 W (2) Po = 10 W Fig 17. THD as a function of frequency, BTL configuration with 1 × 8 Ω load TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 26 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 001aai703 0 αcs (dB) −20 −40 −60 −80 −100 10 102 103 104 105 f (Hz) VP = ±35 V, 2 × 4 Ω SE configuration For OUT1 and OUT2 for both 1 W and 10 W. Fig 18. Channel separation as a function of frequency, SE configuration with 2 × 4 Ω load 001aai704 0 αcs (dB) −20 −40 −60 −80 −100 10 102 103 104 105 f (Hz) VP = ±35 V, 2 × 6 Ω SE configuration For OUT1 and OUT2 for both 1 W and 10 W. Fig 19. Channel separation as a function of frequency, SE configuration with 2 × 6 Ω load TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 27 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier P (W) 001aai705 40 35 30 25 (1) 20 (2) 15 (3) 10 5 0 0 20 40 60 80 100 120 Po (W) VP = ±35 V, fi = 1 kHz, fosc = 325 kHz (1) 2 × 4 Ω SE configuration (2) 2 × 6 Ω SE configuration (3) 2 × 8 Ω SE configuration Fig 20. Power dissipation as function of output power per channel 001aai706 100 (1) η (%) (2) (3) 80 60 40 20 0 0 20 40 60 80 100 120 Po (W) VP = ±35 V, fi = 1 kHz, fosc = 325 kHz (1) 2 × 4 Ω SE configuration (2) 2 × 6 Ω SE configuration (3) 2 × 8 Ω SE configuration Fig 21. Efficiency as function of output power per channel TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 28 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier Po (W) 001aai707 200 180 160 140 120 (1) 100 (2) 80 (3) 60 (4) 40 20 0 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 40 Vp (V) fi = 1 kHz, fosc = 325 kHz Note: infinite heat sink used. (1) THD = 10 %, 4 Ω (2) THD = 0.5 %, 4 Ω; THD = 10 %, 6 Ω (3) THD = 0.5 %, 6 Ω; THD = 10 %, 8 Ω (4) THD = 0.5 %, 8 Ω Fig 22. Output power as a function of supply voltage, SE configuration Po (W) 001aai708 350 300 250 (1) 200 (2) 150 (3) (4) 100 50 0 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 40 Vp (V) fi = 1 kHz, fosc = 325 kHz Note: infinite heat sink used. (1) THD = 10 %, 8 Ω (2) THD = 0.5 %, 8 Ω (3) THD = 10 %, 16 Ω (4) THD = 0.5 %, 16 Ω Fig 23. Output power as function of supply voltage, BTL configuration TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 29 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 001aai709 45 Gv(cl) (dB) 40 (1) 35 (2) 30 (3) (4) 25 20 102 10 103 104 105 f (Hz) VP = ±35 V, Vi = 100 mV, Rs = 0 Ω, Ci = 330 pF. (1) 1 × 8 Ω BTL configuration (2) 2 × 4 Ω SE configuration (3) 2 × 6 Ω SE configuration (4) 2 × 8 Ω SE configuration Fig 24. Gain as function of frequency, Rs = 0 Ω, Ci = 330 pF 001aai710 −20 SVRR (dB) −40 −60 (1) −80 (2) −100 −120 (3) −140 102 10 103 104 106 fripple (Hz) Ripple on VDD, short on input pins. VP = ±35 V, RL = 4 Ω, Vripple = 2 V (p-p). (1) OUT2, mute (2) OUT2, on (3) OUT2, standby Fig 25. SVRR as function of ripple frequency TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 30 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 001aai711 −20 SVRR (dB) −40 −60 −80 (2) (1) −100 −120 (3) −140 102 10 103 104 106 fripple (Hz) Ripple on VSS, short on input pins. VP = ±35 V, RL = 4 Ω, Vripple = 2 V (p-p). (1) OUT2, mute (2) OUT2, on (3) OUT2, standby Fig 26. SVRR as function of ripple frequency 001aai712 10 Vo (V) 1 0.1 0.01 0.001 0.0001 (1) (2) 0.00001 0.000001 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VMODE (V) VP = ±35 V (1) Out1, down (2) Out1, up Fig 27. Output voltage as function of mode voltage TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 31 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 001aai713 −50 αmute (dB) −60 −70 (1) (2) (3) −80 −90 10 102 103 104 105 f (Hz) VP = ±35 V, Vi = 2 V (rms), fosc = 325 kHz (1) OUT2, 8 Ω (2) OUT2, 6 Ω (3) OUT2, 4 Ω Fig 28. Mute attenuation as function of frequency TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 32 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 14. Package outline DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 non-concave Dh x D Eh view B: mounting base side A2 d A5 A4 β E2 B j E E1 L2 L3 L1 L 1 e1 Z e 0 5 v M e2 m w M bp c Q 23 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A 2 mm A4 A5 bp c D (1) d D h E (1) e e1 e2 12.2 4.6 1.15 1.65 0.75 0.55 30.4 28.0 12 2.54 1.27 5.08 11.8 4.3 0.85 1.35 0.60 0.35 29.9 27.5 Eh E1 E2 j L 6 10.15 6.2 1.85 3.6 9.85 5.8 1.65 2.8 L1 L2 L3 m Q v w x β Z (1) 14 10.7 2.4 1.43 2.1 4.3 0.6 0.25 0.03 45° 13 9.9 1.6 0.78 1.8 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 98-02-20 02-04-24 SOT411-1 Fig 29. Package outline SOT411-1 (DBS23P) TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 33 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3 E D A x X c E2 y HE v M A D1 D2 12 1 pin 1 index Q A A2 E1 (A3) A4 θ Lp detail X 24 13 Z w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) D1 D2 E(2) E1 E2 e HE Lp Q +0.08 0.53 0.32 16.0 13.0 −0.04 0.40 0.23 15.8 12.6 1.1 0.9 11.1 10.9 6.2 5.8 2.9 2.5 1 14.5 13.9 1.1 0.8 1.7 1.5 bp c D(2) v w x y 0.25 0.25 0.03 0.07 Z θ 2.7 2.2 8° 0° Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-02-18 03-07-23 SOT566-3 Fig 30. Package outline SOT566-3 (HSOP24) TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 34 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 35 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 31) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Table 11. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 12. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 31. TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 36 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 31. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA8950_1 20080909 Preliminary data sheet - - TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 37 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TDA8950_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 9 September 2008 38 of 39 TDA8950 NXP Semiconductors 2 × 150 W class-D power amplifier 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.1.1 8.3.1.2 8.3.2 8.3.3 8.3.4 8.4 9 10 11 12 12.1 12.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pulse width modulation frequency . . . . . . . . . . 8 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal protection . . . . . . . . . . . . . . . . . . . . . . 8 Thermal FoldBack (TFB) . . . . . . . . . . . . . . . . . 8 OverTemperature Protection (OTP) . . . . . . . . . 9 OverCurrent Protection (OCP) . . . . . . . . . . . . . 9 Window Protection (WP). . . . . . . . . . . . . . . . . 10 Supply voltage protections . . . . . . . . . . . . . . . 10 Differential audio inputs . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics. . . . . . . . . . . . . . . . . . 12 Static characteristics. . . . . . . . . . . . . . . . . . . . 13 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . 14 Stereo and dual SE application characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15 12.3 Mono BTL application characteristics . . . . . . . 16 13 Application information. . . . . . . . . . . . . . . . . . 17 13.1 Mono BTL application . . . . . . . . . . . . . . . . . . . 17 13.2 Pin MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.3 Output power estimation. . . . . . . . . . . . . . . . . 17 13.3.1 SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.3.2 Bridge-Tied Load (BTL) . . . . . . . . . . . . . . . . . 18 13.4 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.5 Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 13.6 Heatsink requirements . . . . . . . . . . . . . . . . . . 19 13.7 Output current limiting. . . . . . . . . . . . . . . . . . . 20 13.8 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 21 13.9 Application schematics . . . . . . . . . . . . . . . . . . 21 13.10 Layout and grounding . . . . . . . . . . . . . . . . . . . 23 13.11 Curves measured in reference design . . . . . . 24 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 15 Soldering of SMD packages . . . . . . . . . . . . . . 35 15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 35 15.2 15.3 15.4 16 17 17.1 17.2 17.3 17.4 18 19 Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 36 37 38 38 38 38 38 38 39 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 9 September 2008 Document identifier: TDA8950_1