PHILIPS 74LVC32245AEC

74LVC32245A
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Rev. 01 — 20 August 2007
Product data sheet
1. General description
The 74LVC32245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible
outputs in both send and receive directions. The device features four output enable (nOE)
inputs for easy cascading and four send/receive (nDIR) inputs for direction control.
Pin nOE controls the outputs so that the buses are effectively isolated.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
To ensure the high-impedance state during power-up or power-down, pin nOE should be
tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by
the current-sinking capability of the driver.
2. Features
n
n
n
n
n
n
n
n
n
n
n
n
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when VCC = 0 V
Complies with JEDEC standard JESD8-B / JESD36
ESD protection:
u HBM EIA/JESD22-A114-B exceeds 2000 V
u MM EIA/JESD22-A115-A exceeds 200 V
Specified from −40 °C to +85 °C
Packaged in plastic fine-pitch ball grid array package
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
74LVC32245AEC
−40 °C to +85 °C
Description
LFBGA96 plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5 × 5.5 × 1.05 mm
Version
SOT536-1
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
4. Functional diagram
A3
1DIR
H3
1OE
A5
A6
E5
4B5
T6
4B6
T5
3B7
R1
4A6
M2
3A7
R2
4A5
L1
3A6
3B6
M6
4B4
R6
P1
4A4
L2
3A5
3B5
M5
4B3
R5
P2
4A3
K1
3A4
3B4
L6
4B2
P6
N1
4A2
K2
3A3
3B3
L5
4B1
P5
N2
4A1
J1
3A2
3B2
K6
4B0
N6
T4
4A0
J2
3A1
3B1
K5
4OE
N5
H2
4DIR
J4
3A0
3B0
J6
2B7
T3
H1
2A7
D1
3DIR
3OE
J5
2B6
H5
G1
2A6
D2
1A7
1B7
J3
2B5
H6
G2
2A5
C1
1A6
1B6
D6
2B4
G6
F1
2A4
C2
1A5
1B5
D5
2B3
G5
F2
2A3
B1
1A4
1B4
C6
2B2
F6
E1
2A2
B2
1A3
1B3
C5
2B1
F5
E2
2A1
A1
1A2
1B2
B6
2B0
E6
H4
2A0
A2
1A1
1B1
B5
2OE
A4
1A0
1B0
2DIR
T1
4A7
M1
4B7
T2
mna476
Fig 1. Logic symbol
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
2 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
5. Pinning information
5.1 Pinning
mna475
6
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A6
3A1
3A3
3A5
3A7
4A1
4A3
4A5
4A6
5
1A0
1A2
1A4
1A6
2A0
2A2
2A4
2A7
3A0
3A2
3A4
3A6
4A0
4A2
4A4
4A7
4
1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE
3
1DIR GND VCC GND GND VCC GND 2DIR 3DIR GND VCC GND GND VCC GND 4DIR
2
1B0
1B2
1B4
1B6
2B0
2B2
2B4
2B7
3B0
3B2
3B4
3B6
4B0
4B2
4B4
4B7
1
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B6
3B1
3B3
3B5
3B7
4B1
4B3
4B5
4B6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Fig 2. Pin configuration
5.2 Pin description
Table 2.
Pin description
Pin name
Ball
Description
nDIR (n = 1 to 4)
A3, H3, J3, T3
direction control
nOE (n = 1 to 4)
A4, H4, J4, T4
output enable input (active LOW)
1A[0:7]
A5, A6, B5, B6, C5, C6, D5, D6
input or output
1B[0:7]
A2, A1, B2, B1, C2, C1, D2, D1
input or output
2A[0:7]
E5, E6, F5, F6, G5, G6, H6, H5
input or output
2B[0:7]
E2, E1, F2, F1, G2, G1, H1, H2
input or output
3A[0:7]
J5, J6, K5, K6, L5, L6, M5, M6
input or output
3B[0:7]
J2, J1, K2, K1, L2, L1, M2, M1
input or output
4A[0:7]
N5, N6, P5, P6, R5, R6, T6, T5
input or output
4B[0:7]
N2, N1, P2, P1, R2, R1, T1, T2
input or output
GND
B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, ground (0 V)
M3, M4, N3, N4, R3, R4
VCC
C3, C4, F3, F4, L3, L4, P3, P4
supply voltage
6. Functional description
Table 3.
Function selection[1]
Input
Output
nOE
nDIR
nAn
nBn
L
L
A=B
inputs
L
H
inputs
B=A
H
X
Z
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
3 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
Min
Max
Unit
−0.5
+6.5
V
−50
-
mA
−0.5
+6.5
V
-
±50
mA
output HIGH or LOW state
[2]
−0.5
VCC + 0.5
V
output 3-state
[2]
−0.5
+6.5
V
-
±50
mA
supply current
[3]
-
200
mA
IGND
ground current
[3]
−200
-
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
[4]
-
1000
mW
output voltage
VO
output current
IO
ICC
VO > VCC or VO < 0 V
VO = 0 V to VCC
Tamb = −40 °C to +85 °C
[1]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
All supply and ground pins connected externally to one voltage source.
[4]
Above 70 °C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
for maximum speed performance
2.7
-
3.6
V
for low-voltage applications
1.2
-
-
V
0
-
5.5
V
0
-
VCC
V
VI
input voltage
VO
output voltage
output 3-state
0
-
5.5
V
Tamb
ambient temperature
in free air
−40
-
+85
°C
∆t/∆V
input transition rise and fall
rate
VCC = 1.2 V to 2.7 V
-
-
20
ns/V
VCC = 2.7 V to 3.6 V
-
-
10
ns/V
output HIGH or LOW state
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
4 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC (V)
Min
Typ[1]
Max
Unit
1.2
VCC
-
-
V
2.7 to 3.6
2.0
-
-
V
1.2
-
-
GND
V
2.7 to 3.6
-
-
0.8
V
IO = −100 µA
2.7 to 3.6
VCC − 0.2
VCC
-
V
IO = −12 mA
2.7
VCC − 0.5
-
-
V
IO = −18 mA
3.0
VCC − 0.6
-
-
V
IO = −24 mA
3.0
VCC − 0.8
-
-
V
Conditions
Tamb = −40 °C to +85 °C
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
VOH
HIGH-level output voltage
LOW-level output voltage
VOL
VI = VIH or VIL
VI = VIH or VIL
IO = 100 µA
2.7 to 3.6
-
GND
0.20
V
IO = 12 mA
2.7
-
-
0.40
V
IO = 24 mA
3.0
-
-
0.55
V
II
input leakage current
VI = 5.5 V or GND
3.6
-
±0.1
±5
µA
IOZ
OFF-state output current
VI = VIH or VIL;
VO = 5.5 V or GND
3.6
-
±0.1
±5
µA
IOFF
power-off leakage current
VI or VO = 5.5 V
0.0
-
±0.1
±10
µA
ICC
supply current
VI = VCC or GND; IO = 0 A
3.6
-
0.1
40
µA
∆ICC
additional supply current
per input pin;
VI = VCC − 0.6 V; IO = 0 A
2.7 to 3.6
-
5
500
µA
CI
input capacitance
VI = GND to VCC
0 to 3.6
-
5.0
-
pF
CI/O
input/output capacitance
VI = GND to VCC
0 to 3.6
-
10
-
pF
[2]
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
[2]
For I/O ports the parameter IOZ includes the input leakage current.
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
5 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 5.
Symbol Parameter
Conditions
VCC (V)
nAn to nBn; nBn to nAn;
see Figure 3
1.2
Min
Typ[1]
Max
Unit
Tamb = −40 °C to +85 °C
propagation delay
tpd
[2]
-
13.0
-
ns
1.0
2.7
4.7
ns
1.0
2.2
4.5
ns
-
15.0
-
ns
2.7
1.5
3.6
6.7
ns
3.0 to 3.6
1.0
2.8
5.5
ns
-
11.0
-
ns
1.5
3.4
6.6
ns
2.7
3.0 to 3.6
enable time
ten
disable time
tdis
nOE to nAn, nBn: see Figure 4
nOE to nAn, nBn; see Figure 4
[2]
1.2
[2]
1.2
2.7
3.0 to 3.6
tsk(o)
output skew time
CPD
power dissipation
capacitance
per buffer; VI = GND to VCC
1.5
3.2
5.6
ns
3.0 to 3.6
[3]
-
-
1.0
ns
3.3
[4]
-
30
-
pF
[1]
Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 2.7 V, and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
VI
nAn, nBn
input
VM
GND
t PHL
t PLH
VOH
nBn, nAn
output
VM
VOL
mna477
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 3. The input (nAn, nBn) to output (nBn, nAn) propagation delays
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
6 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
VI
nOE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
outputs
enabled
outputs
disabled
outputs
enabled
mna362
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5 × VCC at VCC < 2.7 V.
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VX = VOL + 0.15 V at VCC < 2.7 V.
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.15 V at VCC < 2.7 V.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4. 3-state enable and disable times.
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
7 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
001aae331
Test data is given in Table 8.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 5. Load circuitry for switching times
Table 8.
Test data
Supply voltage
Input
Load
VEXT
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
≤ 2 ns
50 pF
500 Ω
open
2 × VCC
GND
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
8 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
12. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
A
B
D
ball A1
index area
A
A2
E
A1
detail X
e1
C
1/2 e
∅v M C A B
e
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
ball A1
index area
y1 C
y
∅w M C
b
e
e2
1/2 e
1 2 3 4 5 6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.5
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
0.8
4
12
0.15
0.1
0.1
0.2
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-03-04
03-02-05
SOT536-1
Fig 6. Package outline SOT536-1 (LFBGA96)
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
9 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
13. Abbreviations
Table 9.
Abbreviations
Acronym
Description
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC32245A_1
20070820
Product data sheet
-
-
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
10 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
74LVC32245A_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 20 August 2007
11 of 12
74LVC32245A
NXP Semiconductors
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 20 August 2007
Document identifier: 74LVC32245A_1