74LVC4066
Quad bilateral switch
Rev. 02 — 27 August 2007
Product data sheet
1. General description
The 74LVC4066 is a high-speed Si-gate CMOS device.
The 74LVC4066 provides four single pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features
■ Wide supply voltage range from 1.65 V to 5.5 V
■ Very low ON resistance:
◆ 7.5 Ω (typical) at VCC = 2.7 V
◆ 6.5 Ω (typical) at VCC = 3.3 V
◆ 6 Ω (typical) at VCC = 5 V
■ Switch current capability of 32 mA
■ High noise immunity
■ CMOS low-power consumption
■ Direct interface TTL-levels
■ Latch-up performance exceeds 250 mA
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
■ Enable inputs accept voltages up to 5 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC4066
NXP Semiconductors
Quad bilateral switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC4066D
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVC4066PW
−40 °C to +125 °C
TSSOP14
plastic thin small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVC4066BQ
−40 °C to +125 °C
DHVQFN14
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
4. Functional diagram
1
1Y
13
1E
4
2Y
1Z
2
1
1
2Z
3
2
13 #
4
4
5
2E
8
3Y
6
3E
11
4Y
12
4E
5
3Z
9
4Z 10
3
5
1
X1
1
#
2
1
3
X1
#
8
6
1
13 #
9
#
11
10
12 #
8
6
1
#
11
12 #
(a)
1
9
X1
1
1
10
X1
(b)
mnb111
mnb112
Fig 1. Logic symbol
Fig 2. Logic symbol (IEEE/IEC)
Z
Y
E
VCC
mna658
Fig 3. Logic diagram (one switch)
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
2 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
5. Pinning information
1Y
terminal 1
index area
14 VCC
5.1 Pinning
1
14 VCC
1Z
2
13 1E
1Z
2
13 1E
12 4E
2Z
3
12 4E
2Y
4
4066
11 4Y
2E
5
GND(1)
10 4Z
3E
6
1
1Y
4066
11 4Y
10 4Z
2E
5
3E
6
9
3Z
GND
7
8
3Y
9
8
4
3Y
2Y
7
3
GND
2Z
3Z
001aad118
Transparent top view
001aad117
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration for SO14 and TSSOP14
Fig 5. Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1Y
1
independent input/output
1Z
2
independent output/input
2Z
3
independent output/input
2Y
4
independent input/output
2E
5
enable input (active HIGH)
3E
6
enable input (active HIGH)
GND
7
ground (0 V)
3Y
8
independent input/output
3Z
9
independent output/input
4Z
10
independent output/input
4Y
11
independent input/output
4E
12
enable input (active HIGH)
1E
13
enable input (active HIGH)
VCC
14
supply voltage
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
3 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
6. Functional description
Table 3.
Function table[1]
Input nE
Switch
L
OFF
H
ON
[1]
H = HIGH voltage level;
L = LOW voltage level.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
VI
input voltage
IIK
input clamping current
ISK
switch clamping current
VI < −0.5 V or VI < VCC + 0.5 V
VSW
switch voltage
enable and disable mode
ISW
switch current
−0.5 < VSW < VCC + 0.5 V
ICC
[1]
VI < −0.5 V or VI < VCC + 0.5 V
Min
Max
Unit
−0.5
+6.5
V
−0.5
+6.5
V
−50
-
mA
-
±50
mA
−0.5
+6.5
V
-
±50
mA
supply current
-
100
mA
IGND
ground current
−100
-
mA
Tstg
storage temperature
−65
+150
°C
-
500
mW
total power dissipation
Ptot
Tamb = −40 °C to +125 °C
[2]
[3]
[1]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[2]
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3]
For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
4 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
VSW
switch voltage
Tamb
ambient temperature
∆t/∆V
input transition rise and fall rate
[1]
Min
Typ
Max
Unit
1.65
-
5.5
V
0
-
5.5
V
0
-
VCC
V
−40
-
+125
°C
VCC = 1.65 V to 2.7 V
[2]
-
-
20
ns/V
VCC = 2.7 V to 5.5 V
[2]
-
-
10
ns/V
[1]
To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no
limit for the voltage drop across the switch.
[2]
Applies to control signal levels.
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
HIGH-level
input voltage
LOW-level
input voltage
−40 °C to +85 °C
Conditions
VCC = 1.65 V to 1.95 V
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
0.65VCC
-
-
0.65VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
0.7VCC
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V to 5.5 V
0.35VCC V
-
-
0.3VCC
-
0.3VCC
V
-
±0.1
±5
-
±20
µA
II
input leakage
current
pin nE; VCC = 5.5 V;
VI = 5.5 V or GND
[2]
IS(OFF)
OFF-state
leakage
current
VI = VIH or VIL; VCC = 5.5 V;
see Figure 6
[2]
-
±0.1
±5
-
±20
µA
IS(ON)
ON-state
leakage
current
VI = VIH or VIL; VCC = 5.5 V;
see Figure 7
[2]
-
±0.1
±5
-
±20
µA
ICC
supply current VI = VCC or GND; VSW = GND or
VCC; VCC = 5.5 V; IO = 0 A;
[2]
-
0.1
10
-
40
µA
∆ICC
additional
pin nE; VI = VCC − 0.6 V; VCC = 5.5 V;
supply current VSW = GND or VCC
[2]
-
5
500
-
5000
µA
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
5 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
Table 6.
Static characteristics …continued
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
−40 °C to +85 °C
Conditions
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
CI
input
capacitance
-
12.5
-
-
-
pF
CS(OFF)
OFF-state
capacitance
-
8.0
-
-
-
pF
CS(ON)
ON-state
capacitance
-
14.0
-
-
-
pF
[1]
All typical values are measured at Tamb = 25 °C.
[2]
These typical values are measured at VCC = 3.3 V.
9.1 Test circuits
VCC
VCC
E
VIL
IS
Y
Z
IS
IS
GND
VI
E
VIH
Z
Y
GND
VI
VO
001aag488
VO
001aag489
VI = VCC or GND and VO = GND or VCC.
VI = VCC or GND and VO = open circuit.
Fig 6. Test circuit for measuring OFF-state leakage
current
Fig 7. Test circuit for measuring ON-state leakage
current
9.2 ON resistance
Table 7.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14.
Symbol
RON(peak)
Parameter
−40 °C to +85 °C
Conditions
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
34.0
130
-
195
Ω
ON resistance (peak) VI = GND to VCC; see Figure 8
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
12.0
30
-
45
Ω
ISW = 12 mA; VCC = 2.7 V
-
10.4
25
-
38
Ω
ISW = 24 mA; VCC = 3 V to 3.6 V
-
7.8
20
-
30
Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
6.2
15
-
23
Ω
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
6 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
Table 7.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14.
Symbol
RON(rail)
Parameter
ON resistance (rail)
−40 °C to +85 °C
Conditions
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
8.2
18
-
27
Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
7.1
16
-
24
Ω
ISW = 12 mA; VCC = 2.7 V
-
6.9
14
-
21
Ω
ISW = 24 mA; VCC = 3 V to 3.6 V
-
6.5
12
-
18
Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
5.8
10
-
15
Ω
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
10.4
30
-
45
Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
7.6
20
-
30
Ω
ISW = 12 mA; VCC = 2.7 V
-
7.0
18
-
27
Ω
ISW = 24 mA; VCC = 3 V to 3.6 V
-
6.1
15
-
23
Ω
-
4.9
10
-
15
Ω
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
26.0
-
-
-
Ω
VI = GND; see Figure 8
VI = VCC; see Figure 8
ISW = 32 mA; VCC = 4.5 V to 5.5 V
RON(flat)
ON resistance
(flatness)
VI = GND to VCC
[2]
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
5.0
-
-
-
Ω
ISW = 12 mA; VCC = 2.7 V
-
3.5
-
-
-
Ω
ISW = 24 mA; VCC = 3 V to 3.6 V
-
2.0
-
-
-
Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
1.5
-
-
-
Ω
[1]
Typical values are measured at Tamb = 25 °C and nominal VCC.
[2]
Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
7 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
9.3 ON resistance test circuit and graphs
mna673
40
RON
(Ω)
30
VSW
(1)
20
VCC
E
VIH
(2)
(3)
Y
10
Z
(4)
GND
VI
(5)
ISW
0
0
1
2
3
4
5
VI (V)
001aag490
RON = VSW / ISW.
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 8. Test circuit for measuring ON resistance
001aaa712
55
RON
(Ω)
Fig 9. Typical ON resistance as a function of input
voltage; Tamb = 25 °C
001aaa708
15
RON
(Ω)
45
13
35
11
(4)
(3)
(2)
(1)
(1)
(2)
25
9
(3)
(4)
15
7
5
5
0
0.4
0.8
1.2
1.6
2.0
0
0.5
VI (V)
1.5
2.0
2.5
VI (V)
(1) Tamb = 125 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(4) Tamb = −40 °C.
Fig 10. ON resistance as a function of input voltage;
VCC = 1.8 V
Fig 11. ON resistance as a function of input voltage;
VCC = 2.5 V
74LVC4066_2
Product data sheet
1.0
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
8 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
001aaa709
13
001aaa710
10
RON
(Ω)
RON
(Ω)
11
8
(1)
(1)
9
(2)
(2)
6
(3)
(3)
7
(4)
(4)
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
VI (V)
0
1
2
3
4
VI (V)
(1) Tamb = 125 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(4) Tamb = −40 °C.
Fig 12. ON resistance as a function of input voltage;
VCC = 2.7 V
Fig 13. ON resistance as a function of input voltage;
VCC = 3.3 V
001aaa711
7
RON
(Ω)
6
5
(1)
(2)
(3)
4
(4)
3
0
1
2
3
4
5
VI (V)
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 14. ON resistance as a function of input voltage; VCC = 5.0 V
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
9 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
10. Dynamic characteristics
Table 8.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit Figure 17.
Symbol Parameter
−40 °C to +85 °C
Conditions
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
-
0.8
2.0
-
3.0
ns
VCC = 2.3 V to 2.7 V
-
0.4
1.2
-
2.0
ns
propagation delay nY to nZ or nZ to nY;
see Figure 15
tpd
[2][3]
VCC = 2.7 V
-
0.4
1.0
-
1.5
ns
VCC = 3.0 V to 3.6 V
-
0.3
0.8
-
1.5
ns
-
0.2
0.6
-
1.0
ns
VCC = 4.5 V to 5.5 V
enable time
ten
nE to nY or nZ; see Figure 16
[4]
VCC = 1.65 V to 1.95 V
1.0
5.3
10
1.0
12.5
ns
VCC = 2.3 V to 2.7 V
1.0
3.0
5.6
1.0
7.0
ns
VCC = 2.7 V
1.0
2.6
5.0
1.0
6.5
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
4.4
1.0
5.5
ns
1.0
1.9
3.9
1.0
5.0
ns
VCC = 1.65 V to 1.95 V
1.0
4.2
9.0
1.0
11.5
ns
VCC = 2.3 V to 2.7 V
1.0
2.4
5.5
1.0
7.0
ns
VCC = 2.7 V
1.0
3.6
6.5
1.0
8.5
ns
VCC = 3.0 V to 3.6 V
1.0
3.4
6.0
1.0
7.5
ns
1.0
2.5
5.0
1.0
6.5
ns
VCC = 2.5 V
-
11.0
-
-
-
pF
VCC = 3.3 V
-
12.5
-
-
-
pF
VCC = 5.0 V
-
15.6
-
-
-
pF
VCC = 4.5 V to 5.5 V
disable time
tdis
nE to nY or nZ; see Figure 16
[5]
VCC = 4.5 V to 5.5 V
power dissipation
capacitance
CPD
−40 °C to +125 °C Unit
Typ[1]
CL = 50 pF; fi = 10 MHz;
VI = GND to VCC
[6]
[1]
Typical values are measured at Tamb = 25 °C and nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4]
ten is the same as tPZH and tPZL.
[5]
tdis is the same as tPLZ and tPHZ.
[6]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ{(CL + CS(ON)) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS(ON) = maximum ON-state switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ{(CL + CS(ON)) × VCC2 × fo} = sum of the outputs.
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
10 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
10.1 Waveforms and test circuit
VI
nY or nZ
input
VM
VM
GND
t PLH
t PHL
VOH
nZ or nY
output
VM
VM
VOL
001aaa541
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. Input (nY or nZ) to output (nZ or nY) propagation delays
VI
nE input
VM
GND
t PLZ
t PZL
VCC
output
LOW-to-OFF
OFF-to-LOW
nY or nZ
VM
VX
VOL
t PZH
t PHZ
nY or nZ
output
HIGH-to-OFF
OFF-to-HIGH
VOH
Vy
VM
GND
switch
enabled
switch
disabled
switch
enabled
001aaa542
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
1.65 V to 1.95 V
0.5VCC
0.5 VCC
VOL + 0.15 V
VOH − 0.15 V
2.3 V to 2.7 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH − 0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
4.5 V to 5.5 V
0.5VCC
0.5VCC
VOL + 0.3 V
VOH − 0.3 V
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
11 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 17. Load circuit for switching times
Table 10.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
1.65 V to 1.95 V
VCC
≤ 2.0 ns
30 pF
1 kΩ
open
GND
2VCC
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
GND
2VCC
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6V
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6V
4.5 V to 5.5 V
VCC
≤ 2.5 ns
50 pF
500 Ω
open
GND
2VCC
10.2 Additional dynamic characteristics
Table 11. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol
Parameter
Conditions
THD
total harmonic distortion
RL = 10 kΩ; CL = 50 pF; fi = 1 kHz;
see Figure 18
Min
Typ
Max
Unit
VCC = 1.65 V
-
0.032
-
%
VCC = 2.3 V
-
0.008
-
%
VCC = 3 V
-
0.006
-
%
VCC = 4.5 V
-
0.005
-
%
VCC = 1.65 V
-
0.068
-
%
VCC = 2.3 V
-
0.009
-
%
VCC = 3 V
-
0.008
-
%
VCC = 4.5 V
-
0.006
-
%
RL = 10 kΩ; CL = 50 pF; fi = 10 kHz;
see Figure 18
74LVC4066_2
Product data sheet
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74LVC4066
NXP Semiconductors
Quad bilateral switch
Table 11. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol
Parameter
Conditions
f(-3dB)
-3 dB frequency response
RL = 600 Ω; CL = 50 pF;
see Figure 19
Min
Typ
Max
Unit
VCC = 1.65 V
-
170
-
MHz
VCC = 2.3 V
-
210
-
MHz
VCC = 3 V
-
212
-
MHz
VCC = 4.5 V
-
215
-
MHz
VCC = 1.65 V
-
> 500
-
MHz
VCC = 2.3 V
-
> 500
-
MHz
VCC = 3 V
-
> 500
-
MHz
VCC = 4.5 V
-
> 500
-
MHz
VCC = 1.65 V
-
−46
-
dB
VCC = 2.3 V
-
−46
-
dB
VCC = 3 V
-
−46
-
dB
VCC = 4.5 V
-
−46
-
dB
VCC = 1.65 V
-
−42
-
dB
VCC = 2.3 V
-
−42
-
dB
VCC = 3 V
-
−42
-
dB
VCC = 4.5 V
-
−42
-
dB
RL = 50 Ω; CL = 5 pF; see Figure 19
αiso
isolation (OFF-state)
RL = 600 Ω; CL = 50 pF; fi = 1 MHz;
see Figure 20
RL = 50 Ω; CL = 5 pF; fi = 1 MHz; see
Figure 20
Vct
Xtalk
crosstalk voltage
crosstalk
between digital inputs and switch;
RL = 600 Ω; CL = 50 pF; fi = 1 MHz;
tr = tf = 2 ns; see Figure 21
VCC = 1.65 V
-
69
-
mV
VCC = 2.3 V
-
87
-
mV
VCC = 3 V
-
156
-
mV
VCC = 4.5 V
-
302
-
mV
VCC = 1.65 V
-
−58
-
dB
VCC = 2.3 V
-
−58
-
dB
VCC = 3 V
-
−58
-
dB
VCC = 4.5 V
-
−58
-
dB
VCC = 1.65 V
-
−58
-
dB
VCC = 2.3 V
-
−58
-
dB
VCC = 3 V
-
−58
-
dB
VCC = 4.5 V
-
−58
-
dB
between switches; RL = 600 Ω;
CL = 50 pF; fi = 1 MHz; see Figure 22
between switches; RL = 50 Ω;
CL = 5 pF; fi = 1 MHz; see Figure 22
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
13 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
Table 11. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol
Parameter
Conditions
Qinj
charge injection
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω;
fi = 1 MHz; RL = 1 MΩ; see Figure 23
Min
Typ
Max
Unit
VCC = 1.8 V
-
3.3
-
pC
VCC = 2.5 V
-
4.1
-
pC
VCC = 3.3 V
-
5.0
-
pC
VCC = 4.5 V
-
6.4
-
pC
VCC = 5.5 V
-
7.5
-
pC
10.2.1 Test circuits
VCC
0.5VCC
E
VIH
RL
Y/Z
10 pF
Z/Y
VO
600 Ω
fi
CL
D
001aag492
Test conditions:
VCC = 1.65 V: Vi = 1.4 V (p-p).
VCC = 2.3 V: Vi = 2 V (p-p).
VCC = 3 V: Vi = 2.5 V (p-p).
VCC = 4.5 V: Vi = 4 V (p-p).
Fig 18. Test circuit for measuring total harmonic distortion
VCC
E
VIH
0.1 pF
fi
0.5VCC
Y/Z
RL
Z/Y
50 Ω
VO
CL
dB
001aag491
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB.
Fig 19. Test circuit for measuring the frequency response when switch is in ON-state
74LVC4066_2
Product data sheet
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Rev. 02 — 27 August 2007
14 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
0.5VCC
VCC
RL VIL
0.1 pF
0.5VCC
E
RL
Y/Z
Z/Y
VO
50 Ω
fi
CL
dB
001aag493
Adjust fi voltage to obtain 0 dBm level at input.
Fig 20. Test circuit for measuring isolation (OFF-state)
VCC
E
Y/Z
G
logic
input
50 Ω
Z/Y
600 Ω
VO
RL
0.5VCC
CL
0.5VCC
001aag494
Fig 21. Test circuit for measuring crosstalk voltage (between digital inputs and switch)
0.5VCC
1E
VIH
0.1 pF
Ri
1Y or 1Z
600 Ω
fi
RL
1Z or 1Y
CHANNEL
ON
50 Ω
CL
50 pF
VO1
0.5VCC
2E
VIL
RL
2Y or 2Z
Ri
600 Ω
2Z or 2Y
CHANNEL
OFF
CL
50 pF
VO2
001aag496
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 22. Test circuit for measuring crosstalk between switches
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
15 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
VCC
E
Rgen
G
logic
input
Y/Z
Z/Y
VO
RL
1 MΩ
Vgen
CL
0.1 nF
001aag495
logic
input (E)
off
on
off
∆VO
VO
mna675
Qinj = ∆VO × CL.
∆VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 23. Test circuit for measuring charge injection
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
16 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 24. Package outline SOT108-1 (SO14)
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
17 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 25. Package outline SOT402-1 (TSSOP14)
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
18 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 26. Package outline SOT762-1 (DHVQFN14)
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
19 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
12. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
TTL
Transistor-Transistor Logic
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
DUT
Device Under Test
13. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC4066_2
20070827
Product data sheet
-
74LVC4066_1
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 2 “Features”:
Added: Wide supply voltage range from 1.65 V to 5.5 V
Added: Switch handling capability of 32 mA
Added: Multiple package options
Deleted: Complies with JEDESD-8 standards
Added: Specified from −40 °C to +85 °C and −40 °C to +125 °C
Added: Enable input accepts voltages up to 5 V
•
Section 7 “Limiting values”
Added: Derating factors of the applicable packages
•
Section 9 “Static characteristics”
Changed: Maximum values of ON resistance (peak) parameters and graphics.
•
Section 10 “Dynamic characteristics”:
Changed: Typical values of the charge injection.
74LVC4066_1
20030812
Product specification
74LVC4066_2
Product data sheet
-
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
20 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
74LVC4066_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 27 August 2007
21 of 22
74LVC4066
NXP Semiconductors
Quad bilateral switch
16. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
9.1
9.2
9.3
10
10.1
10.2
10.2.1
11
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms and test circuit . . . . . . . . . . . . . . . 11
Additional dynamic characteristics . . . . . . . . . 12
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 August 2007
Document identifier: 74LVC4066_2