74HC590 8-bit binary counter with output register; 3-state Rev. 02 — 28 April 2009 Product data sheet 1. General description The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks are connected together, the counter state always is one count ahead of the register. 2. Features n n n n n Counter and register have independent clock inputs Counter has master reset Complies with JEDEC standard no. 7A Multiple package options ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 2000 V n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC590N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HC590D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC590PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HC590BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT403-1 SOT763-1 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 4. Functional diagram 12 CE 11 CPC 8-BIT BINARY COUNTER 10 MRC 13 CPR RCO 9 8-BIT STORAGE REGISTER Q0 15 Q1 1 Q2 2 Q3 3 14 OE 3-STATE OUTPUTS Q4 4 Q5 5 Q6 6 Q7 7 001aac542 Fig 1. Functional diagram OE CPR 11 CPC 13 CE CPR RCO Q0 Q1 Q2 12 Q3 CE Q4 Q5 Q6 Q7 MRC 9 15 CPC MRC 14 13 12 11 10 EN3 C2 G1 1+ CTR8 9 (CT=255)Z4 CT=0 1 1D 2D Fig 2. Logic symbol 3 2 4 3 5 4 6 5 7 6 OE 14 15 1 001aac544 3 7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac545 Fig 3. IEC logic symbol 74HC590_2 Product data sheet 3 2 2D 10 RCO © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 2 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state OE CPR 14 13 12 CE CPC 9 11 T MRC 10 15 1R RCO Q0 C1 R 1S T 1 1R Q1 C1 R 1S T 2 1R Q2 C1 R 1S T 3 1R Q3 C1 R 1S T 4 1R Q4 C1 R 1S T 5 1R Q5 C1 R 1S T 6 1R Q6 C1 R 1S T 7 1R Q7 C1 R 1S 001aac543 Fig 4. Logic diagram 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 3 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 5. Pinning information 5.1 Pinning 1 terminal 1 index area Q2 2 15 Q0 Q3 3 14 OE Q4 4 Q5 Q1 1 Q2 2 16 VCC 15 Q0 Q3 3 14 OE Q4 4 13 CPR Q5 5 12 CE Q6 6 11 CPC Q7 7 10 MRC GND 8 13 CPR 12 CE 5 Q6 6 11 CPC Q7 7 10 MRC GND 74HC590 9 8 RCO 9 001aaj535 Fig 5. Pin configuration DIP16 RCO 001aac564 Fig 6. Pin configuration SO16 and TSSOP16 14 OE Q4 4 13 CPR Q5 5 Q6 6 Q7 7 12 CE GND(1) 11 CPC 10 MRC 9 16 VCC 15 Q0 3 RCO 1 2 Q3 8 Q1 Q2 GND 74HC590 16 VCC Q1 74HC590 Transparent top view 001aac547 (1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. Fig 7. Pin configuration DHVQFN16 5.2 Pin description Table 2. Pin description Symbol Pin Description Q0 to Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V) RCO 9 ripple carry output (active LOW) MRC 10 master reset counter input (active LOW) CPC 11 counter clock input (active HIGH) CE 12 count enable input (active LOW) CPR 13 register clock input (active HIGH) OE 14 output enable input (active LOW) VCC 16 supply voltage 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 4 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 6. Functional description Table 3. Function table[1] [2] Inputs Description OE CPR MRC CE CPC H X X X X Q outputs disable L X X X X Q outputs enable X ↑ X X X counter data stored into register X ↓ X X X register stage is not changed X X L X X counter clear X X H L ↑ advance one count X X H L ↓ no count X X H H X no count [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition. [2] RCO = Q0’ · Q1’ · Q2’ · Q3’ · Q4’ · Q5’ · Q6’ · Q7’ (Q0’ to Q7’ are internal outputs of the counter). 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 5 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state CPC CPR MRC CE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 RCO count inhibit counter clear high-impedance OFF-state 001aac548 Fig 8. Typical timing sequence 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 6 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to VCC + 0.5 V RCO standard output Min Max Unit −0.5 +7.0 V - ±20 mA - ±20 mA - ±25 mA - ±35 mA ICC supply current - 70 mA IGND ground current −70 - mA Tstg storage temperature −65 +150 °C DIP16 package - 750 mW SO16 package - 500 mW TSSOP16 package - 500 mW Qn bus driver output total power dissipation Ptot Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 packages: Ptot derates linearly with 8 mW/K above 70 °C. For TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN16 packages: Ptot derates linearly with 8 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC VI Min Typ Max Unit supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V VO output voltage ∆t/∆V input transition rise and fall rate Tamb Conditions 0 - VCC V VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V −40 - +125 °C ambient temperature 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 7 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions Min VIH VIL VOH HIGH-level input voltage LOW-level input voltage Typ −40 °C to +85 °C −40 °C to +125 °C Unit Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V HIGH-level VI = VIH or VIL output voltage all outputs IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = −4 mA; VCC = 4.5 V 4.18 4.31 - 4.13 - 4.1 - V IO = −5.2 mA; VCC = 6.0 V 5.68 5.80 - 5.63 - 5.6 - V IO = −6.0 mA; VCC = 4.5 V 4.18 4.31 - 4.13 - 4.1 - V IO = −7.8 mA; VCC = 6.0 V 5.68 5.80 - 5.63 - 5.6 - V RCO standard output Qn bus driver output VOL LOW-level VI = VIH or VIL output voltage all outputs IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4 mA; VCC = 4.5 V - 0.17 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.18 0.26 - 0.33 - 0.4 V IO = 6.0 mA; VCC = 4.5 V - 0.17 0.26 - 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V - 0.18 0.26 - 0.33 - 0.4 V RCO standard output Qn bus driver output II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 µA IOZ OFF-state output current per pin; VI = VIH or VIL; VO = VCC or GND; other inputs at VCC or GND; VCC = 6.0 V - - ±0.5 - ±5.0 - ±10 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 4.0 - 40 - 80 µA CI input capacitance - 3.5 - - - - - pF 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 8 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit see Figure 15. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max tpd propagation delay CPC to RCO; see Figure 9 Min Max Min Max [1] VCC = 2.0 V - 52 150 - 190 - 230 ns VCC = 4.5 V - 19 30 - 38 - 45 ns VCC = 6.0 V - 15 26 - 33 - 40 ns VCC = 2.0 V - 50 140 - 175 - 210 ns VCC = 4.5 V - 17 28 - 35 - 42 ns VCC = 6.0 V - 14 24 - 30 - 36 ns - 53 130 - 165 - 200 ns - 18 26 - 33 - 40 ns - 14 22 - 28 - 34 ns VCC = 2.0 V - 28 105 - 130 - 160 ns VCC = 4.5 V - 13 21 - 26 - 32 ns - 11 18 - 22 - 27 ns VCC = 2.0 V - 28 105 - 130 - 160 ns VCC = 4.5 V - 13 21 - 26 - 32 ns VCC = 6.0 V - 11 18 - 22 - 27 ns VCC = 2.0 V 100 24 - 125 - 145 - ns VCC = 4.5 V 20 9 - 25 - 29 - ns VCC = 6.0 V 17 8 - 21 - 25 - ns VCC = 2.0 V 75 28 - 95 - 110 - ns VCC = 4.5 V 15 8 - 19 - 22 - ns VCC = 6.0 V 13 6 - 16 - 19 - ns VCC = 2.0 V 100 46 - 125 - 150 - ns VCC = 4.5 V 20 14 - 25 - 30 - ns VCC = 6.0 V 17 10 - 21 - 26 - ns VCC = 2.0 V 100 44 - 125 - 150 - ns VCC = 4.5 V 20 11 - 25 - 30 - ns VCC = 6.0 V 17 9 - 21 - 26 - ns CPR to Qn; see Figure 10 tPLH LOW to HIGH MRC to RCO; see Figure 11 propagation VCC = 2.0 V delay VCC = 4.5 V VCC = 6.0 V ten enable time OE to Qn; see Figure 12 [2] VCC = 6.0 V tdis tW disable time pulse width OE to Qn; see Figure 12 [3] CPC and CPR; HIGH or LOW; see Figure 9 and Figure 10 MRC; LOW; see Figure 11 tsu set-up time CPC to CPR; see Figure 14 CE to CPC; see Figure 13 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 9 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state Table 7. Dynamic characteristics …continued GND (ground = 0 V); for test circuit see Figure 15. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max th hold time recovery time trec maximum frequency fmax power dissipation capacitance [1] Max Min Max CE to CPC; see Figure 13 VCC = 2.0 V 0 - - 0 - 0 - ns VCC = 4.5 V 0 - - 0 - 0 - ns VCC = 6.0 V 0 - - 0 - 0 - ns VCC = 2.0 V 75 28 - 95 - 110 - ns VCC = 4.5 V 15 7 - 19 - 22 - ns VCC = 6.0 V 13 6 - 16 - 19 - ns VCC = 2.0 V 6.6 16 - 5.2 - 4.4 - MHz VCC = 4.5 V 33 52 - 26 - 22 - MHz 39 61 - 31 - 26 - MHz - 44 - - - - - pF MRC to CPC; see Figure 11 CPC or CPR; see Figure 9 and Figure 10 VCC = 6.0 V CPD Min VI = GND to VCC [4] tpd is the same as tPHL, tPLH. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 10 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 11. Waveforms 1/fmax VI CPC input VM GND tW tPLH tPHL VOH RCO output VM VOL 001aac550 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 9. Table 8. Waveforms showing the propagation delays from the counter clock input (CPC) to ripple carry (RCO) output and the CPC pulse width Measurement points Type Input 74HC590 Output VI VM VM VCC 0.5VCC 0.5VCC 1/fmax VI CPR input VM GND tW tPLH tPHL VOH Qn output VM VOL 001aac549 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 10. Waveforms showing the propagation delays from the register clock input (CPR) to output (Qn) and the register clock pulse width 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 11 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state tW VI MRC input VM GND tPLH VOH VM RCO output VOL trec VI VM CPC input GND 001aac551 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 11. Waveforms showing the propagation delays from the master reset counter input (MRC) to output (RCO), the MRC pulse width and recovery time VI OE input VM GND output VCC tPLZ tPZL VM LOW-to-OFF OFF-to-LOW VOL 10 % tPHZ output HIGH-to-OFF OFF-to-HIGH VOH tPZH 90 % VM GND outputs enabled outputs disabled outputs enabled 001aac554 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 12. Waveforms showing the 3-state enable and disable times 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 12 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state VI VM CE input GND tsu th tsu th VOH VM CPC input VOL 001aac553 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 13. Waveforms showing the set-up and hold times for the count enable input (CE) to the counter clock input (CPC) VI VM CPC input GND tsu th VOH VM CPR input VOL 001aac552 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 14. Waveforms showing the set-up and hold times for the counter clock input (CPC) to the register clock input (CPR) 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 13 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 15. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load Switch position VCC VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 2.0 V to 6.0 V VCC 6 ns 50 pF 1 kΩ open GND VCC 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 14 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 16. Package outline SOT38-4 (DIP16) 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 15 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 17. Package outline SOT109-1 (SO16) 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 16 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 18. Package outline SOT403-1 (TSSOP16) 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 17 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 19. Package outline SOT763-1 (DHVQFN16) 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 18 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC590_2 20090428 Product data sheet - 74HC590_1 Modifications: 74HC590_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate. Quick reference data incorporated in to Section 9 and Section 10. Added type number 74HC590N (DIP16 package) 20050330 Product data sheet 74HC590_2 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 19 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC590_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 28 April 2009 20 of 21 74HC590 NXP Semiconductors 8-bit binary counter with output register; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 28 April 2009 Document identifier: 74HC590_2