PHILIPS PCF8579

INTEGRATED CIRCUITS
DATA SHEET
PCF8579
LCD column driver for dot matrix
graphic displays
Product specification
Supersedes data of 1996 Oct 25
File under Integrated Circuits, IC12
1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
Multiplexed LCD bias generation
Power-on reset
Timing generator
Column drivers
Display RAM
Data pointer
Subaddress counter
I2C-bus controller
Input filters
RAM access
Display control
TEST pin
8
I2C-BUS PROTOCOL
8.1
Command decoder
9
CHARACTERISTICS OF THE I2C-BUS
9.1
9.2
9.3
9.4
Bit transfer
Start and stop conditions
System configuration
Acknowledge
1997 Apr 01
2
PCF8579
10
LIMITING VALUES
11
HANDLING
12
DC CHARACTERISTICS
13
AC CHARACTERISTICS
14
APPLICATION INFORMATION
15
CHIP DIMENSIONS AND BONDING PAD
LOCATIONS
16
CHIP-ON GLASS INFORMATION
17
PACKAGE OUTLINES
18
SOLDERING
18.1
18.2
18.3
18.3.1
18.3.2
18.3.3
18.4
Introduction
Reflow soldering
Wave soldering
LQFP
VSO
Method (LQFP and VSO)
Repairing soldered joints
19
DEFINITIONS
20
LIFE SUPPORT APPLICATIONS
21
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
1
2
FEATURES
PCF8579
APPLICATIONS
• LCD column driver
• Automotive information systems
• Used in conjunction with the PCF8578, this device forms
part of a chip set capable of driving up to 40960 dots
• Telecommunication systems
• 40 column outputs
• Computer terminals
• Point-of-sale terminals
• Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32
• Instrumentation.
• Externally selectable bias configuration, 5 or 6 levels
• Easily cascadable for large applications (up to
32 devices)
3
GENERAL DESCRIPTION
The PCF8579 is a low power CMOS LCD column driver,
designed to drive dot matrix graphic displays at multiplex
rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device has
40 outputs and can drive 32 × 40 dots in a 32 row
multiplexed LCD. Up to 16 PCF8579s can be cascaded
and up to 32 devices may be used on the same I2C-bus
(using the two slave addresses). The device is optimized
for use with the PCF8578 LCD row/column driver.
Together these two devices form a general purpose LCD
dot matrix driver chip set, capable of driving displays of up
to 40960 dots. The PCF8579 is compatible with most
microcontrollers and communicates via a two-line
bidirectional bus (I2C-bus). To allow partial VDD shutdown
the ESD protection system of the SCL and SDA pins does
not use a diode connected to VDD. Communication
overheads are minimized by a display RAM with
auto-incremented addressing and display bank switching.
• 1280-bit RAM for display data storage
• Display memory bank switching
• Auto-incremented data loading across hardware
subaddress boundaries (with PCF8578)
• Power-on reset blanks display
• Logic voltage supply range 2.5 to 6 V
• Maximum LCD supply voltage 9 V
• Low power consumption
• I2C-bus interface
• TTL/CMOS compatible
• Compatible with most microcontrollers
• Optimized pinning for single plane wiring in multiple
device applications (with PCF8578)
• Space saving 56-lead plastic mini-pack and 64-pin
plastic low profile quad flat package
• Compatible with chip-on-glass technology
• I2C-bus address: 011110 SA0.
4
ORDERING INFORMATION
TYPE
NUMBER
PCF8579T
PACKAGE
NAME
VSO56
PCF8579U7
−
PCF8579H
LQFP64
1997 Apr 01
DESCRIPTION
plastic very small outline package; 56 leads
VERSION
SOT190
−
chip with bumps on tape
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
3
SOT314-2
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
5
PCF8579
BLOCK DIAGRAM
C39 - C0
17 - 56
(30 to 33, 35 to 64, 1 to 6)
VDD
V3
V4
12 (20)
14 (22)
COLUMN
DRIVERS
15 (23)
(1)
PCF8579
16 (24)
V
LCD
TEST
VSS
6 (12)
OUTPUT
CONTROLLER
5 (11)
Y DECODER
AND SENSING
AMPLIFIERS
32 x 40 BIT
DISPLAY RAM
POWER-ON
RESET
A3
A2
A1
A0
SCL
SDA
8 (14)
9 (16)
10 (17)
11 (18)
DISPLAY
DECODER
X DECODER
(9) 3
SUBADDRESS
COUNTER
RAM DATA POINTER
Y
2 (8)
INPUT
FILTERS
1 (7)
(15, 19, 21, 25 to 29, 34)
13
TIMING
GENERATOR
SYNC
(10) 4
CLK
X
I 2 C-BUS
CONTROLLER
COMMAND
DECODER
7 (13)
MSA919
n.c.
SA0
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
The pin numbers given in parenthesis refer to the LQFP64 package.
Fig.1 Block diagram.
1997 Apr 01
4
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
6
PCF8579
PINNING
PINS
SYMBOL
DESCRIPTION
VSO56
LQFP64
SDA
1
7
I2C-bus serial data input/output
SCL
2
8
I2C-bus serial clock input
SYNC
3
9
cascade synchronization input
CLK
4
10
external clock input
VSS
5
11
ground (logic)
TEST
6
12
test pin (connect to VSS)
SA0
7
13
I2C-bus slave address input (bit 0)
8 to 11
14, 16 to 18
A3 to A0
I2C-bus subaddress inputs
VDD
12
20
supply voltage
n.c.
13(1)
15, 19, 21,25 to 29, 34
not connected
14 and 15
22 and 23
V3, V4
VLCD
C39 to C0
16
24
17 to 56
30 to 33, 35 to 64 and 1 to 6
Note
1. Do not connect, this pin is reserved.
1997 Apr 01
5
LCD bias voltage inputs
LCD supply voltage
LCD column driver outputs
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
SDA
1
56
SCL
2
55 C1
SYNC
3
54
C2
CLK
4
53
C3
V SS
5
52
C4
TEST
6
51
C5
SA0
7
50
C6
A3
8
49
C7
A2
9
48
C8
A1 10
47
C9
A0 11
46
C10
C0
V DD 12
45 C11
n.c. 13
44 C12
V 3 14
43 C13
PCF8579
V 4 15
42 C14
V LCD 16
41 C15
C39 17
40 C16
C38 18
39 C17
C37
19
38 C18
C36
20
37 C19
C35
21
36 C20
C34
22
35 C21
C33
23
34 C22
C32
24
33 C23
C31
25
32 C24
C30
26
31 C25
C29
27
30 C26
C28
28
29 C27
MSA918
Fig.2 Pin configuration (VSO56).
1997 Apr 01
6
Philips Semiconductors
Product specification
49 C21
50 C20
51 C19
52 C18
53 C17
54 C16
PCF8579
55 C15
56 C14
57 C13
58 C12
59 C11
60 C10
61 C9
62 C8
64 C6
handbook, full pagewidth
63 C7
LCD column driver for dot matrix graphic
displays
C5 1
48 C22
C4 2
47 C23
C3 3
46 C24
C2 4
45 C25
C1 5
44 C26
C0 6
43 C27
SDA 7
42 C28
41 C29
SCL 8
PCF8579
Fig.3 Pin configuration (LQFP64).
1997 Apr 01
7
C37 32
33 C36
C38 31
A2 16
C39 30
34 n.c.
n.c. 29
n.c. 15
n.c. 28
35 C35
n.c. 27
A3 14
n.c. 26
36 C34
n.c. 25
SA0 13
VLCD 24
37 C33
V4 23
TEST 12
V3 22
38 C32
n.c. 21
VSS 11
n.c. 19
39 C31
VDD 20
CLK 10
A0 18
40 C30
A1 17
SYNC 9
MBH590
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
7
PCF8579
FUNCTIONAL DESCRIPTION
The PCF8579 column driver is designed for use with the
PCF8578. Together they form a general purpose LCD dot
matrix chip set.
MSA838
1.0
V bias
V2
Vop
Typically up to 16 PCF8579s may be used with one
PCF8578. Each of the PCF8579s is identified by a unique
4-bit hardware subaddress, set by pins A0 to A3.
The PCF8578 can operate with up to 32 PCF8579s when
using two I2C-bus slave addresses. The two slave
addresses are set by the logic level on input SA0.
0.8
V3
0.6
0.4
7.1
V4
Multiplexed LCD bias generation
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (Vth). Vth is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 1 shows the
optimum voltage bias levels for the PCF8578/PCF8579
chip set as functions of Vop (Vop = VDD − VLCD), together
with the discrimination ratios (D) for the different multiplex
rates. A practical value for Vop is obtained by equating
Voff(rms) with Vth. Figure 4 shows the first 4 rows of Table 1
as graphs.
0.2
V5
0
1:8
1:16
1:24
1:32
multiplex rate
Vbias = V2, V3, V4, V5. See Table 1.
Fig.4
Vbias/Vop as a function of the multiplex rate.
Table 1 Optimum LCD bias voltages
MULTIPLEX RATE
7.2
PARAMETER
1:8
1 : 16
1 : 24
1 : 32
V2
--------V op
0.739
0.800
0.830
0.850
V3
--------V op
0.522
0.600
0.661
0.700
At power-on the PCF8579 resets to a defined starting
condition as follows:
1. Display blank (in conjunction with PCF8578)
2. 1 : 32 multiplex rate
3. Start bank, 0 selected
4. Data pointer is set to X, Y address 0, 0
V4
--------V op
0.478
V5
--------V op
0.261
V off ( rms )
----------------------V op
0.297
0.245
0.214
0.193
V on ( rms )
----------------------V op
0.430
0.316
0.263
0.230
V on ( rms )
D = ---------------------V off ( rms )
1.447
1.291
1.230
1.196
V op
--------V th
3.370
4.080
4.680
5.190
1997 Apr 01
Power-on reset
0.400
0.339
5. Character mode
0.300
6. Subaddress counter is set to 0
0.200
0.170
7. I2C-bus is initialized.
0.150
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
8
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
T frame
0
ROW 0
COLUMN
1
2
3
ON
4
5
6
OFF
7
VDD
V2
V3
V4
V5
V LCD
1:8
VDD
V2
V3
V4
V5
V LCD
SYNC
0
ROW 0
COLUMN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDD
V2
V3
V4
V5
V LCD
1:16
VDD
V2
V3
V4
V5
V LCD
SYNC
0
ROW 0
COLUMN
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
VDD
V2
V3
V4
V5
V LCD
1:24
VDD
V2
V3
V4
V5
V LCD
SYNC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ROW 0
COLUMN
VDD
V2
V3
V4
V5
V LCD
1:32
VDD
V2
V3
V4
V5
V LCD
SYNC
MSA841
Fig.5 LCD row/column waveforms.
1997 Apr 01
9
column
display
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
T frame
ROW 1
R1 (t)
VDD
V2
V3
V4
V5
V LCD
ROW 2
R2 (t)
VDD
V2
V3
V4
V5
V LCD
COL 1
C1 (t)
VDD
V2
V3
V4
V5
V LCD
COL 2
C2 (t)
VDD
V2
V3
V4
V5
V LCD
state 1 (OFF)
state 2 (ON)
dot matrix
1:8 multiplex rate
V op
0.261 Vop
V state 1 (t)
0V
0.261 Vop
V op
V op
0.478 Vop
0.261 Vop
V state 2 (t)
0V
0.261 Vop
0.478 Vop
V op
MSA840
V state 1 (t) = C1(t)
Von(rms)
V op
=
1
8
V state 2 (t) = C2(t)
Voff(rms)
V op
=
general relationship (n = multiplex rate)
R1(t):
8
8 (
1
8
1)
= 0.430
R2(t):
2 ( 8 1)
= 0.297
8 ( 8 1) 2
Von(rms)
V op
=
Voff(rms)
=
V op
1
n
n 1
n ( n 1)
2 ( n 1)
n ( n 1) 2
Fig.6 LCD drive mode waveforms for 1 : 8 multiplex rate.
1997 Apr 01
10
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
state 1 (OFF)
state 2 (ON)
T frame
ROW 1
R1 (t)
VDD
V2
V3
V4
V5
V LCD
ROW 2
R2 (t)
VDD
V2
V3
V4
V5
V LCD
COL 1
C1 (t)
VDD
V2
V3
V4
V5
V LCD
COL 2
C2 (t)
dot matrix
1:16 multiplex rate
VDD
V2
V3
V4
V5
V LCD
V op
0.2 Vop
V state 1 (t)
0V
0.2 Vop
V op
V op
0.6 Vop
V state 2 (t)
0.2 Vop
0V
0.2 Vop
0.6 Vop
V op
MSA836
V state 1 (t) = C1(t)
Von(rms)
V op
=
V op
=
Von(rms)
1
16 1
= 0.316
16 16 ( 16 1 )
V state 2 (t) = C2(t)
V off(rms)
general relationship (n = multiplex rate)
R1(t):
V op
R2(t):
=
Voff(rms)
=
V op
2 ( 16 1)
= 0.254
16 ( 16 1 ) 2
1
n
n 1
n ( n 1)
2 ( n 1)
n ( n 1) 2
Fig.7 LCD drive mode waveforms for 1 : 16 multiplex rate.sa.
1997 Apr 01
11
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
7.3
7.10
Timing generator
• Character
• Half-graphic
• Full-graphic.
These modes are specified by bits G1 and G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.8).
Column drivers
Outputs C0 to C39 are column drivers which must be
connected to the LCD. Unused outputs should be left
open-circuit.
7.5
To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.9):
Display RAM
• Device subaddress (specified by the DEVICE SELECT
command)
The PCF8579 contains a 32 × 40-bit static RAM which
stores the display data. The RAM is divided into 4 banks of
40 bytes (4 × 8 × 40 bits). During RAM access, data is
transferred to/from the RAM via the I2C-bus.
7.6
• RAM X-address (specified by the LOAD X-ADDRESS
command)
• RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
Data pointer
Subsequent data bytes will be written or read according to
the chosen RAM access mode. Device subaddresses are
automatically incremented between devices until the last
device is reached. If the last device has subaddress 15,
further display data transfers will lead to a wrap-around of
the subaddress to 0.
The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
data byte or a series of data bytes to be written into, or read
from, the display RAM, controlled by commands sent on
the I2C-bus.
7.7
Subaddress counter
7.11
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage and
retrieval take place only when the contents of the
subaddress counter agree with the hardware subaddress
at pins A0, A1, A2 and A3.
7.8
RAM access
There are three RAM ACCESS modes:
The timing generator of the PCF8579 organizes the
internal data flow from the RAM to the display drivers.
An external synchronization pulse SYNC is received from
the PCF8578. This signal maintains the correct timing
relationship between cascaded devices.
7.4
PCF8579
Display control
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.
The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits
B1 and B0 of the SET START BANK command. This is
shown in Fig.10 This feature is useful when scrolling in
alphanumeric applications.
I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8579 acts as an
I2C-bus slave transmitter/receiver. Device selection
depends on the I2C-bus slave address, the hardware
subaddress and the commands transmitted.
7.12
TEST pin
The TEST pin must be connected to VSS.
7.9
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
1997 Apr 01
12
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PCF8579
driver 1
driver 2
driver k
bank 0
bank 1
RAM
4 bytes
bank 2
bank 3
PCF8579 system RAM
1 k 16
40-bits
1 byte
0
1
2
3
4
5
6
7
8
LSB
9 10 11
character mode
13
MSB
0
2
4
6
8 10 12 14 16 18 20 22
1
3
5
7
9 11 13 15 17 19 21 23
Philips Semiconductors
PCF8579
LCD column driver for dot matrix graphic
displays
1997 Apr 01
PCF8579
2 bytes
half-graphic mode
0
4
8 12 16 20 24 28 32 36 40 44
1
5
9 13 17 21 25 29 33 37 41 45
2
6 10 14 18 22 26 30 34 38 42 46
3
7 11 15 19 23 27 31 35 39 43 47
4 bytes
Fig.8 RAM access mode.
MSA921
Product specification
full-graphic mode
PCF8579
RAM data bytes are
written or read as
indicated above
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bank 0
character mode
bank 1
bank 1
RAM
bank 2
bank 3
LOAD X-ADDRESS: X-address = 8
R/ W
slave address
READ
S
S 0 1 1 1 1 0 A 1 A
DATA
A
14
0
R/W
slave address
S
DEVICE SELECT
LOAD X-ADDRESS
RAM ACCESS
Philips Semiconductors
RAM ACCESS:
LCD column driver for dot matrix graphic
displays
1997 Apr 01
DEVICE SELECT:
subaddress 12
S
0 1 1 1 1 0 A 0 A 1 1 1 0 1 1 0 0 A 1 0 0 0 1 0 0 0 A 0 1 1 1 0 0 0 1 A
0
last command
WRITE
DATA
A
DATA
A
MSA835
Product specification
PCF8579
Fig.9 Example of commands specifying initial data byte RAM locations.
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
RAM
bank 0
top of LCD
bank 1
LCD
bank 2
bank 3
MSA851
Fig.10 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.
1997 Apr 01
15
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
8
In READ mode, indicated by setting the read/write bit
HIGH, data bytes may be read from the RAM following the
slave address acknowlegement. After this
acknowlegement the master transmitter becomes a
master receiver and the PCF8579 becomes a slave
transmitter. The master receiver must acknowledge the
reception of each byte in turn. The master receiver must
signal an end of data to the slave transmitter, by not
generating an acknowledge on the last byte clocked out of
the slave. The slave transmitter then leaves the data line
HIGH, enabling the master to generate a stop
condition (P).
I2C-BUS PROTOCOL
Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8578 and PCF8579. The least
significant bit of the slave address is set by connecting
input SA0 to either logic 0 (VSS) or logic 1 (VDD).
Therefore, two types of PCF8578 or PCF8579 can be
distinguished on the same I2C-bus which allows:
1. One PCF8578 to operate with up to 32 PCF8579s on
the same I2C-bus for very large applications.
2. The use of two types of LCD multiplex schemes on the
same I2C-bus.
Display bytes are written into, or read from, the RAM at the
address specified by the data pointer and subaddress
counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be
transferred either to, or from, the intended devices.
In most applications the PCF8578 will have the same slave
address as the PCF8579.
The I2C-bus protocol is shown in Fig.11.
All communications are initiated with a start condition (S)
from the I2C-bus master, which is followed by the desired
slave address and read/write bit. All devices with this slave
address acknowledge in parallel. All other devices ignore
the bus transfer.
In multiple device applications, the hardware subaddress
pins of the PCF8579s (A0 to A3) are connected to VSS or
VDD to represent the desired hardware subaddress code.
If two or more devices share the same slave address, then
each device must be allocated a unique hardware
subaddress.
In WRITE mode (indicated by setting the read/write bit
LOW) one or more commands follow the slave address
acknowlegement. The commands are also acknowledged
by all addressed devices on the bus.
The last command must clear the continuation bit C. After
the last command a series of data bytes may follow.
The acknowlegement after each byte is made only by the
(A0, A1, A2 and A3) addressed PCF8579 or PCF8578
with its implicit subaddress 0. After the last data byte has
been acknowledged, the I2C-bus master issues a stop
condition (P).
1997 Apr 01
PCF8579
16
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
R/ W
PCF8579
acknowledge
by A0, A1, A2 and A3
selected PCF8578s /
PCF8579s only
acknowledge by
all addressed
PCF8578s / PCF8579s
slave address
S
S 0 1 1 1 1 0 A 0 A C
1 byte
A
COMMAND
0
n
DISPLAY DATA
0 byte(s)
n
P
0 byte(s)
MSA830
(a)
A
update data pointers
and if necessary,
subaddress counter
acknowledge by
all addressed
PCF8578s / PCF8579s
slave address
S
acknowledge
from master
slave address
S
0 1 1 1 1 0 A 0 A C
0
no acknowledge
from master
S
A
COMMAND
n
S 0 1 1 1 1 0 A 1 A
DATA
A
DATA
0
1 byte
n bytes
R/ W
1
P
last byte
R/W
at this moment master
transmitter becomes a
master receiver and
PCF8578/PCF8579 slave
receiver becomes a
slave transmitter
update data pointers
and if necessary
subaddress counter
MSA832
(b)
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge
from master
no acknowledge
from master
slave address
S
S 0 1 1 1 1 0 A 1 A
0
MSA831
R/ W
DATA
n bytes
(c)
A
DATA
1
P
last byte
update data pointers
and if necessary,
subaddress counter
Fig.11 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string
(WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ
mode).
1997 Apr 01
17
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
8.1
PCF8579
Command decoder
MSB
The command decoder identifies command bytes that
arrive on the I2C-bus. The most significant bit of a
command is the continuation bit C (see Fig.12). When this
bit is set, it indicates that the next byte to be transferred will
also be a command. If the bit is reset, it indicates the
conclusion of the command transfer. Further bytes will be
regarded as display data. Commands are transferred in
WRITE mode only.
C
LSB
REST OF OPCODE
MSA833
C = 0; last command.
C = 1; commands continue.
Fig.12 General format of command byte.
The five commands available to the PCF8579 are defined
in Tables 2 and 3.
Table 2 Summary of commands
OPCODE(1)
COMMAND
DESCRIPTION
SET MODE
C
1
0
D
D
D
D
D
multiplex rate, display status, system type
SET START BANK
C
1
1
1
1
1
D
D
defines bank at top of LCD
DEVICE SELECT
C
1
1
0
D
D
D
D
defines device subaddress
RAM ACCESS
C
1
1
1
D
D
D
D
graphic mode, bank select (D D D D ≥ 12 is not allowed;
see SET START BANK opcode)
LOAD X-ADDRESS
C
0
D
D
D
D
D
D
0 to 39
Note
1. C = command continuation bit. D = may be a logic 1 or 0.
1997 Apr 01
18
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
Table 3 Definition of PCF8578/PCF8579 commands
COMMAND
SET MODE
OPCODE
C
1
0
T
OPTIONS
E1 E0 M1 M0 see Table 4
1
DESCRIPTION
defines LCD drive mode
see Table 5
defines display status
see Table 6
defines system type
SET START BANK
C
1
1
1
1
B1 B0 see Table 7
defines pointer to RAM bank
corresponding to the top of the LCD;
useful for scrolling, pseudo motion and
background preparation of new display
DEVICE SELECT
C
1
1
0
A3 A2 A1 A0 see Table 8
four bits of immediate data, bits
A0 to A3, are transferred to the
subaddress counter to define one of
sixteen hardware subaddresses
RAM ACCESS
C
1
1
1
G1 G0 Y1 Y0 see Table 9
defines the auto-increment behaviour of
the address for RAM access
see Table 10 two bits of immediate data, bits Y0 to Y1,
are transferred to the X-address pointer
to define one of forty display RAM
columns
LOAD X-ADDRESS C
1997 Apr 01
0
X5 X4 X3 X2 X1 X0 see Table 11 six bits of immediate data, bits X0 to X5,
are transferred to the X-address pointer
to define one of forty display RAM
columns
19
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
Table 4 Set mode option 1
PCF8579
Table 8 Device select option 1
BITS
DESCRIPTION
LCD DRIVE MODE
M1
M0
1:8
MUX ( 8 rows)
0
1
1 : 16
MUX (16 rows)
1
0
1 : 24
MUX (24 rows)
1
1
1 : 32
MUX (32 rows)
0
0
BITS
Decimal value of 0 to 15
A3
A2
A1
A0
Table 9 RAM access option 1
BITS
RAM ACCESS MODE
Character
Table 5 Set mode option 2
BITS
DISPLAY STATUS
G1
G0
0
0
Half-graphic
0
1
Full-graphic
1
0
Not allowed (note 1)
1
1
E1
E0
Blank
0
0
Note
Normal
0
1
1. See opcode for SET START BANK in Table 3.
All segments on
1
0
Inverse video
1
1
Table 10 RAM access option 2
DESCRIPTION
Table 6 Set mode option 3
Decimal value of 0 to 3
SYSTEM TYPE
Y1
Y0
BIT T
PCF8578 row only
0
PCF8578 mixed mode
1
Table 11 Load X-address option 1
DESCRIPTION
Decimal value of 0 to 39
Table 7 Set start bank option 1
BITS
START BANK POINTER
B1
B0
Bank 0
0
0
Bank 1
0
1
Bank 2
1
0
Bank 3
1
1
1997 Apr 01
BITS
20
BITS
X5 X4 X3 X2 X1 X0
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
9
CHARACTERISTICS OF THE I2C-BUS
9.4
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
9.1
Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the stop condition (P).
9.3
Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
9.2
PCF8579
System configuration
A device transmitting a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message flow is the ‘master’ and the devices
which are controlled by the master are the ‘slaves’.
SDA
SCL
change
of data
allowed
data line
stable;
data valid
Fig.13 Bit transfer.
1997 Apr 01
21
MBA607
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBA608
Fig.14 Definition of start and stop condition.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MBA605
Fig.15 System configuration.
clock pulse for
acknowledgement
START
condition
handbook, full pagewidth
SCL FROM
MASTER
1
2
8
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER
MBA606 - 1
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig.16 Acknowledgement on the I2C-bus.
1997 Apr 01
22
9
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+8.0
V
VLCD
LCD supply voltage
VDD − 11
VDD
V
Vi1
input voltage pins SDA, SCL, SYNC, CLK, TEST, SA0, A0,
A1, A2 and A3
VSS − 0.5
VDD + 0.5
V
Vi2
input voltage pins V3 and V4
VLCD − 0.5
VDD + 0.5
V
Vo1
output voltage pin SDA
VSS − 0.5
VDD + 0.5
V
Vo2
output voltage pins C0 to C39
VLCD − 0.5
VDD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
IDD, ISS, ILCD current at pins VDD, VSS or VLCD
−50
+50
mA
Ptot
total power dissipation per package
−
400
mW
Po
power dissipation per output
−
100
mW
Tstg
storage temperature
−65
+150
°C
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe it is
desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12
under “Handling MOS Devices”.
1997 Apr 01
23
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
12 DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
2.5
−
6.0
VLCD
LCD supply voltage
VDD − 9
−
VDD − 3.5 V
IDD
supply current
fCLK = 2 kHz; note 1
−
9
20
µA
VPOR
power-on reset level
note 2
−
1.3
1.8
V
VSS
−
0.3VDD
V
0.7VDD
−
VDD
V
−1
−
+1
µA
V
Logic
VIL
LOW level input voltage
VIH
HIGH level input voltage
ILI1
leakage current at pins SDA, SCL,
SYNC, CLK, TEST, SA0, A0, A1, A2
and A3
Vi = VDD or VSS
IOL
LOW level output current at pin SDA
VOL = 0.4 V; VDD = 5 V 3
−
−
mA
Ci
input capacitance
note 3
−
−
5
pF
Vi = VDD or VLCD
−2
−
+2
µA
−
±20
−
mV
−
3
6
kΩ
LCD outputs
ILI2
leakage current at pins V3 to V4
VDC
DC component of LCD drivers pins
C0 to C39
RCOL
output resistance at pins C0 to C39
note 4
Notes
1. Outputs are open; inputs at VDD or VSS; I2C-bus inactive; clock with 50% duty factor.
2. Resets all logic when VDD < VPOR.
3. Periodically sampled; not 100% tested.
4. Resistance measured between output terminal (C0 to C39) and bias input (V3, V4, VDD and VLCD) when the specified
current flows through one output under the following conditions (see Table 1):
a) − Vop = VDD − VLCD = 9 V;
b) − V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; ILOAD = 100 µA.
1997 Apr 01
24
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
13 AC CHARACTERISTICS
All timing values are referred to VIH and VIL levels with an input voltage swing of VSS to VDD.
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fclk
clock frequency
50% duty factor
−
note 1
10
kHz
tPLCD
driver delays
VDD − VLCD = 9 V; with test loads
−
−
100
µs
I2C-bus
fSCL
SCL clock frequency
−
−
100
kHz
tSW
tolerable spike width on bus
−
−
100
ns
tBUF
bus free time
4.7
−
−
µs
tSU;STA
START condition set-up time
4.7
−
−
µs
tHD;STA
START condition hold time
4.0
−
−
µs
tLOW
SCL LOW time
4.7
−
−
µs
tHIGH
SCL HIGH time
4.0
−
−
µs
tr
SCL and SDA rise time
−
−
1.0
µs
tf
SCL and SDA fall time
−
−
0.3
µs
tSU;DAT
data set-up time
250
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tSU;STO
STOP condition set-up time
4.0
−
−
µs
repeated start codes only
Note
1. Typically 0.9 to 3.3 kHz.
SDA
1.5 k Ω
VDD
(2%)
1 nF
C0 to C39
MSA916
Fig.17 AC test loads.
1997 Apr 01
25
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
1/ f CLK
0.7 VDD
CLK
0.3 V DD
0.5 V
(V DD
C0 to C39
V LCD = 9 V)
0.5 V
t PLCD
MSA917
Fig.18 Driver timing waveforms.
k, full pagewidth
SDA
t BUF
tf
t LOW
SCL
t
HD;STA
t HD;DAT
tr
t HIGH
t SU;DAT
SDA
MGA728
t SU;STA
Fig.19 I2C-bus timing waveforms.
1997 Apr 01
26
t
SU;STO
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V2
C
R
C
(4 2 3)R
V4
R
R
SA0
VSS
27
VSS
40
columns
unused columns
VSS
VLCD
VLCD
16)
8
PCF8578
(ROW MODE)
V5
C
LCD DISPLAY
rows
V3
C
1:32 multiplex rate
32 x 40 x k dots (k
(20480 dots max.)
32
R
V DD
V DD
SDA SCL CLK SYNC
VSS
V DD
V DD
VLCD
A2
V3
A0
V DD
V DD
A0
A2
V3
A3
V4
VSS SYNC CLK SCL SDA SA0
A3
V4
VSS SYNC CLK SCL SDA SA0
V4
VSS SYNC CLK SCL SDA SA0
VSS
VSS
VSS
1
PCF8579
A1
subaddress k 1
VLCD
V3
R OSC
A0
40
columns
subaddress 1
A1
VLCD
OSC
40
columns
subaddress 0
VSS
2
PCF8579
VSS
k
PCF8579
A1
A2
A3
VSS
Philips Semiconductors
V DD
C
LCD column driver for dot matrix graphic
displays
14 APPLICATION INFORMATION
1997 Apr 01
V DD
V DD
SCL
SDA
MSA845
Product specification
PCF8579
Fig.20 Typical LCD driver system with 1 : 32 multiplex rate.
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SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
V4
2
PCF8579
A1
VLCD
SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
k
V4
PCF8579
A1
V LCD
A0
V DD
subaddress k 1
A0
V DD
40
columns
V DD
28
R
subaddress 1
C
R
V2
16
rows
V3
C
R
C
R
V4
PCF8578
(ROW MODE)
V5
C
R
SA0
V LCD
VLCD
VSS
VSS
LCD DISPLAY
rows
8
40
columns
unused columns
V DD
VSS / V DD
V DD
SDA SCL CLK SYNC
1:16 multiplex rate
16 x 40 x k dots (k
(10240 dots max.)
16)
A0
V DD
V DD
A1
V DD
V4
VLCD
V DD
40
columns
V DD
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
VSS
VSS
VSS
VSS
VLCD
A2
V3
A0
A3
2
PCF8579
A1
subaddress k 1
V3
1
PCF8579
VSS
V DD
40
columns
subaddress 1
A0
1
PCF8579
A0
V DD
subaddress 0
40
columns
subaddress 0
A2
A2
V4
VSS
16)
SA0 SDA SCL CLK SYNC VSS
A3
V3
VLCD
V3
R OSC
1:16 multiplex rate
16 x 40 x k dots (k
(10240 dots max.)
VSS
A1
VLCD
OSC
V DD
40
columns
16
V DD
C
V DD
VSS
Philips Semiconductors
V DD
VSS
LCD column driver for dot matrix graphic
displays
1997 Apr 01
V DD
k
PCF8579
A1
A2
VSS
V DD
SCL
SDA
MSA847
Product specification
PCF8579
Fig.21 Split screen application with 1 : 16 multiplex rate for improved contrast.
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SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
V4
2
PCF8579
A1
VLCD
SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
k
V4
PCF8579
A1
V LCD
A0
V DD
V DD
C
R
C
R
29
rows
V3
PCF8578
(ROW MODE)
V5
C
R
SA0
V LCD
VLCD
VSS
VSS
1:32 multiplex rate
32 x 40 x k dots (k
(20480 dots max.)
16)
1:32 multiplex rate
32 x 40 x k dots (k
(20480 dots max.)
16)
VSS
SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
V4
1
PCF8579
A1
VLCD
A0
V DD
V DD
V DD
40
columns
subaddress 0
32
C
V4
40
columns
32
(4 2 3)R
R
V DD
subaddress 1
LCD DISPLAY
V2
C
A0
V DD
40
columns
subaddress k 1
V DD
V DD
VSS
8
V DD
VSS / V DD
R OSC
40
columns
subaddress 1
A0
V DD
A0
A1
VLCD
A1
VLCD
A2
V3
A2
V3
A3
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
VSS
VSS
VSS
1
PCF8579
VSS
V DD
2
PCF8579
VSS
V DD
V DD
subaddress k 1
VLCD
V4
VSS
40
columns
subaddress 0
V DD
V3
OSC
SDA SCL CLK SYNC
40
columns
unused columns
Philips Semiconductors
V DD
VSS
LCD column driver for dot matrix graphic
displays
1997 Apr 01
V DD
A0
k
PCF8579
A1
A2
VSS
V DD
SCL
SDA
MSA846
Product specification
PCF8579
Fig.22 Split screen application with 1 : 32 multiplex rate.
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SDA
V DD
V
LCD
R0
(4 2 3)R
R
R
R OSC
R
R
n.c.
n.c.
LCD DISPLAY
PCF8578
30
R31/C31
C0
C27
C28
PCF8579
C39
C0
C27
C28
C39
Philips Semiconductors
LCD column driver for dot matrix graphic
displays
1997 Apr 01
VSS
SCL
PCF8579
c.
n.
c.
n.
to other
PCF8579s
PCF8579
Fig.23 Example of single plane wiring, single screen with 1 : 32 multiplex rate (PCF8578 in row driver mode).
Product specification
MSA852
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
15 CHIP DIMENSIONS AND BONDING PAD LOCATIONS
4.76
mm
A3
SA0
TEST
VSS
CLK
SYNC
SCL
SDA
C0
C1
C2
C3
C4
y
8
7
6
5
4
3
2
1
56
55
54
53
52
A2
9
A1
10
A0
11
C5
50
C6
49
C7
48
C8
47
C9
46
C10
VDD
12
n.c.
13
45
C11
V3
14
44
C12
V4
15
43
C13
VLCD
16
42
C14
41
C15
40
C16
39
C17
38
C18
37
C19
36
C20
35
C21
34
C22
0
x
0
25
26
27
28
29
30
31
32
33
C23
24
C24
23
C25
22
C26
21
C27
20
C28
C36
C29
19
C31
C37
C32
18
C33
C38
C34
17
C35
C39
C30
PCF8579
3.02 mm
Chip area: 14.37 mm2.
Bonding pad dimensions: 120 µm × 120 µm.
Gold bump dimensions (if ordered): 94 × 94 × 25 µm.
The numbers given in the square boxes refer to the pad number.
Fig.24 Bonding pad locations.
1997 Apr 01
51
31
MSA920
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
Table 12 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to centre of chip, see Fig.24.
PINS
PAD NUMBER
SYMBOL
x
y
VSO56
LQFP64
1
SDA
252
2142
1
7
2
SCL
48
2142
2
8
3
SYNC
−156
2142
3
9
4
CLK
−360
2142
4
10
5
VSS
−564
2142
5
11
6
TEST
−786
2142
6
12
7
SA0
−1032
2142
7
13
8
A3
−1314
2142
8
14
9
A2
−1314
1920
9
16
10
A1
−1314
1716
10
17
11
A0
−1314
1512
11
18
12
VDD
−1314
708
12
20
13
n.c.
−1314
504
13
21
14
V3
−1314
300
14
22
15
V4
−1314
96
15
23
16
VLCD
−1314
−108
16
24
17
C39
−1314
−1308
17
30
18
C38
−1314
−1512
18
31
19
C37
−1314
−1716
19
32
20
C36
−1314
−1920
20
33
21
C35
−1314
−2142
21
35
22
C34
−1032
−2142
22
36
23
C33
−786
−2142
23
37
24
C32
−564
−2142
24
38
25
C31
−360
−2142
25
39
26
C30
−156
−2142
26
40
27
C29
48
−2142
27
41
28
C28
252
−2142
28
42
29
C27
498
−2142
29
43
30
C26
702
−2142
30
44
31
C25
906
−2142
31
45
32
C24
1110
−2142
32
46
33
C23
1314
−2142
33
47
34
C22
1314
−1830
34
48
35
C21
1314
−1570
35
49
36
C20
1314
−1326
36
50
37
C19
1314
−1122
37
51
1997 Apr 01
32
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
PINS
PAD NUMBER
SYMBOL
x
y
VSO56
LQFP64
38
C18
1314
−918
38
52
39
C17
1314
−714
39
53
40
C16
1314
−510
40
54
41
C15
1314
−306
41
55
42
C14
1314
−102
42
56
43
C13
1314
102
43
57
44
C12
1314
306
44
58
45
C11
1314
510
45
59
46
C10
1314
714
46
60
47
C9
1314
918
47
61
48
C8
1314
1122
48
62
49
C7
1314
1326
49
63
50
C6
1314
1566
50
64
51
C5
1314
1830
51
1
52
C4
1314
2142
52
2
53
C3
1110
2142
53
3
54
C2
906
2142
54
4
55
C1
702
2142
55
5
56
C0
498
2142
56
6
−
n.c.
−
−
−
15, 19, 21,
25 to 29, 34
1997 Apr 01
33
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VSS
CLK
SYNC
SCL
SA
O
R
O
SC
0
SC
SDA
A2
A1
A0
0
D
LK
C
c.
N
2
SC
R
CLK
L
n.
1
SY
R
VSS
V
D
V
V 5
LC
D
ST
0
C
S
VS
A
R
V4
VLCD
TE
SD
V
4
SA
C
V
V 2
3
LK
C
V
D
A3
D
ST
TE
S
VS
N
SY
L
SC
V3
A
V
3
SD
SYNC
0
V
V 4
LC
D
C
SCL
1
C
C
38
C
39
SDA
C
37
C
38
39
34
C
Philips Semiconductors
V4
VLCD
LCD column driver for dot matrix graphic
displays
VDD
V3
16 CHIP-ON GLASS INFORMATION
1997 Apr 01
VDD
PCF8578
PCF8579
R0 to R31
C0
C1
C2
If inputs SA0 and A0 to A3 are left unconnected they are internally pulled-up to VDD.
Fig.25 Typical chip-on glass application (viewed from underside of chip).
PCF8579
MSA850
Product specification
LCD
DISPLAY
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
17 PACKAGE OUTLINES
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
HE
v M A
Z
56
29
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
detail X
28
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
3.3
0.3
0.1
3.0
2.8
0.25
0.42
0.30
0.22
0.14
21.65
21.35
11.1
11.0
0.75
15.8
15.2
2.25
1.6
1.4
1.45
1.30
0.2
0.1
0.1
0.90
0.55
0.13
0.012
0.004
0.12
0.11
0.01
0.017 0.0087 0.85
0.012 0.0055 0.84
inches
0.44
0.62
0.0295
0.43
0.60
0.063
0.089
0.055
0.057
0.035
0.008 0.004 0.004
0.051
0.022
θ
Note
1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
96-04-02
97-08-11
SOT190-1
1997 Apr 01
EUROPEAN
PROJECTION
35
o
7
0o
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
wM
θ
bp
pin 1 index
64
Lp
L
17
detail X
16
1
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
1.45
1.05
7
0o
1.45
1.05
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-12-19
97-08-01
SOT314-2
1997 Apr 01
EUROPEAN
PROJECTION
36
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
18 SOLDERING
18.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
18.3.2
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP and
VSO packages.
• The package footprint must incorporate solder thieves at
the downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
18.3.3
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
18.3.1
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
LQFP
18.4
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
1997 Apr 01
METHOD (LQFP AND VSO)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
18.3
VSO
Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
18.2
PCF8579
37
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
19 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Apr 01
38
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
NOTES
1997 Apr 01
39
PCF8579
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/03/pp40
Date of release: 1997 Apr 01
Document order number:
9397 750 01757