INTEGRATED CIRCUITS DATA SHEET TDA5153 Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads Preliminary specification File under Integrated Circuits, IC11 1997 Jul 02 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.10.5 8.10.5.1 8.10.5.2 8.10.5.3 8.10.6 8.10.7 8.10.8 8.10.9 8.10.10 8.11 8.12 Read mode Write mode Sleep mode Standby mode Active mode Bi-directional serial interface Addressing Programming data Reading data Operation of the serial interface Configuration Power control Head select Servo write Test MR head test Temperature monitor Thermal asperity detector Write amplifier programmable capacitors High frequency gain attenuator pole register High frequency gain boost register Settle pulse Address registers Head unsafe HUS survey 9 LIMITING VALUES 10 HANDLING 11 THERMAL RESISTANCE 12 RECOMMENDED OPERATION CONDITIONS 13 CHARACTERISTICS 14 PACKAGE OUTLINE 15 SOLDERING 16 DEFINITION 17 LIFE SUPPORT APPLICATIONS 1997 Jul 02 2 TDA5153 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 1 FEATURES 3 • Designed for 4 (TDA5153BG) or 6 dual-stripe MR-read/inductive write heads • Single supply voltage (5.0 V ±10%); a separate write drivers supply pin can be biased from VCC to 8 V +10% • MR elements connected to ground (GND) • Equal bias currents in the two MR stripes of each head • On-chip AC couplings eliminate MR head DC offset • 3-wire serial interface for programming The IC incorporates read amplifiers, write amplifiers, serial interface, digital-to-analog converters, reference and control circuits which operate on a single supply voltage of 5 V ±10%. The output drivers have a separate supply voltage pin which can be connected to a higher supply voltage of up to 8 V +10%. The complementary output stages of the write amplifier allow writing with near rail-to-rail peak voltages across the inductive write head. • Programmable high-frequency zero-pole gain boost • Programmable write driver compensation capacitance • Programmable MR bias currents and write currents • 1-bit programmable read gain • Sleep, standby, active and test modes available • Measurement of head resistances in test mode • In test mode, one MR bias current may be forced to a minimum current The read amplifier has a low input impedance. The DC offset between the two stripes of the MR head is eliminated using on-chip AC coupling. Fast settling features are used to keep the transients short. As an option, the read amplifier may be left biased during writing so as to reduce the duration of these transients even more. Series inductance in the leads between the amplifier and MR heads influences the bandwidth which can be compensated by using a programmable high-frequency gain-boost (HF zero). HF noise and bandwidth can be attenuated using a programmable high-frequency gain-attenuator (HF pole). • Short write current rise and fall times with near rail-to-rail voltage swing • Head unsafe pin for signalling of abnormal conditions and behaviour • Low supply voltage write-current inhibit (active or inactive) • Supports servo writing • Provides temperature monitor • Thermal asperity detection with programmable threshold level On-chip digital-to-analog converters for MR bias currents and write currents are programmed via a 3-wire serial interface. Head selection, mode control, testing and servo writing can also be programmed using the serial interface. In sleep mode the CMOS serial interface is operational. Figure 1 shows the block diagram of the device. • Requires only one external resistor. APPLICATIONS • Hard Disk Drive (HDD). 4 GENERAL DESCRIPTION The 5.0 V pre-amplifier for HDD described here is designed for five terminals, dual stripe Magneto-Resistive (MR)-read/inductive-write heads. The disks of the disk drive are connected to ground. To avoid voltage break-through between the heads and the disk, the MR elements of the heads are also connected to ground. The symmetry of the dual-stripe head-amplifier combination automatically distinguishes between the differential signals such as signals and the common-mode effects like interference. The latter are rejected by the amplifier. • Current bias-current sense architecture 2 TDA5153 ORDERING INFORMATION TYPE NUMBER TDA5153X TDA5153AG; TDA5153BG 1997 Jul 02 PACKAGE NAME − LQFP48 DESCRIPTION VERSION − naked die plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm 3 SOT313-2 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 5 TDA5153 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage 4.5 5.0 5.5 V VCC(WD) write drivers supply voltage VCC 8.0 8.8 V F noise figure RMR = 28 Ω; IMR = 10 mA; Tamb = 25 °C; f = 20 MHz − 3.0 3.2 dB Vnir input referred noise voltage; see RMR = 28 Ω; IMR = 10 mA; note 3 in Chapter 13 Tamb = 25 °C; f = 20 MHz − 0.9 1.0 nV/√Hz Gv(dif) differential voltage gain d4 = logic 0 − 160 − d4 = logic 1 − 226 − from head inputs to RDx, RDy; RMR = 28 Ω; IMR = 10 mA B−3 db −3 dB frequency bandwidth upper bandwidth without gain boost (4 nH lead inductance) − 220 − MHz CMRR common mode rejection ratio; RMR mismatch <5% IMR = 10 mA; f < 1 MHz − 45 − dB IMR = 10 mA; f < 100 MHz − 25 − dB power supply rejection ratio (input referred); RMR mismatch <5% f < 1 MHz − 80 − dB f < 100 MHz − 50 − dB VCC(WD) = 8.0 V − − 1.8 ns VCC(WD) = 6.5 V − − 2.1 ns Rext = 10 kΩ 5 − 20.5 mA Rext = 10 kΩ 20 − 51 mA − − 25 MHz PSRR tr, tf IMR(PR) rise/fall times (10% to 90%) programming MR bias current IWR(PR)(b-p) programming write current range (base-to-peak) fSCLK 1997 Jul 02 Lh = 150 nH; IWR = 35 mA; f = 20 MHz serial interface clock rate 4 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 6 TDA5153 BLOCK DIAGRAM VCC(WD) VCC handbook, full pagewidth (5 to 8 V) 48 11 WDlx WDly TDA5153 2 6(3) 3 WRITE DRIVER INPUT IWDlx(1) FF 6(3) IWDly(1) HUS 1 15(2), 20, 26, 33, 39, 44(2) 14(2), 19, 25, 32, 38, 43(2) nWy nWx HEAD UNSAFE INDICATOR 6(3) LOW SUPPLY VOLTAGE INDICATOR Rext WRITE CURRENT SOURCE 12 WRITE DRIVER AND READ PREAMP (6×)(3) VOLTAGE REFERENCE +VCC R/W SCLK SEN SDATA TAS DETECTOR 4 7 5 SERIAL INTERFACE 4 20 kΩ head select 5 3 6 6(3) RMR CURRENT SOURCE 5 4 6(3) 18(2), 23, 29, 36, 42, 47(2) 4 9 6(3) RDx RDy 17(2), 22, 28, 35, 41, 46(2) 10 6(3) 16(2), 21, 27, 34, 40, 45(2) 8, 13 MGK422 GND n Pin numbers correspond to TDA5153AG and TDA5153BG only. See Fig.3 and Chapter 7 for pinning of TDA5153X. (1) Only available on naked die. (2) Absent on TDA5153BG (4 channel version). (3) 4 on TDA5153BG. Fig.1 Block diagram. 1997 Jul 02 5 nRy nGND nRx Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 7 TDA5153 PINNING PIN PAD SYMBOL DESCRIPTION TDA5153AG TDA5153BG TDA5153X HUS 1 1 1 head unsafe output WDIx 2 2 2 write data input (differential; voltage input) WDIy 3 3 3 write data input (differential; voltage input) IWDIx − − 4 write data input (differential; current input) IWDIy − − 5 write data input (differential; current input) R/W 4 4 6 read/write (read = HIGH; write = LOW) SEN 5 5 7 serial bus enable SDATA 6 6 8 serial bus data SCLK 7 7 9 serial bus clock GND1 8 8 10 ground connection 1 RDx 9 9 11 read data output (differential x − y) RDy 10 10 12 read data output (differential x − y) GND3 − − 13 ground connection 3 VCC 11 11 14 supply voltage Rext 12 12 15 10 kΩ external resistor GND2 13 13 16 ground connection 2 0Wx 14 − 17 inductive write head connection for head H0 (differential x − y) 0Wy 15 − 18 inductive write head connection for head H0 (differential x − y) 0Rx 16 − 19 MR-read head connection for head H0 (differential x − y) 0GND 17 − 20 ground connection for head H0 0Ry 18 − 21 MR-read head connection for head H0 (differential x − y) n.c. − 14 − not connected n.c. − 15 − not connected n.c. − 16 − not connected n.c. − 17 − not connected n.c. − 18 − not connected 1Wx 19 19 22 inductive write head connection for head H1 (differential x − y) 1Wy 20 20 23 inductive write head connection for head H1 (differential x − y) 1Rx 21 21 24 MR-read head connection for head H1 (differential x − y) 1GND 22 22 25 ground connection for head H1 1Ry 23 23 26 MR-read head connection for head H1 (differential x − y) n.c. 24 24 − not connected 2Wx 25 25 27 inductive write head connection for head H2 (differential x − y) 2Wy 26 26 28 inductive write head connection for head H2 (differential x − y) 2Rx 27 27 29 MR-read head connection for head H2 (differential x − y) 2GND 28 28 30 ground connection for head H2 2Ry 29 29 31 MR-read head connection for head H2 (differential x − y) n.c. 30 30 − not connected 1997 Jul 02 6 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads PIN TDA5153 PAD SYMBOL DESCRIPTION TDA5153AG TDA5153BG TDA5153X n.c. 31 31 − not connected 3Wx 32 32 32 inductive write head connection for head H3 (differential x − y) 3Wy 33 33 33 inductive write head connection for head H3 (differential x − y) 3Rx 34 34 34 MR-read head connection for head H3 (differential x − y) 3GND 35 35 35 ground connection for head H3 3Ry 36 36 36 MR-read head connection for head H3 (differential x − y) n.c. 37 37 − not connected 4Wx 38 38 37 inductive write head connection for head H4 (differential x − y) 4Wy 39 39 38 inductive write head connection for head H4 (differential x − y) 4Rx 40 40 39 MR-read head connection for head H4 (differential x − y) 4GND 41 41 40 ground connection for head H4 4Ry 42 42 41 MR-read head connection for head H4 (differential x − y) 5Wx 43 − 42 inductive write head connection for head H5 (differential x − y) 5Wy 44 − 43 inductive write head connection for head H5 (differential x − y) 5Rx 45 − 44 MR-read head connection for head H5 (differential x − y); 5GND 46 − 45 ground connection for head H5 5Ry 47 − 46 MR-read head connection for head H5 (differential x − y) n.c. − 43 − not connected n.c. − 44 − not connected n.c. − 45 − not connected n.c. − 46 − not connected n.c. − 47 − not connected VCC(WD) 48 48 47 supply voltage for the write drivers GND4 − − 48 ground connection 4 1997 Jul 02 7 Philips Semiconductors Preliminary specification HUS 37 n.c. 36 3Ry 1 WDIx 2 35 3GND WDIy 3 34 3Rx R/W 4 33 3Wy SEN 5 32 3Wx SDATA 6 31 n.c. TDA5153AG SCLK 7 30 n.c. GND1 8 29 2Ry RDx 9 28 2GND RDy 10 27 2Rx n.c. 24 1Ry 23 MGK424 37 n.c. 38 4Wx 1Rx 21 1GND 22 39 4Wy 40 4Rx 1Wx 19 1Wy 20 41 4GND 42 4Ry 0Ry 18 43 n.c. 0Rx 16 0GND 17 44 n.c. 45 n.c. 46 n.c. 47 n.c. 48 VCC(WD) HUS 0Wy 15 25 2Wx 0Wx 14 26 2Wy Rext 12 GND2 13 VCC 11 handbook, full pagewidth 36 3Ry 1 WDIx 2 35 3GND WDIy 3 34 3Rx R/W 4 33 3Wy SEN 5 32 3Wx SDATA 6 31 n.c. TDA5153BG SCLK 7 30 n.c. GND1 8 29 2Ry RDx 9 28 2GND 8 n.c. 24 1Ry 23 1GND 22 1Rx 21 1Wy 20 1Wx 19 n.c. 18 n.c. 17 25 2Wx n.c. 16 Rext 12 n.c. 15 26 2Wy n.c. 14 27 2Rx GND2 13 RDy 10 VCC 11 Fig.2 Pin configurations. 1997 Jul 02 38 4Wx 39 4Wy 40 4Rx TDA5153 41 4GND 42 4Ry 43 5Wx 44 5Wy 45 5Rx 46 5GND handbook, full pagewidth 47 5Ry 48 VCC(WD) Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads MGK420 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads VCC(WD) 5Ry 5GND 5Rx 5Wy 5Wx 4Ry 4GND 4Rx 4Wy 4Wx 47 46 45 44 43 42 41 40 39 38 37 handbook, full pagewidth GND4 TDA5153 48 36 3Ry HUS 1 35 3GND WDIx 2 34 3Rx WDIy 3 33 3Wy IWDIx 4 32 3Wx IWDIy 5 R/W 6 SEN 7 SDATA 8 SCLK 9 GND1 10 RDx 11 31 2Ry RDy 12 30 2GND GND3 13 29 2Rx 28 2Wy 27 2Wx 25 Fig.3 TDA5153X pad configuration. 1997 Jul 02 9 26 1Ry 24 1GND 23 1Rx 22 1Wy 21 1Wx 20 0Ry 19 0GND 18 0Rx 17 0Wy Rext 14 16 15 0Wx VCC GND2 TDA5153X MGK421 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8 8.1 read, sleep and standby modes. In write mode, a programmable current is forced through the selected two terminals inductive write head. The push-pull output drivers yield near rail-to-rail voltage swing for fast current polarity switching. FUNCTIONAL DESCRIPTION Read mode The read mode disables the write circuitry to save power while reading. The read circuitry is de-activated for write, sleep and standby modes. The read circuitry may also be biased during write mode to shorten transients. The selected head is connected to a multiplexed low-noise read amplifier. The read amplifier has low-impedance inputs nRx and nRy (n is the number of the head) and low-impedance outputs RDx and RDy. The signal polarity is non-inverting from x and y inputs to x and y outputs. The differential write data input WDIx − WDIy is PECL (Positive Emitter Coupled Logic) compatible. The write data flip-flop can either be used or passed-by. In the case that the write data flip-flop is used, current polarity is toggled at the falling edges of the Vdata = VWDIx − VWDIy. Switching to Write Mode initializes the data flip-flop so that the write current flows in the write head from x to y. In the case that the write data flip-flop is not used, the signal polarity is non-inverting from x and y inputs to x and y outputs. Ambient magnetic fields at the MR elements result in a relative change in MR resistance ∆R MR ---------------R MR The write current magnitude is controlled through on-chip DACs. The write current is defined as follows: 10 kΩ I WR = ---------------- ( 20 + 16 ⋅ d4 + 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + d0 ) R ext This change produces a current variation ∆R MR ∆I MR = I MR × ---------------- , R MR (in mA) where d4 to d0 are bits (either logic 0 or logic 1). The adjustable range of the write current is 20 mA to 51 mA. At power-up, the default values d4 = d3 = d2 = d1 = d0 = logic 0 are initialized, corresponding to IWR = 20 mA. IWR is the current provided by the write drivers: the current in the write coil and in the damping resistor together. The static current in the write coil is I WR ----------------- , R 1 + ------hRd where IMR is the bias current in the MR element. The current variation is amplified to form the read data output signal voltage, which is available at RDx − RDy. AC coupling between MR elements and amplifier stages prevents the amplifier input stages from overload by DC voltages across the MR elements. A fast settling procedure shortens DC settling transients. An on-chip generated stable temperature reference voltage (1.32 V), available at the Rext pin, is dropped across an external resistor (10 kΩ) to form a global reference current for the write and the MR bias currents. The MR bias current DACs are programmed through the serial interface according to the following formula 10 kΩ I MR = ------------------- ( 10 + 16 ⋅ d4 + 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + d0 ) 2 ⋅ R ext where Rh is the resistance of the coil including leads and Rd is the damping resistor. 8.3 Write mode To minimize power dissipation, the read circuitry may be disabled in write mode. The write circuitry is disabled in 1997 Jul 02 Sleep mode In sleep mode, the device is accessible via the serial interface. All circuits are inactive, except the circuits of the CMOS serial interface and the circuit which forces the data registers to their default values at power-up and which fixes the DC level of RDx − RDy (required when operating with more than one amplifier). Typical static current consumption is −30 µA. Dynamic current consumption during operation of the serial interface in the sleep mode and owing to external activity at the inputs to the serial interface is not included. In all modes including the sleep mode, data registers can be programmed. Sleep is the default mode at power-up. Switching to other modes takes less than 0.1 ms. (in mA), where d4 to d0 are bits (either logic 0 or logic 1). At power-up, all bits are set to logic 0, which results in a default MR current of 5 mA. The adjustable range of the MR currents is 5 mA to 20.5 mA. The MR bias currents are equal for the two stripes of each head. The gain amplifier is 1-bit programmable. The amplifier gain can be set to its nominal value or to the nominal value +3 dB. 8.2 TDA5153 10 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.4 8.7 Standby mode Active mode Active mode is either read mode or write mode depending on the R/W pin. 8.6 If bit a0 = logic 0, a programming sequence starts. If bit a0 = logic 1, reading data from the pre-amplifier can start. Bi-directional serial interface The serial interface is used for programming of the device and for reading of status information. 16 bits (8 bits for data and 8 for address) are used to program the device. The serial interface requires 3 pins: SDATA, SCLK and SEN. These pins (and R/W) are CMOS inputs. The logic input R/W has an internal 20 kΩ pull-up resistor and the SEN logic input has an internal 20 kΩ pull-down resistor. Thus, in case the SEN line is opened, no data will be registered and in case the R/W line is opened, the device will never be in write mode. 8.8 Programming data If a0 = logic 0, the last eight bits d7 to d0 before SEN goes LOW are shifted into an input register. Bits d6 and d7 are don’t care. When SEN goes LOW, the communication sequence is ended and the data in the input register is copied in parallel to the data register that corresponds to the decoded address a7 to a4. SEN should go LOW at least 5 ns after the last rising edge of SCLK. 8.9 SDATA: serial data; bi-directional data interface. In all circumstances, the LSB is transmitted first. Reading data Immediately after the IC detects that a0 = logic 1, data from the data register (address a7 to a4) is copied in parallel to the input register. Two wait clock cycles must follow before the controller can start inputting data. At the first falling edge of SCLK after the 2 wait rising edges of SCLK, the LSB d0 is placed on SDATA line followed by d1 at the next falling edge of SCLK etc. If SEN goes LOW before 8 address bits (a7 to a0) have been detected, the communication is ignored. SCLK: serial clock; 25 MHz clock frequency. SEN: serial enable; data transfer takes place when SEN is HIGH. When SEN is LOW, data and clock signals are prohibited from entering the circuit. Three phases in the communication are distinguishable: addressing, programming and reading. Each communication sequence starts with an addressing phase, followed by either a programming phase or a reading phase. 1997 Jul 02 Addressing When SEN goes HIGH, bits are latched in at rising edges of SCLK. The first eight bits a7 to a0, starting with a0, are shifted serially into an address register. If SEN goes LOW before 16 bits have been received, the operation is ignored. When more than 16 bits (address and data) are latched in before SEN goes LOW, the first 8 bits are interpreted as an address and the last 8 bits as data. SEN should go HIGH at least 5 ns before the first rising edge of SCLK. Data should be valid at least 5 ns before and after a rising edge of SCLK. The bits a7 to a4 constitute the register address.To validate the communication with the preamplifier, bits a1, a2 and a3 have to be programmed as (1, 0, 0). The circuit can be put in standby mode using the serial interface. In standby mode, typical DC current consumption is 330 µA. Transients from standby mode to active mode are two orders of magnitude shorter than from sleep mode to active mode. This is important in the case of cylinder mode operation with multiple amplifiers. All amplifiers can operate from standby mode and all head switch times can be kept just as short as in the case of operation with a single amplifier. Head switching times are summarized in the switching characteristics. 8.5 TDA5153 11 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5153 >5 ns handbook, full pagewidth >5 ns SEN , , ,, ,, SCLK SDATA 0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 address d4 d5 d6 d7 data MGK423 Fig.4 Timing diagram of the serial interface operation; writing sequence (a0 = 0). handbook, full pagewidth SEN ,, ,, SCLK SDATA 1 a1 a2 a3 a4 address a5 a6 ,, ,, a7 wait cycles d0 d1 d2 d3 data ,, ,, d4 d5 MGK419 Fig.5 Timing diagram of the serial interface operation; reading sequence (a0 = 1). 1997 Jul 02 12 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.10 8.10.1 If d1 = d0 = logic 1, the circuit goes in active mode, (read or write mode depending on the R/W input). Operation of the serial interface CONFIGURATION 8.10.3 d0 By default (d0 = logic 0), write data passes from the write data input via the data flip-flop to the write driver. The write driver toggles the current in the head at the falling edges of V WDIx – V WDIy V data = ------------------------------------2 When d0 = logic 1, the flip-flop is not used. The signal polarity is non-inverting from WDIx and WDIy to Wx and Wy. 8.10.4 SERVO WRITE The circuit is prepared for servo writing. However, the chip will not be guaranteed. 8.10.5 TEST d2 = d1 = d0 = logic 0. The circuit is not in test mode. This is the default situation. By default (d1 = logic 0) the pre-amplifier senses PECL write signals at WDIx and WDIy. d1 should remain logic 0. 8.10.5.1 MR head test d2 = logic 0, d1 = logic 0, d0 = logic 1. In read mode, the voltages at Rx and Ry (at the top of the MR elements) of the selected head are fed to RDx and RDy outputs. By measuring the output voltages single-ended at two different IMR currents, the MR resistance can be accurately measured according to the following formula: V RDx1 – V RDx2 R MRx = -------------------------------------- for the x side for instance. I MRx1 – I MRx2 d2 By default, (d2 = logic 0) the write current is inhibited under low supply voltage conditions. The write current inhibit is made inactive by programming d2 to logic 1. d3 By default (d3 = logic 0), in write mode low supply voltage, open head, and other conditions are monitored and flagged at HUS. If d3 = logic 1, HUS is LOW in write mode and HIGH in read mode. Open head and head short-circuited to ground conditions can therefore be detected. d4 d2 = logic 0, d1 = logic 1, d0 = logic 0. Same as before, with the difference that IMR2 is fixed to a minimum constant value of 5 mA. Measuring in the same way as above with IMR1 > 5 mA, enables the detection of MR elements connected together. The amplifier read gain may be programmed in the configuration register. By default (d4 = logic 0), the read gain is typically 160 with RMR = 28 Ω. If d4 = logic 1, the read amplifier typical gain is 3 dB higher (i.e. 226 if RMR = 28 Ω). d5 8.10.5.2 In order to minimize the write-to-read recovery times, the first stage of the read amplifier may be kept biased during write mode. By default, (d5 = logic 0) the read amplifier is powered-down during write mode, and the fast settling procedure is activated after write-to-read switching. If d5 = logic 1 the read amplifier is kept biased during write mode, and the fast settling procedure still occurs if the head is changed or the MR current is re-programmed. Temperature monitor d2 = logic 0, d1 = logic 1, d0 = logic 1. The temperature monitor voltages are connected to RDx and RDy. The output differential voltage depends on the temperature according to: dV = – 0.00364 × T + 1.7 , 0 < T < 140 °C The temperature may be measured with a typical precision of 5 °C. POWER CONTROL By default d0 = d1 = logic 0, the pre-amplifier powers-up in sleep mode. If d1 = logic 0, d0 = logic 1 or d1 = logic 1, d0 = logic 0 the circuit goes in standby mode. 1997 Jul 02 HEAD SELECT d2, d1 and d0 are used to select head H0 to H5 for the 6 channel version and to select head H1 to H4 for the 4 channel version. d1 8.10.2 TDA5153 13 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.10.5.3 TDA5153 attenuator provides a pole which limits the bandwidth and reduces the high-frequency noise. The HF pole can be used in combination with the HF zero in order to boost the HF gain locally and yet limit the very high frequency noise enhancement. Thermal asperity detector d2 = logic 1, d1 = don’t care, d0 = either logic or 1. Unlike the above tests, the thermal asperity detection does not use the RDx to RDy outputs. Thus, the reader is fully operational. In case a thermal asperity is detected, it is flagged at the HUS pin. 8.10.8 HIGH FREQUENCY GAIN BOOST REGISTER The threshold voltage for the thermal asperity detection is 2-bit programmable. These 2 bits consist of d0 (LSB) of the test mode register (address = 0XXX0110), as the MSB, and b2 of the compensation register (address = 0XXX0111). V th = ( 210 + 560 ⋅ d0 + 280 ⋅ b2 ) µV , By default (d3 = d2 = d1 = d0 = logic 0), the high frequency gain boost is not active. The gain boost provides a zero which allows to optimize the bandwidth of the read amplifier and to correct for attenuation caused by series inductances in the leads between the MR-heads and the read amplifier inputs. where d0 is d0 of test mode register and b2 is d2 of capacitor compensation register. 8.10.9 8.10.6 By default (d2 = d1 = d0 = logic 0) the settle pulse has a nominal duration of 3 µs. Its value can be programmed from 2.125 µs to 3 µs according to the following formula: 1 t st = 2 + -------------------------------------------------------------------------- µs ( 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 + 1 ) WRITE AMPLIFIER PROGRAMMABLE CAPACITORS By default (d2 = d1 = d0 = logic 0) the programmable capacitors are zero. These capacitors are used to improve the performance of the write amplifier according to the write amplifier output load. 8.10.7 SETTLE PULSE HIGH FREQUENCY GAIN ATTENUATOR POLE REGISTER By default (d3 = d2 = d1 = d0 = logic 0), the high frequency gain attenuator is not active. The gain 8.10.10 ADDRESS REGISTERS; note 1 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 1 0 DESCRIPTION configuration register: d0 = 0: use data flip-flop; d0 = 1: by-pass data flip-flop d1 = 0: the WDI inputs are PECL levels; d1 = 1: invalid d2 = 0: write current inhibit active; d2 = 1: write current inhibit inactive read mode: d3 = 0: HUS active; d3 = 1: HUS HIGH write mode: d3 = 0: HUS active; d3 = 1: HUS LOW d4 = 0: read gain nominal; d4 = 1: read gain nominal + 3 dB d5 = 0: read amplifier OFF during write mode; d5 = 1: read amplifier ON during write mode 0 0 0 1 0 0 1 0 power control register: (d1, d0) = (0, 0): sleep mode (d1, d0) = (1, 0) or (0, 1): standby mode (d1, d0) = (1, 1): active mode (write or read) 0 0 1 0 0 0 1 0 head select register: 6 channels: (d2,d1,d0) = (0,0,0) to (1,0,1): H0 to H5 4 channels: (d2,d1,d0) = (0, 0, 1) to (1, 0, 0): H1 to H4 1997 Jul 02 14 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads A7 A6 A5 A4 A3 A2 A1 A0 TDA5153 DESCRIPTION 0 0 1 1 0 0 1 0 MR current DAC register: 10 kΩ I MR = 0.5 × ---------------- × ( 10 + 16 ⋅ d4 + 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 ) mA R ext 0 1 0 0 0 0 1 0 write current DAC register: 10 kΩ I WR = ---------------- × ( 20 + 16 ⋅ d4 + 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 ) mA R ext 0 1 0 1 0 0 1 0 servo write register: (d0, d1) = (0, 0) = one head (d0, d1) = (1, 1) = all heads 0 1 1 0 0 0 1 0 test mode register: (d2,d1,d0) = (0,0,0) = not in test mode (d2,d1,d0) = (0,0,1) = read head test (IMR1 = IMR2) (d2,d1,d0) = (0,1,0) = read head test (IMR2 = 5 mA fixed) (d2,d1,d0) = (0,1,1) = temperature monitor (d2,d1,d0) = (1, X, d0) = thermal asperity detection V th = ( 210 + 560 ⋅ d0 + 280 ⋅ b2 ) µV , see note 2 0 1 1 1 0 0 1 0 compensation capacitor register: equivalent differential capacitance: ( 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 ) × 2 pF 1 0 0 0 0 0 1 0 high frequency gain attenuator register: 800 MHz nominal pole frequency: ------------------------------------------------------------------------------8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 1 0 0 1 0 0 1 0 high-frequency gain boost register: 800 MHz nominal zero frequency: ------------------------------------------------------------------------------8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 1 0 1 0 0 0 1 0 settle time register: 1 settle time: t st = 2 + -------------------------------------------------------------------------- µs ( 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 + 1 ) 1 1 1 1 0 0 1 1 chip ID register: ID = 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 , d3 to d0 are preset to (0, 0, 1, 1) a7 a6 a5 a4 0 0 1 1 when a0 = 1, data from the register with address a7 to a4 is read out on SDATA Notes 1. Not used bits in the registers (indicated by X) are don’t care. Default data, initialized at power-up, is zero in all registers. For VCC < 2.5 V, the register contents are not guaranteed. 2. Vth programming uses both test mode register and compensation capacitor register. d0 in the formula above is the LSB of the test mode register and b2 is the data bit d2 of the compensation register. 1997 Jul 02 15 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.11 TDA5153 Test mode: HUS is HIGH except when the TAS detector is ON. If a thermal asperity is detected, HUS goes LOW. Head unsafe The HUS pin is an open-collector output. Consequently, when the pin is not connected to an external pull-up resistor, HUS is LOW. HUS pins can be connected together in case of operation with more than one amplifier. It is used to detect abnormal/unexpected operation. Servo write mode: HUS is LOW Write mode: • if in the configuration register d3 = 1, HUS is LOW • if in the configuration register d3 = 0, HUS goes HIGH for: the write current may be inhibited if d1 = 0 in the configuration register. Sleep mode: HUS is HIGH, to permit working with more than one amplifier. Standby mode: HUS is HIGH, to permit working with more than one amplifier. – Rext pin open, short-circuited to ground or to VCC (write current too low or too high) Read mode: – Write data input frequency too low (WDIx − WDIy) • if in the configuration register d3 = 1, HUS is HIGH – Write head Wx − Wy open, Wx or Wy short-circuited to ground (switching to write mode makes HUS LOW; after the transient the HUS detection circuitry is activated; the target for the head-open detect time is 15 ns) • if in the configuration register d3 = 0, HUS goes LOW for: – Rext pin open, short-circuited to ground or to VCC (read current too low or too high) – Write-head still left biased while not selected – Low VCC and VCC(WD) conditions. A low supply voltage detector is placed close to the VCC and VCC(WD) pins. – Low VCC and VCC(WD) conditions (write current inhibit can be active or inactive). The same detector is used for read and write mode. HUS goes LOW again between 0.5 and 1 µs after the last unsafe condition was detected. Detection of low VCC (main general supply): a VCC supply voltage below 4.0 V ±5% is flagged to the HUS pin. The voltage detection range is then 4.2 to 3.8 V with an hysteresis of 110 mV ±10%. Detection of low VCC(WD) (writer dedicated supply): a fault will be flagged at HUS pin if VCC(WD) drops 0.8 V ±10% below VCC. One must be aware that such a detection is only aimed to warn for a catastrophic situation. Indeed, VCC(WD) should never be below VCC. 8.12 HUS survey HUS DATA BIT D3 MODE STATE 0 1 Sleep mode − − HIGH HIGH Standby mode − − HIGH HIGH Read mode ACTIVE HIGH A-test mode(1) HIGH HIGH TAS mode ACTIVE ACTIVE Read Active mode Write Write mode ACTIVE LOW A-test mode(1) HIGH HIGH Servo mode(2) LOW LOW Notes 1. HUS survey: A-test mode = analog test mode. 2. In servo mode, the performance of the IC is not guaranteed. 1997 Jul 02 16 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5153 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage −0.5 +6.0 V VCC(WD) write driver supply voltage −0.5 +9.5 V VIL LOW level digital input voltage −0.5 +5.5 V VIH HIGH level digital input voltage −0.5 +5.5 V Vn1 voltage on all pins except VCC, read inputs nRx, nRy and write outputs nWx, nWy (n = 0 to 9) −0.5 +5.5 V − VCC + 0.5 V V but not higher than Vn2 voltage on write driver outputs nWx, nWy but not higher than −0.5 +8.8 − VCC(WD) + 0.8 V Vn3 voltage on read inputs nRx, nRy −0.5 1 InGND current through pins nGND − 0.1 A Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C V 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS device. 11 THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER CONDITION VALUE UNIT 70 K/W thermal resistance from junction to ambient TDA5153AG, TDA5153BG in free air TDA5153X see note 1 Note 1. The TDA5153X is shipped in naked dies. The thermal resistance depends on the flex used. 1997 Jul 02 17 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5153 12 RECOMMENDED OPERATION CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT VCC supply voltage range note 1 4.5 − 5.5 V VCC(WD) write driver supply voltage note 2 VCC − 8.8 V VIH HIGH level input voltage (CMOS) 3.5 − VCC V VIL LOW level input voltage (CMOS) 0 − 0.8 V Vi(dif)(p-p) differential input voltage (peak-to-peak value) note 3 0.4 0.7 1.5 V VIH(PECL) HIGH level PECL input voltage note 3 1.5 2.85 VCC V note 3 − 2.15 − V 0 − 70 °C reading − − 110 °C writing (VCC(WD) = 8 V) − − 130 °C 15 28 34 Ω VIL(PECL) LOW level PECL input voltage Tamb ambient temperature Tj junction temperature RMR MR element resistance ∆RMR RMR mismatch note 4 − − 4 Ω Ll(tot) total lead inductance to the head in each lead; note 5 − 35 − nH Rl(tot) total lead resistance to the head in each lead; note 5 − 1.5 − Ω VMR voltage on top of MR elements note 6 − − 0.5 V 0.4 1 2 mV Vsig(dif)(p-p) differential MR head input signal (peak-to-peak value) Lwh write head inductance including lead; note 5 − 0.15 − µH Rwh write head resistance including lead; note 5 − 10 − Ω Cwh write head capacitance including lead; note 5 − 5 − pF Rext external reference resistor V ref I ref = ---------R ext − 10 − kΩ Notes 1. A supply by-pass capacitor from VCC to ground or a low-pass filter may be used to optimize the PSRR. 2. The supply voltage VCC(WD) must never be below VCC in normal mode, and two diode voltages above VCC in servo mode. 3. The given values should be interpreted in such a way that the single-ended voltage could swing 0.2 to 0.75 V and that the common mode voltage should be such that for any of the two states, VIH(max) < VCC and VIL(min) > 1.5 V. PECL voltage swing: a wider peak-to-peak voltage swing can be used. In that case a current will flow through the ( WDIx – WDIy ) – 1.4 WDI inputs. This current is approximately equal to ----------------------------------------------------------200 4. The mismatch refers to the resistance of the two stripes of the same head. This is defined as follows: ∆RMR = RMR1 − RMR2 5. These parameters depend on the head model. The values given are those used for testing. 6. The combination of maximum head resistance, lead resistance and bias current is not permitted. To avoid voltage break-through between heads and disk, the voltage over the MR elements is limited by two diodes. 1997 Jul 02 18 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5153 13 CHARACTERISTICS VCC = 5.0 V; VCC(WD) = 8 V; VGND = 0 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Read characteristics IMR MR current adjust range ∆IMR tolerance (excluding Rext) Rext = 10 kΩ; 0.5 mA steps 5 − 20.5 mA − ±4 − % − 160 − I MR – I MR(PR) ---------------------------------I MR(PR) with IMR(PR) = 10 mA Gv(dif) differential voltage gain; note 1 from head inputs to RDx, RDy; RMR = 28 Ω; IMR = 10 mA; f = 20 MHz; d4 = 0 − 226 − − 13 − Ω differential input capacitance − 16 − pF d4 = 1 Ri(dif) differential input resistance Ci(dif) IMR = 10 mA THD total harmonic distortion − 1 − % BL signal gain pass band edge; note 2 −3 dB − − 100 kHz BH signal gain pass band edge without −3 dB (4 nH lead inductance) gain boost; note 2 −3 dB (50 nH lead inductance) − 220 − MHz − 170 − MHz F noise figure; note 3 RMR = 28 Ω; IMR = 10mA; Tamb = 25 °C; f = 20 MHz − 3.0 3.2 dB Vnir input referred noise voltage; note 3 RMR = 28 Ω; IMR = 10mA; Tamb = 25 °C; f = 20 MHz − 0.9 1.0 nV/√Hz fB(L) +3 dB noise low corner frequency RMR = 28 Ω; IMR = 10 mA; Tamb = 25 °C; no lead inductance − 400 kHz fB(H) +3 dB noise upper corner frequency RMR = 28 Ω; IMR = 10 mA; Tamb = 25 °C; no lead inductance − 220 MHz αcs channel separation; note 4 unselected head − 50 dB PSRR power supply rejection ratio; note 5 f < 1 MHz; IMR = 10 mA − 80 dB − 50 dB f < 1 MHz − 45 dB f < 100 MHz − 25 dB from SCLK, SDATA inputs to − the RDx − RDy outputs; note 7 50 dB f < 100 MHz; IMR = 10 mA CMRR common mode rejection ratio; note 5 from nRx − nRy to RDx − RDy; RMR mismatch < 5%; IMR = 10 mA; DR rejection of SCLK and SDATA; note 6 VO(R)(dif) output DC offset voltage in read DC voltage between mode (differential after DC settling) RDx − RDy (in read mode) − − ±0.2 V Zo(R) output impedance in read mode − 16 − Ω 1997 Jul 02 single ended 19 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads SYMBOL PARAMETER CONDITIONS TDA5153 MIN. TYP. MAX. UNIT − 4 − mA 1.0 1.5 2.0 V common mode DC supply rejection in read mode − 20 − dB differential output impedance in other modes (write, standby, sleep) − 50 − kΩ Io(max)(dif) maximum differential output current Vo(cm) common mode output voltage in read mode ∆V ocm ---------------∆V CC Zo(n)(dif) RDx, RDy Write characteristics IWR write current adjust range (in the write drivers) Rext = 10 kΩ; 1 mA steps 20 35 51 mA ∆IWR tolerance (excluding Rext); IWR(PR) = 35 mA − ±7 − % VCC(WD) = 5 V − − 8 V I WR – I RW (PR) -----------------------------------I RW (PR) Vs(max)(p-p) maximum voltage swing (peak-to-peak value) Ro(dif) differential output resistance tr, tf write current rise/fall time without flip-flop (10% to 90%); note 8 tas − − 13 V − 200 − Ω VCC(WD) = 8 V; Lh = 150 nH, Rh = 10 Ω; IWR = 35 mA; f = 20 MHz − − 1.8 ns write current asymmetry; note 9 percentage of tr/tf (tr, tf and logic asymmetry) − − 5 % tpd propagation delay 50% of (WDIx/WDIy) to 50% of (Wx, Wy) write head short circuited; data flip-flop by passed − − 5 ns αcs channel separation unselected head − 45 − dB − − 25 MHz − 200 − mV read amplifier OFF: d5 = 0 − 3 4.5 µs VCC(WD) = 8 V (differential) Switching characteristics fSCLK serial interface clock rate ∆Vo(cm) output common mode DC voltage change from Read to Write modes IMR = 10 mA; IWR = 35 mA trec(W-R) write to read recovery time (AC and DC settling); note 10 from 50% of the rising edge of R/W to steady state read-back signal: AC and DC settling at 90% (without load at RDx − RDy) read amplifier ON: d5 = 1 − 100 150 µs tsw(R) head switching (in read mode), standby to read active and MR current change recovery time; (AC and DC settling); note 11 from falling edge of SEN to steady state read-back signal; (without load at RDx − RDy) − 3 4.5 µs toff(R) read amplifier off time from falling edge of R/W to read head inactive − − 50 ns 1997 Jul 02 20 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads SYMBOL PARAMETER TDA5153 CONDITIONS MIN. TYP. MAX. UNIT tst(W) write settle times; note 12 from 50%of the falling edge of − R/W to 90% of the steady state write current (in Write Mode) − 70 ns toff(W) write amplifier off time from rising edge of R/W to IWR-programmed /10 (IWR = 35 mA) − − 50 ns tsw(W) head switching (in write mode), and standby to write head active from falling edge of SEN to write head active − 50 70 ns tsw(S) sleep to (and from) any other modes − − 100 µs − 72 80 mA from VCC (5 V) − 33 41 mA from VCC(WD) (5 to 8 V) − 54 61 mA − 0.25 1 mA − 0.025 − mA − 1.32 − V DC characteristics ICC(R) supply current; note 13 read mode; IMR = 10 mA ICC(W) supply current; note 14 write mode; IWR = 35 mA IDD(stb) standby mode supply current IDD(S) sleep mode supply current Vref reference voltage for Rext static Notes to the characteristics Boltzmann constant and T is the temperature in K. The noise figure is defined as follows: V no 2 ------- - Gv F = 10 × log ------------------------------------------------------------ dB 4kT × ( R + R ) MR1 MR2 1. The differential voltage gain depends on the MR resistance. It can be improved by programming the d4 bit in the configuration register using the serial interface. 2. The gain boost implements a pole-zero combination: The +3 dB gain boost corner frequency is 800 MHz ------------------------------------------------------------------------------------( 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 ) The −3 dB gain attenuation corner frequency is 800 MHz ------------------------------------------------------------------------------------( 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 ) where d3, d2, d1, d0 are bits (0, 1) to be programmed via the Serial Interface. In practical use, the bandwidth is limited by the inductance of the connection between the MR heads and the pre-amplifier. in 1 Hz bandwidth. Note that RMR includes all resistances between Rx or Ry to ground. b) Noise figure versus IMR and RMR: Table 1 shows the variation of the noise figure with IMR (mA) and RMR (Ω). c) Input noise voltage consideration: the input referred noise voltage calculation can significantly be different (from 1.0 to 0.44 nV/√Hz for instance) by taking into account an equivalent signal-to-noise ratio when using two MR stripes (28 Ω for each stripe) or one MR stripes (42 W). It assumes that the signal coming from the head is larger for a dual stripe head than for a single stripe head (50% extra signal for dual stripe head). 3. Noise calculation a) Definitions: The amplifier has a low-ohmic input. No lead resistance is taken into account. The input referred noise voltage, excluding the noise of the MR resistors, is defined as follows: V no 2 2 V nir = --------- – 4kT × ( R MR1 + R MR2 ) V Gv 4. The channel separation is defined by the ratio of the gain response of the amplifier using the selected head H(n) to the gain response of the amplifier using the adjacent head H(n ±1), Head H(n) being selected. where Gv is the voltage gain and Vno is the noise voltage at the output of the amplifier, k is the 1997 Jul 02 21 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 5. 8. The rise and fall times depend on the write amplifier-write head combination. Lh and Rh represent the components on the evaluation board. Parasitic capacitances also limit the performance. The PSRR (in dB) is defined as input referred ratio: Gv PSRR = 20 × log ------- Gp Where Gv is the differential input to differential output gain, and Gp is the power supply to differential output gain. The CMRR (in dB) is defined as input referred Gv ratio: CMRR = 20 × log ----------- G cm 9. The write current rise/fall time asymmetry is defined by tr – tf ----------------------2 ( tr + tf) 10. Write-to-read recovery time includes the write mode to read mode switching using the R/W pin on the same head (see Fig.6). The AC signal reaches its full amplitude few tenth of ns after appearing at the reader RDx and RDy outputs. where Gv is the differential input to differential output gain and Gcm is the common mode input to differential output gain. Flex and board lay-out may affect significantly these parameters. 11. In read mode, the head switching, standby to read active switching and changing MR current include fast current settling (see Fig.7). Same note regarding the AC signals at the reader outputs as above. 6. This refers to the crosstalk from SCLK and SDATA inputs via the read inputs to RDx − RDy. Two cases can be distinguished: a) With SEN LOW, SCLK and SDATA are prohibited from entering the device and crosstalk is low. 12. Write settle time includes read mode to write mode switching using the R/W pin. b) Programming via the serial interface is done with SEN HIGH. Then crosstalk can occur. A careful design of the board or flex-foil is required in order not to get crosstalk via this path. 13. The typical supply current in read mode depends on the bias current for the MR element. 14. The typical supply current in write mode also depends on the write current. 7. A 200 mV peak-to-peak signal is applied to SCLK or SDATA inputs at 25 MHz, and measurement is performed at RDx − RDy. Table 1 TDA5153 Noise figure F (dB) RMR (Ω) 1997 Jul 02 IMR = 7 mA IMR = 10 mA IMR = 15 mA 20 2.7 2.9 3.1 25 2.8 3.0 3.3 30 2.9 3.1 3.5 22 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5153 handbook, full pagewidth R/W RDx-RDy trec(W-R) toff(R) MGG985 Fig.6 Timing diagram of the reader: write-to-read switching on the same logic head. handbook, full pagewidth SEN RDx-RDy tsw(R) MGG986 Fig.7 Timing diagram of the reader: typical head, current and standby-to-read characteristics. 1997 Jul 02 23 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5153 14 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE Q e E HE A A2 (A 3) A1 w M pin 1 index θ bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.69 0.59 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 93-06-15 94-12-19 SOT313-2 1997 Jul 02 EUROPEAN PROJECTION 24 o Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads If wave soldering cannot be avoided, the following conditions must be observed: 15 SOLDERING 15.1 Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 15.2 During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. 15.4 Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1997 Jul 02 Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 15.3 TDA5153 25 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5153 16 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Jul 02 26 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads NOTES 1997 Jul 02 27 TDA5153 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA54 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 297027/25/01/pp28 Date of release: 1997 Jul 02 Document order number: 9397 750 01904