INTEGRATED CIRCUITS DATA SHEET TDA5155 Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads Preliminary specification File under Integrated Circuits, IC11 1997 Apr 08 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.6 8.7.7 8.7.8 8.7.9 8.7.10 8.8 8.9 Read mode Write mode Sleep mode Standby mode Active mode Bi-directional serial interface Addressing Programming data Reading data Operation of the serial interface Configuration Power control Head select Servo write Test Write amplifier programmable capacitors High frequency gain attenuator register High frequency gain boost register Settle pulse Address registers summary Head unsafe HUS survey 9 LIMITING VALUES 10 HANDLING 11 THERMAL RESISTANCE 12 RECOMMENDED OPERATION CONDITIONS 13 CHARACTERISTICS 14 DEFINITIONS 15 LIFE SUPPORT APPLICATIONS 1997 Apr 08 2 TDA5155 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 1 FEATURES 3 • Designed for 10 dual-stripe MR-read/inductive write heads • Single supply voltage (5.0 V ±10%); a separate write drivers supply pin can be biased from VCC to 8 V +10% • MR elements connected to ground (GND) • Equal bias currents in the two MR stripes of each head • On-chip AC couplings eliminate MR head DC offset • 3-wire serial interface for programming • Programmable voltage/current mode write data input The device incorporates read amplifiers, write amplifiers, a serial interface, digital-to-analog converters, reference and control circuits which all operate on a single supply voltage of 5 V ±10%. The output drivers have a separate supply voltage pin which can be connected to a higher supply voltage of up to 8 V +10%. The complementary output stages of the write amplifier allow writing with near rail-to-rail peak voltages across the inductive write head. • Programmable high frequency zero-pole gain boost • Programmable write driver compensation capacitance • Programmable MR bias currents and write currents • 1-bit programmable read gain • Sleep, standby, active and test modes available • Measurement of head resistances in test mode • In test mode, one MR bias current may be forced to a minimum current The read amplifier has low input impedance. The DC offset between the two stripes of the MR head is eliminated using on-chip AC coupling. Fast settling features are used to keep the transients short. As an option, the read amplifier may be left biased during writing so as to reduce the duration of these transients even further. Series inductance in the leads between the amplifier and MR heads influences the bandwidth which can be compensated by using a programmable high frequency gain boost (HF zero). HF noise and bandwidth can be attenuated using a programmable high frequency gain attenuator (HF pole). • Short write current rise and fall times with near rail-to-rail voltage swing • Head unsafe pin for signalling of abnormal conditions and behaviour • Low supply voltage write current inhibit (active or inactive) • Support servo writing • Provide temperature monitor • Thermal asperity detection with programmable threshold level On-chip digital-to-analog converters for MR bias currents and write currents are programmed via a 3-wire serial interface. Head selection, mode control, testing and servo writing can also be programmed using the serial interface. In sleep mode the CMOS serial interface is operational. Fig.1 shows the block diagram of the device. • Requires only one external resistor. APPLICATIONS • Hard Disk Drive (HDD). 4 GENERAL DESCRIPTION The 5.0 V pre-amplifier for HDD applications has been designed for five terminal, dual-stripe Magneto-Resistive (MR)-read/inductive write heads. The disks of the disk drive are connected to ground. To avoid voltage breakthrough between the heads and the disk, the MR elements of the heads are also connected to ground. The symmetry of the dual-stripe head-amplifier combination automatically distinguishes between the differential signals such as signals and the common-mode effects like interference. The latter are rejected by the amplifier. • Current bias-current sense architecture 2 TDA5155 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA5155X − 1997 Apr 08 DESCRIPTION VERSION − naked die 3 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 5 TDA5155 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage 4.5 5.0 5.5 V VCC(WD) supply voltage for write drivers VCC 8.0 8.8 V Gv(dif) differential voltage gain from head inputs to RDx, RDy; RMR = 28 Ω; IMR = 10 mA data bit d4 = 0 − 160 − data bit d4 = 1 − 226 − B−3dB −3 dB frequency bandwidth upper bandwidth without gain boost (4 nH lead inductance) − 220 − MHz F noise figure RMR = 28 Ω; IMR = 10 mA; Tamb = 25 °C; f = 20 MHz − 3.0 3.2 dB Virn input referred noise voltage RMR = 28 Ω; IMR = 10 mA; Tamb = 25 °C; f = 20 MHz − 0.9 1.0 nV/√Hz CMRR common mode rejection ratio RMR mismatch <5% IMR = 10 mA f < 1 MHz − 45 − dB f < 100 MHz − 25 − dB − 80 − dB − 50 − dB VCC(WD) = 8.0 V − − 1.8 ns VCC(WD) = 6.5 V − − 2.1 ns PSRR IMR = 10 mA power supply rejection ratio (input referred) RMR mismatch <5% f < 1 MHz f < 100 MHz tr, tf write current rise/fall time (10% to 90%) Lh = 150 nH; Rh = 10 Ω; IWR = 35 mA; f = 20 MHz IMR(PR) programming MR bias current range Rext = 10 kΩ 5 − 20.5 mA IWR(b-p) programming write current range (base-to-peak) Rext = 10 kΩ 20 − 51 mA fSCLK serial interface clock rate − − 25 MHz 1997 Apr 08 4 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 6 TDA5155 BLOCK DIAGRAM handbook, full pagewidth VCC VCC(WD) 16 1 (5 to 8 V) TDA5155 WDlx(i) WDly(i) WDlx(v) WDly(v) HUS 7 4 WRITE DRIVER INPUT FF 19, 24, 10 29, 34, 39, 44, 49, 54, 59, 64 5 3 nWy nWx HEAD UNSAFE INDICATOR LOW SUPPLY VOLTAGE INDICATOR Rext 20, 25, 30, 35, 40, 45, 50, 55, 60, 65 10 6 WRITE CURRENT SOURCE 10 17 WRITE DRIVER AND READ PREAMP (10×) VOLTAGE REFERENCE +VCC TAS DETECTOR 8 R/W SCLK SEN SDATA 11 SERIAL INTERFACE 4 9 10 20 kΩ head select 5 3 10 RMR CURRENT SOURCE 5 23, 28, 33, 38, 43, 48, 53, 58, 10 63, 68 4 4 22, 27, 32, 37, 42, 47, 52, 57, 10 62, 67 13 RDx RDy 14 21, 26, 31, 36, 41, 46, 51, 56, 10 61, 66 2, 12, 15, 18 MGG982 GNDn Fig.1 Block diagram. 1997 Apr 08 5 nRy nGND nRx Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 7 TDA5155 PINNING SYMBOL PAD VCC(WD) GND1 HUS WDIx(v) 1 2 3 4 WDIy(v) 5 WDIx(i) 6 WDIy(i) 7 R/W 8 SEN SDATA SCLK GND2 RDx RDy GND3 VCC Rext GND4 0Wx 9 10 11 12 13 14 15 16 17 18 19 0Wy 20 0Rx 21 0GND 0Ry 22 23 1Wx 24 1Wy 25 1Rx 26 1GND 1Ry 27 28 2Wx 29 1997 Apr 08 SYMBOL PAD DESCRIPTION supply voltage for the write drivers ground connection 1 head unsafe output write data input (differential, voltage input) write data input (differential, voltage input) write data input (differential, current input) write data input (differential, current input) read/write (read = active HIGH, write = active LOW) serial bus enable serial bus data serial bus clock ground connection 2 read data output (differential x − y) read data output (differential x − y) ground connection 3 supply voltage 10 kΩ external resistor ground connection 4 inductive write head connection for head H0 (differential x − y) inductive write head connection for head H0 (differential x − y) MR-read head connection for head H0 (differential x − y) ground connection for head H0 MR-read head connection for head H0 (differential x − y) inductive write head connection for head H1 (differential x − y) inductive write head connection for head H1 (differential x − y) MR-read head connection for head H1 (differential x − y) ground connection for head H1 MR-read head connection for head H1 (differential x − y) inductive write head connection for head H2 (differential x − y) 6 2Wy 30 2Rx 31 2GND 2Ry 32 33 3Wx 34 3Wy 35 3Rx 36 3GND 3Ry 37 38 4Wx 39 4Wy 40 4Rx 41 4GND 4Ry 42 43 5Wx 44 5Wy 45 5Rx 46 5GND 5Ry 47 48 6Wx 49 6Wy 50 6Rx 51 6GND 6Ry 52 53 7Wx 54 DESCRIPTION inductive write head connection for head H2 (differential x − y) MR-read head connection for head H2 (differential x − y) ground connection for head H2 MR-read head connection for head H2 (differential x − y) inductive write head connection for head H3 (differential x − y) inductive write head connection for head H3 (differential x − y) MR-read head connection for head H3 (differential x − y) ground connection for head H3 MR-read head connection for head H3 (differential x − y) inductive write head connection for head H4 (differential x − y) inductive write head connection for head H4 (differential x − y) MR-read head connection for head H4 (differential x − y) ground connection for head H4 MR-read head connection for head H4 (differential x − y) inductive write head connection for head H5 (differential x − y) inductive write head connection for head H5 (differential x − y) MR-read head connection for head H5 (differential x − y) ground connection for head H5 MR-read head connection for head H5 (differential x − y) inductive write head connection for head H6 (differential x − y) inductive write head connection for head H6 (differential x − y) MR-read head connection for head H6 (differential x − y) ground connection for head H6 MR-read head connection for head H6 (differential x − y) inductive write head connection for head H7 (differential x − y) Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads SYMBOL PAD 8GND 8Rx 8Wy 8Wx 7Ry 7GND 7Rx 7Wy 7Wx 67 68 8Ry handbook, full pagewidth 9GND 9Ry 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 6Ry 52 6GND 2 51 6Rx 3 50 6Wy 4 49 6Wx 5 48 5Ry 6 47 5GND 7 46 5Rx R/W 8 45 5Wy SEN 9 44 5Wx VCC(WD) 1 GND1 HUS WDIx(v) WDIy(v) WDIx(i) WDIy(i) TDA5155 SDATA 10 43 4Ry 4Wy 39 4Wx GND3 15 38 3Ry VCC 16 37 3GND Rext 17 36 3Rx GND4 18 35 3Wy 3Wx 0 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 2Ry 40 14 2GND 13 RDy 2Rx RDx 2Wy 4Rx 2Wx 4GND 41 1Ry 42 12 1GND 11 1Rx SCLK GND2 1Wy 61 66 1Wx 8Rx 9Rx 9Wx 60 65 0Ry 8Wy 9Wy 9Wy 59 64 0GND 8Wx 9Wx 9Rx 57 58 Fig.2 Pad arrangement. 1997 Apr 08 ground connection for head H8 MR-read head connection for head H8 (differential x − y) inductive write head connection for head H9 (differential x − y) inductive write head connection for head H9 (differential x − y) MR-read head connection for head H9 (differential x − y) ground connection for head H9 MR-read head connection for head H9 (differential x − y) 9GND 7GND 7Ry 62 63 0Rx 56 8GND 8Ry 0Wy 7Rx inductive write head connection for head H7 (differential x − y) MR-read head connection for head H7 (differential x − y) ground connection for head H7 MR-read head connection for head H7 (differential x − y) inductive write head connection for head H8 (differential x − y) inductive write head connection for head H8 (differential x − y) MR-read head connection for head H8 (differential x − y) DESCRIPTION 9Ry 55 SYMBOL PAD 0Wx 7Wy DESCRIPTION TDA5155 7 MGG981 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8 8.1 8.2 FUNCTIONAL DESCRIPTION Write mode To minimize power dissipation, the read circuitry may be disabled in write mode. The write circuitry is disabled in read, sleep and standby modes. In write mode, a programmable current is forced through the selected two-terminal inductive write head. The push-pull output drivers yield near rail-to-rail voltage swings for fast current polarity switching. Read mode The read mode disables the write circuitry to save power while reading. The read circuitry is disactivated for write, sleep and standby modes. The read circuitry may also be biased during write mode to shorten transients. The selected head is connected to a multiplexed low-noise read amplifier. The read amplifier has low-impedance inputs nRx and nRy (n is the number of the head) and low-impedance outputs RDx and RDy. The signal polarity is non-inverting from x and y inputs to x and y outputs. The write data input can be either voltage or current input (see Chapter 12). In voltage mode, the differential write data inputs WDIx(v) and WDIy(v) are PECL (Positive Emitter Coupled Logic) compatible. The write data flip-flop can either be used or passed-by. In the case that the write data flip-flop is used, current polarity is toggled at the falling edges of V WDIx ( v ) – V WDIy ( v ) V data = ----------------------------------------------------2 Switching to write mode initializes the data flip-flop so that the write current flows in the write head from x to y. In the case that the write data flip-flop is not used, the signal polarity is non-inverting from x and y inputs to x and y outputs. Ambient magnetic fields at the MR elements result in a relative change in MR resistance: dR MR -------------R MR This change produces a current variation: dR MR dI MR = I MR × -------------- , R MR where IMR is the bias current in the MR element. The current variation is amplified to form the read data output signal voltage, which is available at RDx and RDy. AC coupling between MR elements and amplifier stages prevents the amplifier input stages from overloading by DC voltages across the MR elements. A fast settling procedure shortens DC settling transients. The write current magnitude is controlled through on-chip DACs. The write current is defined as follows: 10kΩ I WR = --------------- ( 20 + 16d4 + 8d3 + 4d2 + 2d1 + d0 ) R ext (in mA), where d4-d0 are bits (either logic 0 or logic 1). The adjustable range of the write current is 20 mA to 51 mA. At power-up, the default values d4 = d3 = d2 = d1 = d0 = logic 0 are initialized, corresponding to IWR = 20 mA. IWR is the current provided by the write drivers: the current in the write coil and in the damping resistor together. The static current in the write coil is I WR ----------------- , R 1 + ------hRd An on-chip generated stable temperature reference voltage (1.32 V), available at the Rext pin, is dropped across an external resistor (10 kΩ) to form a global reference current for the write and the MR bias currents. The MR bias current DACs are programmed through the serial interface according to the following formula: 10kΩ I MR = 0.5 × --------------- ( 10 + 16d4 + 8d3 + 4d2 + 2d1 + d0 ) R ext (in mA), where d4-d0 are bits (either logic 0 or logic 1). At power-up all bits are set to logic 0, which results in a default MR current of 5 mA. The adjustable range of the MR currents is 5 mA to 20.5 mA. The MR bias currents are equal for the two stripes of each head. The gain amplifier is 1-bit programmable. The amplifier gain can be set to its nominal value or to the nominal value +3 dB. 1997 Apr 08 TDA5155 where Rh is the resistance of the coil including leads and Rd is the damping resistor. 8 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.3 Three phases in the communication are distinguishable: addressing, programming and reading. Each communication sequence starts with an addressing phase, followed by either a programming phase or a reading phase. Sleep mode In sleep mode, the device is accessible via the serial interface. All circuits are inactive, except the circuits of the CMOS serial interface and the circuitry which forces the data registers to their default values at power-up and which fixes the DC level of outputs RDx and RDy (required when operating with more than one amplifier). Typical static current consumption is −30 µA. Dynamic current consumption during operation of the serial interface in sleep mode due to external activity at the inputs to the serial interface is not included. In all modes, including the sleep mode, data registers can be programmed. Sleep is the default mode at power-up. Switching to other modes takes less than 0.1 ms. 8.4 8.6.1 Standby mode 8.6.2 Active mode 8.6.3 Bi-directional serial interface READING DATA Immediately after the IC detects that a7 = logic 1, data from the data register (address a5 to a0) is copied in parallel to the input register. Two wait clock cycles must follow before the controller can start inputting data. At the first falling edge of SCLK after the 2 wait rising edges of SCLK, the LSB d0 is placed on SDATA line followed by d1 at the next falling edge of SCLK etc. If SEN goes LOW before 8 address bits (a7 to a0) have been detected, the communication is ignored. If SEN goes LOW before the 8 data bits have been sent out of the IC, the reading sequence is immediately interrupted. See Fig.4 for the timing diagram of the reading via the serial interface. The serial interface is used for programming the device and for reading of status information. 16 bits (8 bits for data and 8 for address) are used to program the device. The serial interface requires 3 pins: SDATA, SCLK and SEN. These pins (and R/W as well) are CMOS inputs. The logic input R/W has an internal 20 kΩ pull-up resistor and the SEN logic input has an internal 20 kΩ pull-down resistor. Thus, in case the SEN line is opened, no data will be registered and in case the R/W line is opened, the device will never be in write mode. SDATA: serial data; bi-directional data interface. In all circumstances, the LSB is transmitted first. SCLK: serial clock; 25 MHz clock frequency. SEN: serial enable; data transfer takes place when SEN is HIGH. When SEN is LOW, data and clock signals are prohibited from entering the circuit. 1997 Apr 08 PROGRAMMING DATA If a7 = 0, the last eight bits d7 to d0 before SEN goes LOW are shifted into an input register. When SEN goes LOW, the communication sequence is ended and the data in the input register is copied in parallel to the data register that corresponds to the decoded address a0 to a5. SEN should go LOW at least 5 ns after the last rising edge of SCLK. See Fig.3 for the timing diagram of the programming. Active mode is either read mode or write mode depending on the status of the R/W pin. 8.6 ADDRESSING When SEN goes HIGH, bits are latched in at rising edges of SCLK. The first eight bits a7 to a0 (starting with a0) are shifted serially into an address register. If SEN goes LOW before 16 bits have been received, the operation is ignored. When more than 16 bits (address and data) are latched in before SEN goes LOW, the first 8 bits are interpreted as an address and the last 8 bits as data. SEN should go HIGH at least 5 ns before the first rising edge of SCLK. Data should be valid at least 5 ns before and after a rising edge of SCLK. The first six bits a5 to a0 constitute the register address. Bit a6 is unused. If bit a7 = logic 0, a PROGRAMMING sequence starts. If bit a7 = logic 1, READING data from the pre-amplifier can start. The circuit can be put in standby mode using the serial interface. In standby mode, the typical DC current consumption is 330 µA. Transients from standby mode to active mode are two orders of magnitude shorter than from sleep mode to active mode. This is important in the case of cylinder mode operation with multiple amplifiers. All amplifiers can operate from standby mode and all head switch times can be kept just as short as in the case of operation with a single amplifier. Head switch times are summarized in the switching characteristics. 8.5 TDA5155 9 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5155 handbook, full pagewidth SEN SCLK SDATA a0 a1 a2 a3 a4 a5 a6 0 d0 d1 d2 d3 address d4 d5 d6 d7 data MGG983 Fig.3 Timing diagram of the write sequence of the serial interface operation (a7 = logic 0). handbook, full pagewidth SEN SCLK SDATA a0 a1 a2 a3 a4 address a5 a6 1 wait cycles d0 d1 d2 d3 d4 d5 d6 d7 data MGG984 Fig.4 Timing diagram of the read sequence of the serial interface operation a7 = logic 1). 1997 Apr 08 10 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.7 Operation of the serial interface 8.7.2 The serial interface programming is summarized in Section 8.7.10. 8.7.1 POWER CONTROL By default, d1 = d0 = logic 0, the pre-amplifier powers up in sleep mode. If d1 = logic 0, d0 = logic 1 or d1 = logic 1, d0 = logic 0 the circuit goes in standby mode. If d1 = d0 = logic 1, the circuit goes in active mode (read or write mode depending on the R/W input). CONFIGURATION d0: By default (d0 = logic 0), write data passes from the write data input via the data flip-flop to the write driver. The write driver toggles the current in the head at the falling edges of: V WDIx ( v ) – V WDIy ( v ) V data = ----------------------------------------------------- or 2 8.7.3 HEAD SELECT Selection of a wrong head (H10-H15) causes an head unsafe condition. HUS goes HIGH when in write mode a wrong head is selected and when d3 in the configuration register is LOW. When in read mode and a wrong head is selected, head H0 is therefore selected and if d3 in the configuration register is LOW, HUS goes LOW. I WDIx ( i ) – I WDIy ( i ) I data = ---------------------------------------------2 When d0 = logic 1, the write data flip-flop is not used. The signal polarity is non-inverting from the inputs WDIx and WDIy to the outputs nWx and nWy. 8.7.4 SERVO WRITE The circuit is prepared for servo writing. However, the device will not be guaranteed. d1: 8.7.5 By default (d1 = logic 0), the pre-amplifier senses PECL write signals at WDIx(v) and WDIy(v). When d1 = logic 1, the pre-amplifier senses input write currents at WDIx(i) and WDIy(i). TEST d2 = d1 = d0 = logic 0. The circuit is not in test mode. This is the default situation. 8.7.5.1 d2: MR head test d2 = logic 0, d1 = logic 0, d0 = logic 1. In read mode, the voltages at Rx and Ry (at the top of the MR elements) of the selected head are fed to outputs RDx and RDy. By measuring the output voltages single ended at two different IMR currents, the MR resistance can be accurately measured according to the following formula: V RDx1 – V RDx2 R MRx = -------------------------------------- for the x-side. I MRx1 – I MRx2 By default (d2 = logic 0), the write current is inhibited under low supply voltage conditions. The write current inhibit is made inactive by programming d2 to logic 1. d3: By default (d3 = logic 0), in write mode low supply voltage, open head, and other conditions are monitored and flagged at HUS. If d3 = logic 1, HUS is LOW in write mode and HIGH in read mode. Open head and head short-circuited-to-ground conditions can therefore be detected. d4: The amplifier read gain may be programmed in the configuration register. By default (d4 = logic 0), the read gain is typically 160 with RMR = 28 Ω. If d4 = logic 1, the read amplifier gain is 3 dB higher (226 in this case). d2 = logic 0, d1 = logic 1, d0 = logic 0. Same as before, with the difference that IMR2 is fixed to a minimum constant value of 5 mA. Measuring in the same way as above with IMR1 > 5 mA, enables the detection of MR elements shorted together. d5: In order to minimize the write-to-read recovery times, the first stage of the read amplifier may be kept biased during write mode. By default, (d5 = logic 0) the read amplifier is powered down during write mode, and the fast settling procedure is activated after write-to-read switching. If d5 = logic 1 the read amplifier is kept biased during write mode, and the fast settling procedure still occurs if the head is changed or the MR current is re-programmed. 1997 Apr 08 TDA5155 8.7.5.2 Temperature monitor d2 = logic 0, d1 = logic 1, d0 = logic 1. The temperature monitor voltages are connected to RDx and RDy. The output differential voltage depends on the temperature according to: dV = −0.00364 × T + 1.7; 0 < T < 140 °C. The temperature may be measured with a typical precision of 5 °C. 11 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.7.5.3 frequency noise. The HF pole can be used in combination with the HF zero in order to boost the HF gain locally and yet limit the very high frequency noise enhancement. Thermal asperity detector d2 = logic 1, d1 = x, d0 = (0,1). Unlike the above tests, the thermal asperity detection does not use the RDx and RDy outputs. Thus, the reader is fully operational. In case a thermal asperity is detected, it is flagged at the HUS pin. 8.7.8 V th = ( 210 + 560.d0 + 280.d2 ) µV d0 of test mode register; d2 of the compensation capacitor register. 8.7.9 SETTLE PULSE By default (d2 = d1 = d0 = logic 0) the settle pulse has a nominal duration of 3 µs. Its value can be programmed from 2.125 µs to 3 µs according to the following formula: 1 t st = 2µs + ------------------------------------------------------------------- µs ( 4.d2 + 2.d1 + 1.d0 + 1 ) The settle pulse is used to shorten the transients during switching. WRITE AMPLIFIER PROGRAMMABLE CAPACITORS By default (d2 = d1 = d0 = logic 0) the programmable capacitors are zero. These capacitors are used to improve the performance of the write amplifier according to the write amplifier output load. 8.7.7 HIGH FREQUENCY GAIN BOOST REGISTER By default (d3 = d2 = d1 = d0 = logic 0) the high frequency gain boost is not active. The gain boost provides a zero which allows to optimize the bandwidth of the read amplifier and to correct for attenuation caused by series inductances in the leads between the MR heads and the read amplifier inputs. The threshold voltage for the thermal asperity detection is 2-bit programmable. These 2 bits consist of d0 (LSB) of the test mode register (address = 0xxx0110), and d2 of the compensation capacitor register (address = 0xxx0111). 8.7.6 TDA5155 HIGH FREQUENCY GAIN ATTENUATOR REGISTER By default (d3 = d2 = d1 = d0 = logic 0) the high frequency gain attenuator is not active. The gain attenuator provides a pole which limits the bandwidth and reduces the high 8.7.10 ADDRESS REGISTERS SUMMARY ADDRESS REGISTERS(1) FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 0 X X X 0 0 0 0 configuration register: d0 = 0: use data flip-flop; d0 = 1: by-pass data flip-flop d1 = 0: WDI PECL; d1 = 1: current input d2 = 0: write current inhibit active; d2 = 1: write current inhibit inactive read mode: d3 = 0: HUS active; d3 = 1: HUS HIGH write mode: d3 = 0: HUS active; d3 = 1: HUS LOW d4 = 0: read gain nominal; d3 = 1: read gain +3 dB d5 = 0: read amplifier OFF during write mode; d5 = 1: read amplifier ON during write mode 0 X X X 0 0 0 1 power control register: (d1,d0) = (0,0): sleep mode (d1,d0) = (1,0) or (0,1): standby mode (d1,d0) = (1,1): active mode (write or read) 0 X X X 0 0 1 0 head select register: (d3,d2,d1,d0) = (0,0,0,0) to (1,0,0,1): H0 to H9 addressing H10 to H15 causes HUS to go HIGH if in write mode and H0 to be selected if in read mode 1997 Apr 08 12 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5155 ADDRESS REGISTERS(1) FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 0 X X X 0 0 1 1 MR current DAC register: 10kΩ I MR = 0.5 × --------------- ( 10 + 16.d4 + 8.d3 + 4.d2 + 2.d1 + d0 ) mA R ext 0 X X X 0 1 0 0 write current DAC register: 10kΩ I WR = --------------- ( 20 + 16.d4 + 8.d3 + 4.d2 + 2.d1 + d0 ) mA R ext 0 X X X 0 1 0 1 servo write register: (d0,d1) = (0,0): one head (d0,d1) = (1,1): all heads (d0,d1) = (1,0): odd numbered heads (H1, H3, H5, H7 and H9) (d0,d1) = (0,1): even numbered heads (H0, H2, H4, H6 and H8) 0 X X X 0 1 1 0 test mode register: (d2,d1,d0) = (0,0,0) = not in test mode (d2,d1,d0) = (0,0,1) = read head test (IMR1 = IMR2) (d2,d1,d0) = (0,1,0) = read head test (IMR2 = 5 mA fixed) (d2,d1,d0) = (0,1,1) = temperature monitor (d2,d1,d0) = (1,X,d0) = thermal asperity detection, see note 2 Vth = (210 + 560.d0 + 280.d2) µV 0 X X X 0 1 1 1 compensation capacitor register: equivalent differential capacitance = (4.d2 + 2.d1 + 1.d0) × 2 pF 0 X X X 1 0 0 0 high frequency gain attenuator register 800 MHz nominal pole frequency = --------------------------------------------------------------------8.d3 + 4.d2 + 2.d1 + 1.d0 0 X X X 1 0 0 1 high frequency gain boost register 800 MHz nominal zero frequency = --------------------------------------------------------------------8.d3 + 4.d2 + 2.d1 + 1.d0 0 X X X 1 0 1 0 settle time register 1 settle time: t st = 2µs + ------------------------------------------------------------------- µs ( 4.d2 + 2.d1 + 1.d0 + 1 ) 1 X X X 1 1 1 1 device ID register ID = 8.d3 + 4.d2 + 2.d1 + 1.d0; d3 to d0 are preset to (0,0,1,1) 1 X X X a3 a2 a1 a0 when a7 = 1, data from the register with address a3 to a0 is read out on SDATA Notes 1. Unused bits in the registers (indicated by X) are don’t care. Default data, initialized at Power-up, is zero in all registers. For VCC <2.5 V, the register contents are not guaranteed. 2. Vth programming uses both the test mode register and the compensation capacitor register. d0 in the formula above is the LSB of the test mode register and d2 is the d2 data bit of the compensation capacitor register. 1997 Apr 08 13 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.8 TDA5155 Test mode: HUS is HIGH except when the TAS detector is ON. If a thermal asperity is detected, HUS goes LOW. Head unsafe The HUS pin is an open collector output. Therefore when the pin is not connected to an external pull-up resistor, HUS is LOW. HUS pins can be connected together in case of operation with more than one amplifier. It is used to detect abnormal or unexpected operation. Servo write mode: HUS is LOW. Write mode: • If in the configuration register d3 = 1, HUS is LOW • If in the configuration register d3 = 0, HUS goes HIGH for: Sleep mode: HUS is HIGH, to permit working with more than one amplifier. – Selection of a wrong head (H10 to H15)(1) Standby mode: HUS is HIGH, to permit working with more than one amplifier. – Rext pin open, short-circuited to ground or to VCC (write current too low or too high) Read mode: – Write Data Input frequency too low (WDIx-WDIy) • If in the configuration register d3 = 1, HUS is HIGH – Write head Wx, Wy open, Wx or Wy short-circuited to ground(2) • If in the configuration register d3 = 0, HUS goes LOW for: – Selection of a wrong head (H10 to – Write driver still left biased while not selected H15)(1) – Low VCC and VCC(WD) conditions (write current inhibit can be active or inactive). – Rext pin open, short-circuited to ground or to VCC (read current too low or too high) The same detector is used for read and write mode. The write current may be inhibited if d2 = 0 in the configuration register. – Low VCC and VCC(WD) conditions. A low supply voltage detector is placed close to the VCC and VCC(WD) pins. The HUS line indicates an unsafe condition as long as the fault is present, in read mode as well as in write mode. It indicates again a safe condition only 0.5 µs to 1 µs after the last fault has disappeared. Detection of low VCC (main supply): a VCC supply voltage below 4.0 V ±5% is flagged at the HUS pin. The voltage detection range is then 4.2 to 3.8 V with an hysteresis of 110 mV ±10%. Detection of low VCC(WD) (write drivers supply): a fault will be flagged at the HUS pin if VCC(WD) drops 0.8 V ±10% below VCC. One must be aware that such a detection is only aimed to warn for a catastrophic situation. Indeed, VCC(WD) should never be below VCC. 8.9 (1) Head numbers 0 to 9 are correct, 10 to 15 are signalled as unsafe. (2) Switching to write mode makes HUS LOW. After the transient the HUS detection circuitry is activated. The target for the head open detection time is 15 ns. HUS survey HUS DATA BIT D3 MODE STATE 0 1 Sleep mode − − HIGH HIGH Standby mode − − HIGH HIGH Active mode Read Write Read mode ACTIVE HIGH A-test mode(1) HIGH HIGH TAS mode ACTIVE ACTIVE Write mode ACTIVE LOW A-test mode(1) HIGH HIGH Servo mode(2) LOW LOW Notes 1. A-test mode = analog test mode. 2. In servo mode, the performance of the IC is not guaranteed. 1997 Apr 08 14 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 9 TDA5155 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage −0.5 +6.0 V VCC(WD) write driver supply voltage −0.5 +9.5 V Vn1 voltage on all pins except VCC(WD), read inputs nRx, nRy −0.5 and write driver outputs nWx, nWy (n = 0 to 9) +5.5 V VCC + 0.5 V V − absolute maximum value Vn2 voltage on write driver outputs nWx, nWy absolute maximum value −0.5 +8.8 − VCC(WD) + 0.5 V Vn3 voltage on read inputs nRx, nRy −0.5 +1 V InGND ground current (pins nGND) − 0.1 A Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 11 THERMAL CHARACTERISTICS The thermal resistance depends on the flex used. The TDA5155X is shipped in naked dies form. 1997 Apr 08 15 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5155 12 RECOMMENDED OPERATION CONDITIONS SYMBOL PARAMETER CONDITIONS VCC supply voltage note 1 note 2 MIN. TYP MAX. 4.5 − 5.5 UNIT V VCC(WD) write driver supply voltage VCC − 8.8 V VIH HIGH level input voltage (CMOS) 3.5 − VCC V VIL LOW level input voltage (CMOS) 0 − 0.8 V Vi(dif)(p-p) differential input voltage (peak-to-peak value) note 3 0.4 0.7 1.5 V VIH(PECL) HIGH level PECL input voltage note 3 − 2.85 VCC V VIL(PECL) LOW level PECL input voltage note 3 1.5 2.15 − V Ii(dif)(p-p) differential input current (peak-to-peak value) note 4 0.4 0.8 1.0 mA IIH(dif) HIGH level differential input current note 4 −1.4 −1.2 − mA IIL(dif) LOW level differential input current note 4 − −0.4 −0.1 mA Tamb ambient temperature 0 − 70 °C Tj junction temperature reading − − 110 °C writing (VCC(WD) = 8 V) − − 130 °C 15 28 34 Ω RMR MR element resistance ∆(RMR) RMR mismatch note 5 − − 4 Ω Ll(tot) total lead inductance to the head in each lead; note 6 − 25 − nH Rl(tot) total lead resistance to the head in each lead; note 6 − 1.5 − Ω VMR voltage on top of MR elements note 7 − − 0.5 V Vsig(dif)(p-p) differential MR head input voltage (peak-to-peak value) 0.4 1 2 mV Lwh write head inductance including lead; note 6 − 0.15 − µH Rwh write head resistance including lead; note 6 − 10 − Ω Cwh write head capacitance including lead; note 6 − tbf − pF Rext external reference resistor − 10 − kΩ 1997 Apr 08 I ref V ref = ---------R ext 16 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 4. Same comments for the given values as for the voltage input mode. The HIGH (respectively LOW) level input current is defined such that it produces the same effect at the output of the writer (Wx, Wy) as the HIGH (resp. LOW) level input voltage. Notes to the recommended operating conditions 1. A supply by-pass capacitor from VCC to ground or a low pass filter may be used to optimize the PSRR. 2. The supply voltage VCC(WD) must never be below VCC in normal mode, and two diode 1.4 V above VCC in servo mode. 5. The mismatch refers to the resistance of the two stripes of the same head. This is defined as follows: ∆(RMR) = abs(RMR1 − RMR2). 3. The given values should be interpreted in the way that the single ended voltage could swing from 0.2 to 0.75 V, and that the common mode voltage should be such that for any of the two states, the VIH(PECL) is less than VCC and VIL(PECL) is more than 1.5 V. PECL voltage swing: a wider peak-to-peak voltage swing can be used. In that case a current will flow through the WDI inputs. This current is approximately WDIx ( v ) – WDIy ( v ) – 1.4 equal to ------------------------------------------------------------------------200 1997 Apr 08 TDA5155 6. These parameters depend on the head model. The data given in the table are those used for testing. 7. The combination of maximum head resistance, lead resistance and bias current is not permitted. To avoid voltage breakthrough between heads and disk, the voltage over the MR elements is limited by two diode voltages. 17 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5155 13 CHARACTERISTICS VCC = 5.0 V; VCC(WD) = 8 V; VGND = 0 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Read characteristics IMR MR current adjust range Rext = 10 kΩ; 0.5 mA steps 5 − 20.5 mA ∆IMR tolerance (excluding Rext) IMR programmed at 10 mA − ±4 − % Gv(dif) differential voltage gain; note 1 from head inputs to RDx, RDy; RMR = 28 Ω; IMR = 10 mA; f = 20 MHz d4 = 0 − 160 − d4 = 1 − 226 − − 13 − Ω Ri(dif) differential input resistance IMR = 10 mA Ci(dif) differential input capacitance − 16 − pF THD total harmonic distortion − 1 − % BL lower signal gain pass-band −3 dB edge − − 100 kHz BH higher signal gain pass-band edge without gain boost (4 nH lead inductance) − 220 − MHz with gain boost (50 nH lead inductance) − 170 − MHz −3 dB; note 2 F noise figure RMR = 28 Ω; IMR = 10 mA; Tamb = 25 °C; f = 20 MHz − 3.0 3.2 dB Virn input referred noise voltage; RMR = 28 Ω; IMR = 10 mA; note 3 Tamb = 25 °C; f = 20 MHz − 0.9 1.0 nV/√Hz BF(L) lower noise band edge (+3 dB) RMR = 28 Ω; IMR = 10 mA; Tamb = 25 °C; no lead inductance − − 400 kHz BF(H) upper noise band edge (+3 dB) RMR = 28 Ω; IMR = 10 mA; Tamb = 25 °C; no lead inductance − 220 − MHz αcs channel separation; note 4 unselected head − 50 − dB PSRR power supply rejection ratio; f < 1 MHz; IMR = 10 mA note 5 f < 100 MHz; IMR = 10 mA − 80 − dB − 50 − dB f < 1 MHz − 45 − dB f < 100 MHz − 25 − dB CMRR 1997 Apr 08 common mode rejection ratio; note 5 from nRx-nRy to RDx-RDy RMR mismatch < 5% IMR = 10 mA 18 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads SYMBOL PARAMETER TDA5155 CONDITIONS MIN. DR rejection ratio of SCLK and SDATA; note 6 from SCLK, SDATA inputs to the − RDx-RDy outputs; a 200 mV (peak-to-peak) signal is applied to SCLK or SDATA inputs at 25 MHz, and measurement is performed at RDx-RDy VO(R)(dif) output DC offset voltage in read mode (differential after DC settling) DC voltage between RDx and RDy Zo(R) output impedance in read mode single ended Io(max)(dif) maximum differential output current Vo(cm) common mode output voltage in read mode ∆V o ( cm ) ---------------------∆V CC Zo(n)(dif) TYP. MAX. UNIT 50 − dB − − ±0.2 V − 16 − Ω − 4 − mA 1.0 1.5 2.0 V common mode DC supply rejection ratio in read mode − 20 − dB differential output impedance in other modes (write, standby, sleep) − 50 − kΩ RDx, RDy Write characteristics IWR write current adjust range (in the write drivers) Rext = 10 kΩ; 1 mA steps 20 35 51 mA ∆IWR tolerance (excluding Rext) IWR programmed at 35 mA − ±7 − % Vs(max)(p-p) maximum voltage swing (peak-to-peak value) VCC(WD) = 5 V − − 8 V VCC(WD) = 8 V (differential) − − 13 V − 200 − Ω − 5 − pF VCC(WD) = 8.0 V − − 1.8 ns VCC(WD) = 6.5 V − − 2.1 ns Ro(dif) differential output resistance Co(dif) differential output capacitance not including the head capacitance tr, tf write current rise/fall time without flip-flop (10% to 90%); note 7 Lh = 150 nH; Rh = 10 Ω; IWR = 35 mA; f = 20 MHz tas write current rise/fall time asymmetry; note 8 percentage of tr or tf (tr or tf and logic asymmetry) − − 5 % tpd propagation delay 50% of (WDIx/WDIy) to 50% of (Wx, Wy) write head short-circuited, data flip-flop by-passed − − 5 ns αcs channel separation not-selected head − 45 − dB 1997 Apr 08 19 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads SYMBOL PARAMETER TDA5155 CONDITIONS MIN. TYP. MAX. UNIT Switching characteristics fSCLK serial interface clock rate − − 25 MHz ∆Vo(cm) common mode DC output IMR = 10 mA; IWR = 35 mA voltage change from read to write mode − 200 − mV trec(W-R) write-to-read recovery time (AC and DC settling); note 9 read amplifier OFF: d5 = 0 − 3 4.5 µs read amplifier ON: d5 = 1 − 100 150 ns from 50% of the rising edge of R/W to steady state read-back signal: AC and DC settling at 90% (without load at RDx, RDy) tsw(R) head switching (in read mode), standby to read active and MR current change recovery time. (AC and DC settling); note 10 from falling edge of SEN to steady state read-back signal (without load at RDx, RDy) − 3 4.5 µs toff(R) read amplifier off time from falling edge of R/W to read head inactive − − 50 ns tst(W) write settling times; note 11 from 50% of the falling edge of R/W to 90% of the steady state write current (in write mode) − − 70 ns toff(W) write amplifier off time from rising edge of R/W to 10 × IWR (programmed) (IWR = 35 mA) − − 50 ns tsw(W) head switching (in write from falling edge of SEN to write − mode), and standby to write head active head active 50 70 ns tsw(S) switch time to and from sleep mode − − 100 µs − 72 80 mA from VCC (5 V) − 33 41 mA from VCC(WD) (5 to 8 V) − 54 61 mA − 0.25 1 mA − −0.02 − mA − 1.32 − V 1⁄ DC characteristics ICC(R) read mode supply current IMR = 10 mA; note 12 ICC(W) write mode supply current IWR = 35 mA; note 13 IDD(STB) standby mode supply current IDD(S) sleep mode supply current Vref reference voltage for Rext 1997 Apr 08 static 20 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads Notes to the characteristics 5. 1. The differential voltage gain depends on the MR resistance. It can be improved by programming the d4 bit in the configuration register. The PSRR (in dB) is defined as input referred ratio: Gv PSRR = 20 × log ------- , where Gv is the differential input Gp to differential output gain, and Gp is the power supply to differential output gain.The CMRR (in dB) is defined Gv as input referred ratio: CMRR = 20 × log ----------- , where G cm 2. The gain boost implements a pole-zero combination: The +3 dB gain boost corner frequency is 800 MHz --------------------------------------------------------------------- . The −3 dB gain 8.d3 + 4.d2 + 2.d1 + 1.d0 attenuation corner frequency is 800 MHz --------------------------------------------------------------------- , where d3, d2, d1 and d0 8.d3 + 4.d2 + 2.d1 + 1.d0 are to be programmed via the serial interface. In practical use, the bandwidth is limited by the inductance of the connection between the MR heads and the pre-amplifier. Gv is the differential input to differential output gain and Gcm is the common mode input to differential output gain. Flex and board lay-out may affect these parameters significantly. 6. This refers to the crosstalk from SCLK and SDATA inputs via the read inputs to RDx and RDy. Two cases can be distinguished: a) When SEN is LOW, SCLK and SDATA are prohibited reaching the device and crosstalk is low. 3. Noise calculation a) Definitions: The amplifier has a low input resistance. No lead resistance is taken into account. The input referred noise voltage, excluding the noise of the MR resistors, is defined V no 2 2 as: ( V irn ) = --------- – 4kT × ( R MR1 + R MR2 ) , Gv b) Programming via the serial interface is done with SEN HIGH. Then crosstalk can occur. A careful design of the board or flex-foil is required to avoid crosstalk via this path. 7. The rise and fall times depend on the write amplifier/write head combination. Lh and Rh represent the components on the evaluation board. Parasitic capacitances also limit the performance. where Gv is the voltage gain, Vno is the noise voltage at the output of the amplifier, k is the Boltzmann constant and T is the temperature in K. The noise figure is defined as follows: V no 2 --------G v F = 10 × log ------------------------------------------------------------ in 1 Hz 4kT × ( R + R ) MR1 MR2 8. The write current rise/fall time asymmetry is defined by tr – tf ----------------------2 ( tr + tf) 9. Write-to-read recovery time includes the write mode to read mode switching using the R/W pin on the same head (see Fig.5). The AC signal reaches its full amplitude few tens of ns after appearing at the reader RDx and RDy outputs. bandwidth. Note that RMR includes all resistances between Rx or Ry to ground. b) Noise figure versus IMR and RMR: Table 1 shows the variation of the noise figure with IMR and RMR. 10. In read mode, the head switching, standby to read active switching and changing MR current include fast current settling (see Fig.5). The AC signal reaches its full amplitude few tenth of ns after appearing at the reader RDx and RDy outputs. c) Input referred noise voltage: The input referred noise voltage calculation can be significantly different (from 1.0 to 0.44 nV/√Hz for instance) by taking an equivalent signal-to-noise ratio into account when using two MR stripes (28 Ω for each stripe) or one MR stripe (42 Ω). It assumes that the signal coming from the head is larger for a dual-stripe head than for a single-stripe head (50% extra signal for a dual-stripe head). 11. Write settling time includes the read mode to write mode switching using the R/W pin. 12. The typical supply current in read mode depends on the bias current for the MR element. 13. The typical supply current in write mode also depends on the write current. 4. The channel separation is defined by the ratio of the gain response of the amplifier using the selected head H(n) to the gain response of the amplifier using the adjacent head H(n ±1), head H(n) being selected. 1997 Apr 08 TDA5155 21 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads Table 1 TDA5155 Noise figure F (dB) RMR (Ω) IMR = 7 mA IMR = 10 mA IMR = 15 mA 20 2.7 2.9 3.1 25 2.8 3.0 3.3 30 2.9 3.1 3.5 handbook, full pagewidth R/W RDx-RDy trec(W-R) toff(R) MGG985 Fig.5 Timing diagram of the reader: write-to-read switching on the same logic head. handbook, full pagewidth SEN RDx-RDy tsw(R) MGG986 Fig.6 Timing diagram of the reader: typical head, current and standby-to-read characteristics. 1997 Apr 08 22 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5155 14 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 297027/20/01/pp24 Date of release: 1997 Apr 08 Document order number: 9397 750 01427