INTEGRATED CIRCUITS DATA SHEET 74AUC1G04 Inverter Preliminary specification File under Integrated Circuits, IC24 2002 Nov 12 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 FEATURES DESCRIPTION • Wide supply voltage range from 0.8 to 2.7 V The 74AUC1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device. • Performance optimised for VCC = 1.8 V • High noise immunity Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. • Complies with JEDEC standard: • CMOS low power consumption This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging current backflow through the device when it is powered down. • Latch-up performance exceeds 250 mA The 74AUC1G04 provides the inverting buffer. – JESD76 (1.65 to 1.95 V) • 8 mA output drive (VCC = 1.65 V) • ESD protection: 2000 V Human Body Model (A 114-A) 200 V Machine Model (A 115-A) • 3.3 V tolerant inputs/outputs • SC-88A and SC-74A package. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; input slewrate ≥ 1 V/ns. SYMBOL tPHL/tPLH PARAMETER propagation delay input A to output Y CI input capacitance CPD power dissipation capacitance per buffer CONDITIONS UNIT VCC = 0.8 V; CL = 15 pF; RL = 2 kΩ 4.4 ns VCC = 1.2 V; CL = 15 pF; RL = 2 kΩ 1.8 ns VCC = 1.5 V; CL = 15 pF; RL = 2 kΩ 1.3 ns VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ 1.4 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 1.2 ns 4 pF 14 pF VCC = 1.8 V; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 2002 Nov 12 TYPICAL 2 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 FUNCTION TABLE See note 1. INPUT OUTPUT A Y L H H L Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING 74AUC1G04GW −40 to +85 °C 5 SC-88A plastic SOT353 FC 74AUC1G04GV −40 to +85 °C 5 SC-74A plastic SOT753 F02 PINNING PIN SYMBOL DESCRIPTION 1 n.c. not connected 2 A data input A 3 GND ground (0 V) 4 Y data output Y 5 VCC supply voltage handbook, halfpage n.c. 1 A 2 GND 5 VCC handbook, halfpage 2 04 3 4 Y A Y 4 MNA108 MNA107 Fig.1 Pin configuration. 2002 Nov 12 Fig.2 Logic symbol. 3 Philips Semiconductors Preliminary specification Inverter handbook, halfpage 74AUC1G04 1 2 4 handbook, halfpage Y A MNA110 MNA109 Fig.3 IEE/IEC logic symbol. Fig.4 Logic diagram. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 0.8 2.7 V VI input voltage 0 2.7 V VO output voltage active mode 0 VCC V VCC = 0 V; Power-down mode 0 2.7 V Tamb operating ambient temperature −40 +85 °C tr,tf (∆t/∆f) input rise and fall times 0 20 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. −0.5 MAX. VCC supply voltage IIK input diode current VI < 0 − −50 mA VI input voltage note 1 −0.5 +3.6 V IOK output diode current VO > VCC or VO < 0 − ±50 mA VO output voltage active mode; notes 1 and 2 −0.5 VCC + 0.5 V +3.6 V ±60 mA Power-down mode; notes 1 and 2 −0.5 VO = 0 to VCC − +3.6 UNIT V IO output source or sink current ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C PD power dissipation per package − 250 mW for temperature range from −40 to +85 °C Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC =0 (Powered-down mode), the output voltage can be 2.7 V in normal operation. 2002 Nov 12 4 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL VIL VOH VOL −40 to +85 PARAMETER VCC (V) OTHER VIH Tamb (°C) MIN. UNIT TYP.(1) MAX. HIGH-level input voltage 0.8 VCC − − V 1.1 to 2.3 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V LOW-level input voltage 0.8 − − GND V 1.1 to 2.3 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V VCC − 0.1 − − V − 0.55 − V HIGH-level output VI = VIH or VIL; IO = −100 µA 0.8 to 2.7 voltage VI = VIH or VIL; IO =− 700 µA 0.8 LOW-level output voltage VI = VIH or VIL; IO =− 3 mA 1.1 VCC − 0.3 − − V VI = VIH or VIL; IO = −5 mA 1.5 VCC − 0.4 − − V VI = VIH or VIL; IO = −8 mA 1.65 VCC − 0.45 − − V VI = VIH or VIL; IO = −9 mA 2.3 1.8 − − V VI = VIH or VIL; IO = 100 µA 0.8 to 2.7 − − 0.2 V VI = VIH or VIL; IO = 700 µA 0.8 − 0.25 − V VI = VIH or VIL; IO = 3 mA 1.1 − − 0.3 V VI = VIH or VIL; IO = 5 mA 1.5 − − 0.4 V VI = VIH or VIL; IO = 8 mA 1.65 − − 0.45 V VI = VIH or VIL; IO = 9 mA 2.3 − − 0.6 V II input leakage current VI = VCC or GND 0 to 2.7 − ±0.1 ±5 µA Ioff power OFF leakage current VI or VO = 2.7 V 0 − ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 0.8 to 2.7 − 0.1 10 µA Note 1. All typical values are at VCC = 1.8 V and Tamb = 25 °C. 2002 Nov 12 5 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 AC CHARACTERISTICS GND = 0 V; input slewrate ≥ 1 V/ns. Tamb (°C) TEST CONDITIONS SYMBOL VCC (V) CL(pF) RL(kΩ) 0.8 15 1.1 to 1.3 15 WAVEFORMS tPHL/tPLH −40 to +85 PARAMETER propagation delay input A to output Y see Figs 5 and 6 MIN. TYP. MAX. 2 − 4.4 2 0.8 1.8 15 2 0.5 1.3 2.0 ns 1 0.6 1.4 2.2 ns 2.3 to 2.7 30 0.5 0.5 1.2 1.9 ns VM tPLH VM MNA111 INPUT 0.8 to 2.7 V VM VI 0.5 × VCC VCC Slewrate ≥ 1 V/ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 Inputs A, B to output Y propagation delay times. 2002 Nov 12 ns 30 tPHL VCC 3.0 1.65 to 1.95 handbook, halfpage Y output ns 1.4 to 1.6 AC WAVEFORMS A input UNIT 6 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 VEXT handbook, full pagewidth VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL MNA616 VEXT VCC VI CL <1.65 V VCC 15 pF 1.65 to 1.95 V VCC 2.3 to 2.7 V VCC RL TPLH/TPHL TPZH/TPHZ TPZL/TPLZ 2 kΩ open GND 2 × VCC 30 pF 1 kΩ open GND 2 × VCC 30 pF 0.5 kΩ open GND 2 × VCC Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”). RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Load circuitry for switching times. 2002 Nov 12 7 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 PACKAGE OUTLINE Plastic surface mounted package; 5 leads SOT353 D E B y X A HE 5 v M A 4 Q A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E (2) e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION SOT353 2002 Nov 12 REFERENCES IEC JEDEC EIAJ SC-88A 8 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 Plastic surface mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION SOT753 2002 Nov 12 REFERENCES IEC JEDEC JEITA SC-74A 9 EUROPEAN PROJECTION ISSUE DATE 02-04-16 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2002 Nov 12 10 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Nov 12 11 Philips Semiconductors Preliminary specification Inverter 74AUC1G04 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 Nov 12 12