PHILIPS UDA1324TS

INTEGRATED CIRCUITS
DATA SHEET
UDA1324TS
Ultra low-voltage stereo filter DAC
Preliminary specification
Supersedes data of 1999 Oct 12
File under Integrated Circuits, IC01
2000 Jan 20
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
FEATURES
General
• Low power consumption
• Ultra low power supply voltage from 1.9 to 2.7 V
• Selectable control via L3 microcontroller interface or via
static pin control
• System clock frequencies of 256fs, 384fs and 512fs
selectable via L3 interface or 256fs and 384fs via static
pin control
APPLICATIONS
• Supports sampling frequencies (fs) from 16 to 48 kHz
• Portable digital audio equipment.
• Integrated digital filter plus non inverting
Digital-to-Analog Converter (DAC)
GENERAL DESCRIPTION
• No analog post filtering required for DAC
The UDA1324TS is a single-chip stereo DAC employing
bitstream conversion techniques. The ultra low-voltage
requirements make the device eminently suitable for use
in portable digital audio equipment which incorporates
playback functions.
• Slave mode only applications
• Easy application
• Small package size (SSOP16).
Multiple format input interface
The UDA1324TS supports the I2S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB-justified
serial data format with word lengths of 16, 18 and 20 bits.
• L3 mode: I2S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible
• Static pin mode: I2S-bus or LSB-justified
16, 18 and 20 bits format compatible
The UDA1324TS can be used in two modes: L3 mode or
static pin mode.
• 1fs input format data rate.
DAC digital sound processing
In the L3 mode, all digital sound processing features must
be controlled via the L3 interface, including the selection of
the system clock setting.
• Digital logarithmic volume control in L3 mode
• Digital de-emphasis selection for 32, 44.1 and 48 kHz
sampling frequencies in L3 mode or 44.1 kHz sampling
frequency in static pin mode
In the two static modes, the UDA1324TS can be operated
in the 256fs and 384fs system clock mode. Muting,
de-emphasis for 44.1 kHz and four digital input formats
(I2S-bus or LSB-justified 16, 18 and 20 bits) can be
selected via static pins. The L3 interface cannot be used in
this application mode, so volume control is not available in
this mode.
• Soft mute control in static pin mode or in L3 mode.
Advanced audio configuration
• Stereo line output (volume control in L3 mode)
• High linearity, wide dynamic range and low distortion.
ORDERING INFORMATION
TYPE
NUMBER
UDA1324TS
2000 Jan 20
PACKAGE
NAME
DESCRIPTION
VERSION
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
2
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
analog supply voltage
1.9
2.0
2.7
V
VDDD
digital supply voltage
1.9
2.0
2.7
V
IDDA
analog supply current
VDDA = 2.0 V
−
3.0
−
mA
IDDD
digital supply current
VDDD = 2.0 V
−
1.5
−
mA
Vo(rms)
output voltage (RMS value)
note 2
−
500
−
mV
(THD + N)/S
total harmonic distortion-plus-noise to at 0 dB
signal ratio
at −60 dB; A-weighted
−
−83
−78
dB
−
−36
−
dB
S/N
signal-to-noise ratio
−
97
−
dB
αcs
channel separation
−
100
−
dB
Tamb
ambient temperature
−40
−
+70
°C
DAC; note 1
code = 0; A-weighted
Notes
1. The analog performance figures are measured at 2.0 V supply voltage.
2. The DAC output voltage scales linearly with the power supply voltage.
BLOCK DIAGRAM
handbook, full pagewidth
VSSD
VDDD
4
BCK
WS
DATAI
7
11
1
2
3
DIGITAL INTERFACE
UDA1324TS
SYSCLK
5
6
CONTROL
INTERFACE
10
9
8
APPSEL
APPL0
APPL1
APPL2
APPL3
VOLUME/MUTE/DE-EMPHASIS
INTERPOLATION FILTER
NOISE SHAPER
VOUTL
DAC
14
13
VDDA
15
VSSA
Fig.1 Block diagram.
2000 Jan 20
16
DAC
3
12
Vref(DAC)
VOUTR
MBK770
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
PINNING
FUNCTIONAL DESCRIPTION
SYMBOL
PIN
System clock
DESCRIPTION
BCK
1
bit clock input
WS
2
word select input
DATAI
3
data input
The UDA1324TS operates in the slave mode only.
Therefore, in all applications the system devices must
provide the system clock. The system frequency (fsys) is
selectable and depends on the application mode.
The options are: 256fs, 384fs and 512fs for the L3 mode
and 256fs or 384fs for the static pin mode. The system
clock must be locked in frequency to the digital interface
input signals.
VDDD
4
digital supply voltage
VSSD
5
digital ground
SYSCLK
6
system clock input: 256fs, 384fs
and 512fs
APPSEL
7
application mode select input
APPL3
8
application input pin 3
The UDA1324TS supports sampling frequencies (fs) from
16 to 48 kHz.
APPL2
9
application input pin 2
Application modes
APPL1
10
application input pin 1
APPL0
11
application input pin 0
The application mode can be set with the three-level
pin APPSEL (see Table 1):
Vref(DAC)
12
DAC reference voltage
• L3 mode
VDDA
13
analog supply voltage for DAC
• Static pin mode with fsys = 384fs
VOUTL
14
left channel output
• Static pin mode with fsys = 256fs.
VSSA
15
analog ground for DAC
VOUTR
16
right channel output
Table 1
Selecting application mode and system clock
frequency via pin APPSEL
VOLTAGE ON
PIN APPSEL
MODE
fsys
VSSD
L3 mode
256fs, 384fs or 512fs
0.5VDDD
VDDD
handbook, halfpage
BCK 1
15 VSSA
DATAI 3
The function of an application input pin (active HIGH)
depends on the application mode (see Table 2).
14 VOUTL
UDA1324TS
VSSD 5
13 VDDA
Table 2
Functions of application input pins
12 Vref(DAC)
SYSCLK 6
11 APPL0
APPSEL 7
10 APPL1
APPL3 8
9
FUNCTION
PIN
APPL2
MBK769
L3 MODE
STATIC PIN MODE
APPL0
TEST
MUTE
APPL1
L3CLOCK
DEEM
APPL2
L3MODE
SF0
APPL3
L3DATA
SF1
For example, in the static pin mode the output signal can
be soft muted by setting pin APPL0 to HIGH.
De-emphasis can be switched on for 44.1 kHz by setting
pin APPL1 to HIGH; setting pin APPL1 to LOW will disable
de-emphasis.
Fig.2 Pin configuration.
2000 Jan 20
256fs
16 VOUTR
WS 2
VDDD 4
384fs
static pin mode
4
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
Interpolation filter
In the L3 mode, pin APPL0 must be set to LOW. It should
be noted that when the L3 mode is used, an initialization
must be performed when the IC is powered-up.
The digital filter interpolates from 1fs to 128fs by cascading
a recursive filter and a FIR filter (see Table 4).
Digital interface
Table 4
DATA FORMATS
The digital interface of the UDA1324TS supports multiple
format inputs (see Fig.3).
VALUE (dB)
Pass-band ripple
0 to 0.45fs
±0.1
>0.55fs
−50
0 to 0.45fs
108
Noise shaper
The BCK clock can be up to 64fs, or in other words the
BCK frequency is 64 times the Word Select (WS)
frequency or less: fBCK ≤ 64 × fWS.
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream Digital-to-Analog Converter (FSDAC).
Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital
interface.
Filter stream DAC
The UDA1324TS also accepts double speed data for
double speed data monitoring purposes.
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage capable of driving a line output.
L3 MODE
• I2S-bus format with data word length of up to 20 bits
• MSB-justified format with data word length up to 20 bits
• LSB-justified format with data word length of
16, 18 or 20 bits.
STATIC PIN MODE
• I2S-bus format with data word length of up to 20 bits
The output voltage of the FSDAC scales linearly with the
power supply voltage.
• LSB-justified format with data word length of
16, 18 or 20 bits.
These four formats are selectable via the static pin codes
SF0 and SF1 (see Table 3).
Input format selection using SF0 and SF1
SF0
SF1
I2S-bus
0
0
LSB-justified 16 bits
0
1
LSB-justified 18 bits
1
0
LSB-justified 20 bits
1
1
2000 Jan 20
CONDITION
Dynamic range
The WS signal must have a 50% duty factor for all
LSB-justified formats.
FORMAT
ITEM
Stop band
Left and right data-channel words are time multiplexed.
Table 3
Interpolation filter characteristics
5
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2
>=8
3
2
3
MSB
B2
1
BCK
MSB
DATA
B2
>=8
MSB
I2S-BUS FORMAT
LEFT
WS
1
2
RIGHT
>=8
3
1
2
>=8
3
BCK
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT
WS
LEFT
RIGHT
16
15
2
1
16
B15 LSB
MSB
15
2
1
BCK
DATA
MSB
B2
B2
B15 LSB
Philips Semiconductors
1
Ultra low-voltage stereo filter DAC
ndbook, full pagewidth
2000 Jan 20
RIGHT
LEFT
WS
LSB-JUSTIFIED FORMAT 16 BITS
6
WS
LEFT
RIGHT
18
17
16
15
2
1
18
B17 LSB
MSB
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B2
B3
B4
B17 LSB
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
20
RIGHT
19
18
17
16
15
2
1
20
B19 LSB
MSB
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B2
B3
B4
B5
B6
B19 LSB
LSB-JUSTIFIED FORMAT 20 BITS
LEFT
23
22
21
20
RIGHT
19
18
17
16
15
1
24
B23 LSB
MSB
2
23
22
21
20
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B2
LSB-JUSTIFIED FORMAT 24 BITS
Fig.3 Digital interface input data formats.
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MBL121
UDA1324TS
24
Preliminary specification
WS
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
L3 INTERFACE
The fundamental timing of data transfers (see Fig.5) is
essentially the same as the address mode. The maximum
input clock frequency and data rate is 64fs.
The following system and digital sound processing
features can be controlled in the L3 mode of the
UDA1324TS:
• De-emphasis for 32, 44.1 and 48 kHz
Data transfer can only be in one direction, consisting of
input to the UDA1324TS to program sound processing and
other functional features. All data transfers are by 8-bit
bytes. Data will be stored in the UDA1324TS after
reception of a complete byte.
• Volume
A multi-byte transfer is illustrated in Fig.6.
• System clock frequency
• Data input format
• Soft mute.
Registers
The exchange of data and control information between the
microcontroller and the UDA1324TS is accomplished
through a serial interface comprising the following signals:
The sound processing and other feature values are stored
in independent registers. The first selection of the registers
is achieved by the choice of data type that is transferred.
This is performed in the address mode using bit 1 and bit 0
(see Table 5).
• L3DATA
• L3MODE
• L3CLOCK.
Table 5
Information transfer through the microcontroller bus is
organized in accordance with the L3 interface format, in
which two different modes of operation can be
distinguished: address mode and data transfer mode.
Selection of data transfer
BIT 1
BIT 0
TRANSFER
0
0
data (volume, de-emphasis, mute)
0
1
not used
Address mode
1
0
The address mode (see Fig.4) is required to select a
device communicating via the L3 interface and to define
the destination registers for the data transfer mode.
status (system clock frequency,
data input format)
1
1
not used
The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6). The other bits in the data byte
(bit 5 to bit 0) represent the value that is placed in the
selected registers.
Data bits 7 to 2 represent a 6-bit device address where
bit 7 is the MSB. The address of the UDA1324TS is
000101 (bit 7 to bit 2). If the UDA1324TS receives a
different address, it will deselect its microcontroller
interface logic.
The ‘status’ settings are given in Table 6 and the ‘data’
settings are given in Table 7.
Data transfer mode
The selected address remains active during subsequent
data transfers until the UDA1324TS receives a new
address command.
2000 Jan 20
7
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
handbook, full pagewidth
L3MODE
tsu(L3)A
th(L3)A
tCLK(L3)L
tsu(L3)A
tCLK(L3)H
th(L3)A
L3CLOCK
Tcy(CLK)(L3)
tsu(L3)DA
th(L3)DA
BIT 7
BIT 0
L3DATA
MGL723
Fig.4 Timing address mode.
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE
tCLK(L3)L
Tcy(CLK)L3
tCLK(L3)H
tsu(L3)D
th(L3)D
L3CLOCK
th(L3)DA
tsu(L3)DA
L3DATA
WRITE
BIT 7
BIT 0
MGL882
Fig.5 Timing data transfer mode.
2000 Jan 20
8
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
tstp(L3)
handbook, full pagewidth
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGL725
Fig.6 Multibyte data transfer.
Programming the features
When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format
can be controlled.
Table 6
Data transfer of type ‘status’
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
SC1
SC0
IF2
IF1
IF0
0
REGISTER SELECTED
SC = system clock frequency (2 bits); see Table 8
IF = data input format (3 bits); see Table 9
1
0
0
0
0
0
0
0
not used
When the data transfer of type ‘data’ is selected, the features for volume, de-emphasis and mute can be controlled.
Table 7
Data transfer of type ‘data’
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
0
VC5
VC4
VC3
VC2
VC1
VC0
0
1
0
0
0
0
0
0
not used
1
0
0
DE1
DE0
MT
0
0
DE = de-emphasis (2 bits); see Table 10
1
1
0
0
0
0
0
1
default setting
VC = volume control (6 bits); see Table 11
MT = mute (1 bit); see Table 12
2000 Jan 20
9
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
SYSTEM CLOCK FREQUENCY
VOLUME CONTROL
The system clock frequency is a 2-bit value to select the
external clock frequency.
The volume control is a 6-bit value to program the volume
attenuation from 0 to −60 dB and −∞ dB in steps of 1 dB.
Table 8
Table 11 Volume settings
SC1
System clock settings
SC0
FUNCTION
VC5
VC4
VC3
VC2
VC1
VC0
VOLUME (dB)
0
0
512fs
0
0
0
0
0
0
0
0
1
384fs
0
0
0
0
0
1
0
1
0
256fs
0
0
0
0
1
0
−1
1
1
not used
0
0
0
0
1
1
−2
:
:
:
:
:
:
:
DATA FORMAT
1
1
0
0
1
1
The data format is a 3-bit value to select the used data
format.
1
1
0
1
0
0
−51
1
1
0
1
0
1
Table 9
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
IF2
Data input format settings
IF1
IF0
FORMAT
0
0
0
I2S-bus
0
0
1
LSB-justified 16 bits
0
1
0
LSB-justified 18 bits
0
1
1
LSB-justified 20 bits
1
0
0
MSB-justified
1
0
1
not used
1
1
0
not used
1
1
1
not used
MUTE
DE-EMPHASIS
Mute is a 1-bit value to enable the digital mute.
De-emphasis is a 2-bit value to enable the digital
de-emphasis filter.
Table 12 Mute setting
MT
Table 10 De-emphasis settings
DE1
0
0
1
1
DE0
0
1
0
1
2000 Jan 20
FUNCTION
no de-emphasis
de-emphasis, 32 kHz
de-emphasis, 44.1 kHz
de-emphasis, 48 kHz
10
FUNCTION
0
no muting
1
muting
−52
−54
−57
−60
−∞
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDD
digital supply voltage
note 1
−
5.0
V
VDDA
analog supply voltage
note 1
−
5.0
V
Txtal(max)
maximum crystal temperature
−
150
°C
Tstg
storage temperature
−65
+125
°C
Tamb
ambient temperature
−40
+85
°C
Ves
electrostatic handling voltage
note 2
−3000
+3000
V
note 3
−300
+300
V
Isc(DAC)
short-circuit current of DAC
output short-circuited to VSSA(DAC)
−
450
mA
output short-circuited to VDDA(DAC)
−
300
mA
note 4
Notes
1. All supply connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pin 14 which can withstand ESD
pulses of −2500 to +2500 V.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
4. Short-circuit test at Tamb = 0 °C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
190
K/W
in free air
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611-E”.
DC CHARACTERISTICS
VDDD = VDDA = 2.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD); unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
analog supply voltage
note 1
1.9
2.0
2.7
V
VDDD
digital supply voltage
note 1
1.9
2.0
2.7
V
IDDA
analog supply current
operating
−
3.0
−
mA
IDDD
digital supply current
operating
−
1.5
−
mA
2000 Jan 20
11
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
SYMBOL
PARAMETER
UDA1324TS
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3
VIH
HIGH-level input voltage
0.8VDDD
−
−
V
VIL
LOW-level input voltage
−
−
0.2VDDD
V
ILI
input leakage current
−
−
1
µA
CI
input capacitance
−
−
10
pF
Three-level input: pin APPSEL
VIH
HIGH-level input voltage
0.8VDDD
−
VDDD + 0.5 V
VIM
MIDDLE-level input voltage
0.3VDDD
−
0.7VDDD
V
VIL
LOW-level input voltage
−0.5
−
0.2VDDD
V
DAC
Vref(DAC)
reference voltage
referenced to VSSA
0.45VDDA
0.5VDDA
0.55VDDA
V
Io(max)
maximum output current
(THD + N)/S < 0.1%;
RL = 5 kΩ
−
0.16
−
mA
RO
output resistance
−
0.15
2.0
Ω
RL
load resistance
3
−
−
kΩ
CL
load capacitance
−
−
50
pF
note 2
Notes
1. All supply connections must be made to the same external power supply unit.
2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
AC CHARACTERISTICS
VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DAC
Vo(rms)
output voltage (RMS value)
−
500
−
mV
∆Vo
unbalance voltage between
channels
−
0.1
−
dB
(THD + N)/S
total harmonic
distortion-plus-noise to
signal ratio
at 0 dB
−
−83
−78
dB
at −60 dB; A-weighted
−
−36
−
dB
S/N
signal-to-noise ratio
code = 0; A-weighted
−
97
−
dB
αcs
channel separation
−
100
−
dB
PSRR
power supply ripple rejection fripple = 1 kHz;
ratio
Vripple = 100 mV (p-p)
−
50
−
dB
2000 Jan 20
12
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
TIMING
VDDD = VDDA = 1.9 to 2.7 V; Tamb = −40 to +85 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock (see Fig.7)
Tsys
system clock cycle time
tCWL
LOW-level system clock pulse width
tCWH
HIGH-level system clock pulse width
fsys = 256fs
78
88
244
ns
fsys = 384fs
52
59
162
ns
fsys = 512fs
39
44
122
ns
fsys < 19.2 MHz
0.3Tsys
−
0.7Tsys
ns
fsys ≥ 19.2 MHz
0.4Tsys
−
0.6Tsys
ns
fsys < 19.2 MHz
0.3Tsys
−
0.7Tsys
ns
fsys ≥ 19.2 MHz
0.4Tsys
−
0.6Tsys
ns
Digital interface with I2S-bus (see Fig.8)
Tcy(BCK)
bit clock cycle time
300
−
−
ns
tBCKH
bit clock HIGH time
100
−
−
ns
tBCKL
bit clock LOW time
100
−
−
ns
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
tsu(DATAI)
data input set-up time
20
−
−
ns
th(DATAI)
data input hold time
0
−
−
ns
tsu(WS)
word select set-up time
20
−
−
ns
th(WS)
word select hold time
10
−
−
ns
Control L3 interface (see Figs 4 and 5)
Tcy(CLK)L3
L3CLOCK cycle time
500
−
−
ns
tCLK(L3)H
L3CLOCK HIGH time
250
−
−
ns
tCLK(L3)L
L3CLOCK LOW time
250
−
−
ns
tsu(L3)A
L3MODE set-up time for address mode
190
−
−
ns
th(L3)A
L3MODE hold time for address mode
190
−
−
ns
tsu(L3)D
L3MODE set-up time for data transfer
mode
190
−
−
ns
th(L3)D
L3MODE hold time for data transfer
mode
190
−
−
ns
tsu(L3)DA
L3DATA set-up time for data transfer and
address mode
190
−
−
ns
th(L3)DA
L3DATA hold time for data transfer and
address mode
30
−
−
ns
tstp(L3)
L3MODE stop time for data transfer
mode
190
−
−
ns
2000 Jan 20
13
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
t CWH
handbook, full pagewidth
MGR984
t CWL
Tsys
Fig.7 System clock timing.
handbook, full pagewidth
WS
th(WS)
tBCKH
tr
tsu(WS)
tf
BCK
tsu(DATAI)
tBCKL
Tcy(BCK)
th(DATAI)
DATAI
MGL880
Fig.8 I2S-bus timing.
2000 Jan 20
14
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
APPLICATION INFORMATION
analog
supply voltage
handbook, full pagewidth
digital
supply voltage
R2
1Ω
C1
R3
1Ω
100 µF
(16 V)
system
clock
R1
SYSCLK
47 Ω
C5
C6
100 nF
(63 V)
VSSA
100 nF
(63 V)
15
VDDA
13
VSSD
5
VDDD
4
6
14
BCK
WS
DATAI
APPSEL
47 µF
(16 V)
1
2
APPL0
APPL2
APPL3
R4
100 Ω
left
output
R5
10 kΩ
3
7
UDA1324TS
APPL1
VOUTL C2
16
VOUTR C3
47 µF
(16 V)
R6
100 Ω
right
output
R7
10 kΩ
11
10
9
12
8
Vref(DAC)
C7
100 nF
(63 V)
C4
47 µF
(16 V)
MBK771
Fig.9 Application diagram.
2000 Jan 20
15
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
PACKAGE OUTLINE
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
D
SOT369-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.5
0.15
0.00
1.4
1.2
0.25
0.32
0.20
0.25
0.13
5.30
5.10
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.45
0.65
0.45
0.2
0.13
0.1
0.48
0.18
10
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT369-1
2000 Jan 20
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
99-12-27
MO-152
16
o
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Jan 20
17
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Jan 20
18
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
NOTES
2000 Jan 20
19
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Internet: http://www.semiconductors.philips.com
SCA 69
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/25/03/pp20
Date of release: 2000
Jan 20
Document order number:
9397 750 06676