INFINEON BGF125

Data Sheet, V2.0, April 2009
BGF125
S I M C a r d I n t e r f a c e F i l te r a n d E S D P r o t e c t i o n
Small Signal Discretes
Edition 2009-04-01
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2009.
All Rights Reserved.
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BGF125
SIM Card Interface Filter and ESD Protection
BGF125
Revision History: 2009-04-01, V2.0
Previous Version: 2008-05-27, V1.0
Page
Subjects (major changes since last revision)
all
target status removed
5, 6
Figure 2 and Figure 3 updated
7
Figure 5 added
Data Sheet
3
V2.0, 2009-04-01
BGF125
SIM Card Interface Filter and ESD Protection
BGF125
BGF125
Features
• ESD protection circuit and interface filter for SIM cards
• Reduced line capacitance of 12 pF maximum
• ESD protection according to IEC61000-4-2 for ±15 kV contact discharge on
external IOs
• Wafer level package with SnAgCu solder balls
• 400 µm solder ball pitch
• RoHS and WEEE compliant package
WLP-8-10-N-3D
Description
BGF125 is an ESD protection and filtering circuit for SIM card interfaces. All external IOs are protected against
ESD pulses of ±15 kV contact discharge according to IEC61000-4-2. The wafer level package is a green lead-free
and halogen-free package with a size of only 1.15 mm x 1.15 mm and a total height of 0.6 mm
Ext. IOs
C2
A3
R1, 100Ω
A2
B3
R2, 47Ω
B1
C3
R3, 100Ω
C1
GND, B2
BGF125 _schematic.vsd
Figure 1
Schematic
Type
Package
Marking
Chip
BGF125
WLP-8-10
25
N0745
Table 1
Maximum Ratings
Parameter
Voltage at all pins to GND
Operating temperature range
Storage temperature range
Summed up input power for all pins
Symbol
VP
TOP
TSTG
Pin
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
0
–
5
V
–
-40
–
+85
°C
–
-65
–
+150
°C
–
–
–
60
mW
TS < 70 °C
-2
–
2
kV
–
-15
–
15
kV
–
Electrostatic Discharge According to IEC61000-4-2
Contact discharge at internal pins A3, B3, C3
VESD
Contact discharge at external pins A2, B1, C1, VESD
C2
Data Sheet
4
V2.0, 2009-04-01
BGF125
SIM Card Interface Filter and ESD Protection
BGF125
Electrical Characteristics1)
Table 2
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
80
100
120
Ω
–
37.6
47
56.4
Ω
–
Leakage current of ESD protection diodes
R1,3
R2
IL
–
–
1
2
100
200
nA
nA
Breakdown voltage of ESD diodes2)
V(BR)
–
18.5
-12.5
–
V
Line capacitance
Capacitance of all lines to GND
1) at TA = 25 °C
CT
8
10
12
pF
V=3V
V=5V
I(BR) = 1 mA
I(BR) = -1 mA
V=0V
Resistors R1, R3
Resistor R2
2) after snap-back
BGF125 insertion loss
0
-5
B1-B3
A2-A3
-10
dB
-15
-20
-25
-30
-35
-40
1
10
100
1000
10000
MHz
Figure 2
Data Sheet
Insertion Loss, ZS = ZL = 50 Ω
5
V2.0, 2009-04-01
BGF125
SIM Card Interface Filter and ESD Protection
BGF125
BGF125 cross talk
0
-20
C1-C2
-40
dB
C1-B3
-60
-80
-100
1
10
100
1000
10000
MHz
Figure 3
Typical Cross Talk, ZS = ZL = 50 Ω
Package Outlines
Solder balls face up
0.6 ±0.05
B
0.4
C
0.4
2 x 0.4 = 0.8
(0.175 ±0.05)
(0.175 ±0.05)
C1
C2
C3
B1
B2
B3
A2
A3
2 x 0.4 = 0.8
8x
0.08 C
8x
COPLANARITY
ø0.05 M A B
0.25 ±0.04 1)
A
1.15 ±0.05
0.1 C
(0.175 ±0.05)
Pin 1
Corner Index Area 2)
SEATING PLANE 3)
0.2 ±0.05
STANDOFF
1.15 ±0.05
(0.175 ±0.05)
Solder balls face down
1) Dimension is measured at the maximum solder ball diameter, parallel to primary datum C
2) A1 corner identified by marking
3) Primary datum C and seating plane are defined by the domed crowns of the balls
WLP-8-10-N-PO V02
Figure 4
Data Sheet
WLP-8-10 (Wafer Level Package)
6
V2.0, 2009-04-01
BGF125
SIM Card Interface Filter and ESD Protection
BGF125
Footprint
0.8
0.8
0.4
0.4
0.25
WLP-8-10-N-FP V02
Figure 5
Recommended PCB pad design for reflow soldering
Tape
0.25
Pin 1
Corner Index Area
Figure 6
1.33
8
1.33
4
0.75
WLP-8-10-N-TP V01
Tape for BGF125 / WLP-8-10
You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
Data Sheet
7
V2.0, 2009-04-01