TI TMS3473

TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
•
•
•
•
•
•
•
TTL-Compatible Inputs
CCD-Compatible Outputs
Variable-Output Slew Rates With External
Resistor Control
Full-Frame Operation
Frame-Transfer Operation
Solid-State Reliability
Adjustable Clock Levels
description
DW PACKAGE
(TOP VIEW)
IALVL
I/N
IAIN
ABIN
MIDSEL
SAIN
PD
GND
VABG+
VSS
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
VSS
IASR
ABSR
VCC
ABLVL
IAOUT
ABOUT
SAOUT
VCC
VABG –
The TMS3473B is a monolithic CMOS integrated
10
11
circuit designed to drive the parallel image-area
gate (IAG), parallel storage-area gate (SAG), and
antiblooming gate (ABG) inputs of the Texas Instruments (TI) virtual-phase CCD image sensors. The
TMS3473B interfaces the CCD image sensor to a user-defined timing generator; it receives TTL-input signals
from the timing generator and outputs level-shifted and slew-rate-adjusted signals to the image sensor.
The TMS3473B allows operation of the CCD image sensor in either the interlace or noninterlace mode. When
the TMS3473B I/N input is connected to VSS, the interlace mode is selected (see Figure 1); when I/N is
connected to VCC, the noninterlace mode is selected (see Figure 2).
ABOUT follows ABIN and switches between VABG+ and VABG–. IAOUT and SAOUT follow IAIN and SAIN,
respectively, and switch between VCC and VSS. Additionally, ABOUT and IAOUT can each be made to output
midlevel voltages. DC inputs to ABLVL and IALVL determine the midlevel voltages that can be output on ABOUT
and IAOUT, respectively. A high-logic level on MIDSEL causes ABOUT to output its midlevel voltage; a low-logic
level on MIDSEL causes IAOUT to output its midlevel voltage if the interlace mode is selected.
Slew-rate adjustment of IAOUT and ABOUT is accomplished by connecting IASR to VCC and ABSR to VABG+
through external resistors. The larger the resistor values, the longer the rise and fall times are.
A low-logic level on PD causes the TMS3473B to power down and all outputs to assume their low levels (IAOUT
and SAOUT to VSS, ABOUT to VABG –).
The TMS3473B is supplied in a 20-pin surface-mount package (DW) and is characterized for operation from
–20°C to 45°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these
high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in
conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground.
Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices and Assemblies available from Texas Instruments.
TI is a trademark of Texas Instruments Incorporated.
Copyright  1990, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
logic symbol
Φ
TTL/CCD
TMS3473B
I/N
PD
MIDSEL
ABIN
ABLVL
ABSR
IAIN
IALVL
IASR
SAIN
2
2
7
5
NONINT
INT/M1
PWR DWN
ABOUT to midlevel
1(IAOUT to midlevel)
4
16
14
18
ABOUT
3
1
15
19
6
13
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IAOUT
SAOUT
TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
ABIN
4
I
Antiblooming in
ABLVL
16
I
DC antiblooming midlevel voltage
ABOUT
14
O
Antiblooming out
ABSR
18
I
Antiblooming slew rate
GND
8
IAIN
3
I
Parallel-image-area in
IALVL
1
I
DC parallel-image-area midlevel voltage
IAOUT
15
O
Parallel-image-area out
IASR
19
I
Parallel-image-area slew rate
I/N
2
I
Interlace/noninterlace select
MIDSEL
5
I
IAOUT/ABOUT midlevel voltage select
PD
7
I
Power down
SAIN
6
I
Parallel storage area in
SAOUT
13
O
Parallel storage area out
VABG+
VABG –
VCC†
9
I
Positive ABG supply voltage
11
I
Negative ABG supply voltage
12
I
Positive supply voltage
17
I
Positive supply voltage
10
I
Negative supply voltage
VCC†
VSS†
Ground
VSS†
20
I
Negative supply voltage
† All terminals of the same name should be connected together externally.
Integrate
Readout
or
Transfer to
Memory‡
I/N
Integrate
–9 V
I/N
Readout
or
Transfer to
Memory‡
5V
IAIN
0V
5V
IAIN
5V
ABIN
0V
0V
IAOUT
IAOUT
ABOUT
3V
– 2.5 V
–8 V
ABOUT
TV Field B
0V
5V
MIDSEL
1.5 V
–3 V
–9 V
TV Field A
0V
5V
ABIN
5V
MIDSEL
2V
0V
1.5 V
–9 V
3V
– 2.5 V
–8 V
Figure 2. Parallel-Driver Timing Diagram
(noninterlace mode)
Figure 1. Parallel-Driver Timing Diagram
(interlace mode)
‡ A readout occurs if the TMS3473B is driving a full-frame CCD image sensor; a transfer to memory occurs if the TMS3473B is driving a
frame-transfer CCD image sensor.
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TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Positive supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 V
Negative supply voltage, VSS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –11.1 V
Positive ABG supply voltage, VABG+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 V
Negative ABG supply voltage, VABG – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 8 V
ABG supply voltage differential (VABG+ – VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 V
Continuous total power dissipation at (or below), TA ≤ 25°C:
Unmounted device (see Figure 3) . . . . . . . . . . . . . . 825 mW
Mounted device (see Figure 3) . . . . . . . . . . . . . . . . 1150 mW
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 45°C
Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
voltage levels only.
POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1500
1400
Mounted Device
(see Note A)
PD – Power Dissipation – mW
1300
1200
1100
1000
900
800
700
600
500
400
300
Unmounted Device
200
100
0
0
10
20
30
40
50
60
70
TA – Free-Air Temperature – °C
Figure 3
NOTE A: The mounted-device derating curve in Figure 3 is obtained under the following conditions:
The board is 50 mm by 50 mm by 1.6 mm thick.
The board material is glass epoxy.
The copper thickness of all the etch runs is 35 microns.
Etch run dimensions – DW package – All 20 etch runs are 0.4 mm by 22 mm.
Each chip is soldered to the board.
An aluminum cooling fin 10 mm by 10 mm by 1 mm thick is coupled to the chip with thermal paste.
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TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
recommended operating conditions (see Note 2)
MIN
Positive supply voltage, VCC†
Negative supply voltage, VSS†
Positive ABG supply voltage, VABG+†
Negative ABG supply voltage, VABG –†
NOM
MAX
0
1
4.4
V
–11.1
– 10
– 9.7
V
1
3.5
4.4
V
– 11.1
–7
– 6.2
V
15.5
V
Power supply voltage differential (VCC – VSS)
DC parallel image area midlevel voltage, IALVL‡
Z < 5 kΩ
DC antiblooming midlevel voltage, ABLVL
Z < 2.5 kΩ
High level input voltage,
High-level
voltage VIH
Low level input voltage,
Low-level
voltage VIL
Input voltage
voltage, VI
ABIN, MIDSEL, PD, IAIN, or SAIN
I/N
–5
–2
V
– 3.5
– 2.5
1
V
2.5
5
ABIN, MIDSEL, PD, IAIN, or SAIN
0
I/N
– 3.5
IALVL
Frequency fclock
Frequency,
l k
IAIN, SAIN§
ABIN§
Input resistance, Ri
IALVL, ABLVL
–6
V
0.9
VSS + 0.4
1
–2
3.58
2
2.5
Slope-resistance bias
Input capacitance, Ci
–6
VCC – 0.4
ABLVL
10
ABLVL
– 20
V
V
MHz
kΩ
50
kΩ
µF
1
Operating free-air temperature, TA
UNIT
45
°C
† VCC, VSS, VABG+, and VABG – have 100-mA current limits. Adequate decoupling capacitors are required from these terminals to ground.
‡ Proper adjustment is required for interlace-mode operation.
§ Different CCD image sensors have different maximum clock rates. See the individual CCD image sensor data sheets for these rates.
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5
TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 2)
TEST CONDITIONS†
PARAMETER
VOH
High-level
g
output
voltage
ABOUT
VOL
Low-level output
voltage
ABOUT
IIH†
High-level
g
input
current
ABIN, IAIN, SAIN, MIDSEL, PD
IIL†
Low-level input
current
ABIN, IAIN, SAIN, MIDSEL, PD
IAB
Antiblooming current
ISS
IAOUT, SAOUT
IAOUT, SAOUT
I/N
I/N
Supply current
MIN
MAX
IOH = 180 mA (peak)
IOH = 730 mA (peak)
VABG+ – 0.2
VCC – 0.5
VABG+ + 0.2
VCC + 0.5
V
IOL = 180 mA (peak)
IOL = 730 mA (peak)
VABG – – 0.3
VSS – 0.6
VABG – + 0.3
VSS + 0.8
V
0
– 50
VIH = 5 V
VIH = VCC = 2 V
± 10
± 10
VIL = 0 V
VIL = VSS = –10 V
± 10
Average load, See Note 3
20
No load,
1.5
PD = 0 V
Average load, See Note 4
25
UNIT
µA
µA
mA
mA
† These parameters are measured with VSS = –10.3 V, VCC = 2.1 V, VABG+ = 4.3 V, VABG – = –7 V, and with IASR connected to VCC and ABSR
connected to VABG+, both through 22-kΩ resistors.
NOTES: 2. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
voltage levels only.
3. The load consists of a TC241 CCD image sensor with ABG clocked at 2 MHz using ABG mode 3 (see the TMS3471C data sheet
for details on mode 3).
4. The load consists of a TC241 CCD image sensor with IAG and SAG clocked at 2.1 MHz.
switching characteristics
PARAMETER
tr
Rise time
tf
Fall time
MIN
MAX
ABOUT
60
140
IAOUT, SAOUT
40
180
45
100
30
110
ABOUT
TEST CONDITIONS
VCC = 2.1 V,,
TA = 25°C,
VABG+ = 4.3 V,,
VSS = –10.3 V,
IAOUT, SAOUT
VABG – = –7 V,,
See Note 5
UNIT
ns
ns
NOTE 5: IASR is connected to VCC and ABSR is connected to VABG+, both through 22-kΩ resistors. The load consists of a TC241 CCD image
sensor with ABG clocked at 2 MHz using ABG mode 3 (see the TMS3471C data sheet for details on mode 3).
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TMS3473B
PARALLEL DRIVER
SOCS022B – NOVEMBER 1990
MECHANICAL DATA
DW/R-PDSO-G**
PLASTIC WIDE-BODY SMALL-OUTLINE PACKAGE
20 PIN SHOWN
A
20
11
PINS**
16
20
24
28
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
DIM
0.419 (10,65)
0.400 (10,15)
0.299 (7,59)
0.293 (7,45)
10
1
0.104 (2,65)
0.093 (2,35)
0.012 (0,30)
0.004 (0,10)
0.364 (9,24)
0.338 (8,58)
Seating Plane
0.004 (0,10)
0.020 (0,51)
0.014 (0,35)
0°– 8°
0.012 (0,30)
0.009 (0,23)
0.050 (1,27)
0.016 (0,40)
0.010 (0,25) M
0.050 (1,27)
4040000/A–10/93
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
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SOCS022B – NOVEMBER 1990
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