Philips Semiconductors Product specification TrenchMOS transistor Standard level FET GENERAL DESCRIPTION N-channel enhancement mode standard level field-effect power transistor in a plastic envelope suitable for surface mounting. Using ’trench’ technology the device features very low on-state resistance. It is intended for use in automotive and general purpose switching applications. PINNING - SOT404 PIN BUK7640-100A QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 10 V PIN CONFIGURATION MAX. UNIT 100 37 138 175 40 V A W ˚C mΩ SYMBOL DESCRIPTION d mb 1 gate 2 drain (no connection possible) 3 mb g 2 source 1 drain s 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 100 100 20 37 26 149 138 175 V V V A A A W ˚C TYP. MAX. UNIT - 1.1 K/W 50 - K/W THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient - Rth j-a December 1999 Minimum footprint, FR4 board 1 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET BUK7640-100A STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage VGS = 0 V; ID = 0.25 mA; VGS(TO) Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C IDSS Zero gate voltage drain current VDS = 100 V; VGS = 0 V; IGSS RDS(ON) Gate source leakage current Drain-source on-state resistance VGS = ±20 V; VDS = 0 V VGS = 10 V; ID = 25 A Tj = 175˚C Tj = 175˚C MIN. TYP. MAX. UNIT 100 89 2 1 - 3 0.05 2 30 - 4 4.4 10 500 100 40 108 V V V V V µA µA nA mΩ mΩ MIN. TYP. MAX. UNIT DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1720 216 133 2293 259 182 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; Rload =1.2Ω; VGS = 10 V; RG = 10 Ω - 12 55 48 30 18 83 67 42 ns ns ns ns Ld Internal drain inductance - 2.5 - nH Ls Internal source inductance Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT - - 37 A IF = 25 A; VGS = 0 V IF = 37 A; VGS = 0 V - 0.85 1.1 149 1.2 - A V V IF = 37 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 70 0.24 - ns µC REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IDR IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge December 1999 CONDITIONS 2 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET BUK7640-100A AVALANCHE LIMITING VALUE SYMBOL 1 DSS W 120 PARAMETER CONDITIONS Drain-source non-repetitive unclamped inductive turn-off energy ID = 26 A; VDD ≤ 25 V; VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C Normalised Power Derating PD% MIN. TYP. MAX. UNIT - - 31 mJ 1000 ID/A 110 100 90 RDS(ON)=VDS/ID tp = 1us 100 80 70 10us 60 50 100us 40 10 30 1ms 20 DC 10ms 10 100ms 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 1 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 VDS/V 1000 100 Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% 10 1 10 Zth/(K/W) 110 100 1 90 0.5 80 0.2 70 0.1 60 0.1 0.05 50 0.02 40 0.01 0 30 20 10 0.001 1E-07 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 1E-05 1E-03 1E-01 1E+01 t/s Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); VGS ≥ 10 V Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 1 For maximum permissible repetive avalanche current see fig.18. December 1999 3 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET BUK7640-100A Drain Current, ID (A) 50 Drain current, ID (A) VGS = 10V Tj = 25 C 45 40 8V 35 30 30 25 25 5.4 V 20 20 5.2 V 15 15 5V 10 10 4.8 V 5 4.4 V 0 4.6 V 5 VDS > ID X RDS(ON) 35 6V 40 0 Tj = 25 C 175 C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 1 5V 5.2 V 4 5 6 7 8 9 10 Fig.8. Typical transfer characteristics. ID = f(VGS) 70 Drain-Source On Resistance, RDS(on) (Ohms) 0.09 3 Gate-source voltage, VGS (V) Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) 0.1 2 2 gfs/S 5.4 V Tj = 25 C 60 4.8 V 0.08 50 0.07 40 0.06 6V 0.05 0.04 8V 0.03 VGS = 10V 30 20 0.02 10 0.01 0 0 0 5 10 15 20 25 30 Drain Current, ID (A) 35 40 45 50 0 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) ID/A 20 30 40 Fig.9. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 3 38 RDS(ON) Ohm 10 36 Rds(on) normalised to 25degC a 2.5 34 2 32 1.5 30 28 1 26 1 2 3 VGS/V 4 0.5 5 Fig.7. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(VGS); conditions: ID = 25 A; December 1999 -100 -50 0 50 100 Tmb / degC 150 200 Fig.10. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) 4 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET 5 BUK7640-100A VGS(TO) / V BUK759-60 10 VGS / V 9 max. 8 4 VDS = 14V 7 typ. VDS = 44V 6 3 5 min. 4 2 3 2 1 1 0 -100 0 -50 0 50 Tj / C 100 150 0 200 10 20 QG / nC 30 40 Fig.14. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.11. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Sub-Threshold Conduction 1E-01 Source-Drain Diode Current, IF (A) 50 VGS = 0 V 45 1E-02 40 35 2% 1E-03 typ 98% 30 175 C 25 Tj = 25 C 20 1E-04 15 10 1E-05 5 0 1E-06 0 0 1 2 3 4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 5 1 1.1 1.2 1.3 1.4 1.5 Source-Drain Voltage, VSDS (V) Fig.12. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.15. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 120 WDSS% 110 3.5 Capacitance / pF 100 3.0 90 2.5 80 70 2.0 60 1.5 50 Ciss 40 1.0 30 0.5 0.0 0.01 20 Coss Crss 0.1 1 VDS/V 10 10 0 100 20 Fig.13. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz December 1999 40 60 80 100 120 Tmb / C 140 160 180 Fig.16. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A 5 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET BUK7640-100A VDD + + VDD RD L VDS VDS - VGS - VGS -ID/100 T.U.T. 0 0 RG T.U.T. R 01 shunt RGS Fig.17. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.19. Switching test circuit. 100 25ºC IAV 10 Tj prior to avalanche 150ºC 1 0.001 0.01 0.1 1 10 Avalanche Time, tAV (ms) Fig.18. Maximum permissible repetitive avalanche current(IAV) versus avalanche time(tAV) for unclamped inductive loads. December 1999 6 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET BUK7640-100A MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.40 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 SOT404 Fig.20. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". December 1999 7 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET BUK7640-100A MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.21. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1999 8 Rev 1.000