PHILIPS TDA8784HL

INTEGRATED CIRCUITS
DATA SHEET
TDA8784
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
Product specification
Supersedes data of 1998 Aug 05
File under Integrated Circuits, IC02
1999 Sep 21
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
FEATURES
APPLICATIONS
• Correlated Double Sampling (CDS), AGC, 10-bit ADC
and reference regulator included, adjustable bandwidth
(CDS and AGC)
• CCD camera systems.
GENERAL DESCRIPTION
• Fully programmable via a 3-wire serial interface
The TDA8784 is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, AGC and a low-power 10-bit
Analog-to-Digital Converter (ADC) together with its
reference voltage regulator.
• Sampling frequency up to 18 MHz
• AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps)
• CDS programmable bandwidth from 4 to 120 MHz
• AGC programmable bandwidth from 4 to 54 MHz
• Standby mode available for each block for power saving
applications (20 mW typical)
The AGC and CDS have a bandwidth circuit controlled by
on-chip DACs via a serial interface.
• 6 dB fixed gain analog output for analog iris control
A 10-bit DAC controls the ADC input clamp level.
• 8-bit and 10-bit DAC included for analog settings
An additional 8-bit DAC is provided for additional system
controls; its output voltage range is 1.4 V (p-p) which is
available at pin OFDOUT.
• Low power consumption of only 483 mW typical
• 5 V operation and 2.5 to 5.25 V operation for the digital
outputs
• TTL compatible inputs, TTL and CMOS compatible
outputs.
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
TDA8784HL
LQFP48
1999 Sep 21
DESCRIPTION
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
2
VERSION
SOT313-2
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
4.75
5
5.25
V
VCCD
digital supply voltage
4.75
5
5.25
V
VCCO
digital outputs supply voltage
2.5
3
5.25
V
ICCA
analog supply current
−
78
85
mA
ICCD
digital supply current
−
18
20
mA
ICCO
digital outputs supply current
−
1
−
mA
fCLK = 18 MHz;
CL = 20 pF; ramp input
ADCres
ADC resolution
−
10
−
bits
Vi(CDS)(p-p)
CDS input voltage (peak-to-peak value)
−
400
1200
mV
GCDS
CDS output amplifier gain
−
6
−
dB
fCLK(max)
maximum clock frequency
18
−
−
MHz
AGCdyn
AGC dynamic range
−
30
−
dB
Ntot(rms)
total output noise from CDS input to
ADC output (RMS value)
gain = 4.5 dB;
fcut(CDS) = 120 MHz;
fcut(AGC) = 40 MHz
−
0.125
−
LSB
Ein(rms)
equivalent input noise (RMS value)
gain = 34.5 dB
−
125
−
µV
Ptot
total power consumption
−
483
550
mW
1999 Sep 21
fcut(CDS) = 120 MHz;
fcut(AGC) = 54 MHz
3
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
BLOCK DIAGRAM
handbook, full pagewidth IND
47
INP AGND3 VCCA3 SHD
46
48
45
SHP
44
CLPOB CLPDM
43
CLK
42
1
DGND2
VCCD2
40
39
41
OE
38
VCCO
37
36
TRACKAND-HOLD
CLOCK
GENERATOR
TRACKAND-HOLD
35
TRACKAND-HOLD
CPCDS
AGND1
34
8
CLAMP
5
33
4-BIT DAC
CUT-OFF
CLAMP
ref1
32
31
AMPOUT
AGND4
AGCOUT
4
OUTPUTS
BUFFER
10-BIT ADC
6 dB
2
30
TDA8784
7
1
29
AGC
28
VCCA1
AGND5
ADCIN
6
1
4-BIT DAC
CUT-OFF
27
9-BIT DAC
9
10
Vref
12
CLPADC
11
26
25
8-BIT DAC
10-BIT DAC
DACOUT
14
15
16
VCCA2
AGND2
17
18
VRB
19
23
AGND6
VRT
DEC1
STDBY
Fig.1 Block diagram.
1999 Sep 21
4
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DGND1
OFDOUT
SERIAL
INTERFACE
REGULATOR
13
3
OGND
22
SEN
21
20
24
SDATA
VCCD1
SCLK
MGM505
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
PINNING
SYMBOL
PIN
DESCRIPTION
CLPOB
1
clamp pulse input at optical black
AGND4
2
analog ground 4
OFDOUT
3
analog output of the additional 8-bit control DAC (controlled via the serial interface)
AMPOUT
4
CDS amplifier output (fixed gain = 6 dB)
AGND1
5
analog ground 1
VCCA1
6
analog supply voltage 1
AGCOUT
7
AGC amplifier signal output
CPCDS
8
clamp storage capacitor pin
AGND5
9
analog ground 5
ADCIN
10
ADC analog signal input from AGCOUT via a short circuit
CLPADC
11
clamp control input for ADC analog input signal clamp (used with a capacitor from Vref to ground)
Vref
12
ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or shorted to
ground via a capacitor)
DACOUT
13
DAC output for ADC clamp level
AGND2
14
analog ground 2
VCCA2
15
analog supply voltage 2
VRB
16
ADC reference voltage (BOTTOM) code 0
VRT
17
ADC reference voltage (TOP) code 1023
DEC1
18
decoupling 1 (decoupled to ground via a capacitor)
AGND6
19
analog ground 6
SDATA
20
serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off;
additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby mode
per block and edge pulse control); see Table 1
SCLK
21
serial clock input for the control DACs and their serial interface; see Table 1
SEN
22
enable input for the serial interface shift register (active when SEN = logic 0); see Table 1
STDBY
23
standby control pin (active HIGH); all the output bits are logic 0 when standby is enabled
VCCD1
24
digital supply voltage 1
DGND1
25
digital ground 1
D0
26
ADC digital output 0 (LSB)
D1
27
ADC digital output 1
D2
28
ADC digital output 2
D3
29
ADC digital output 3
D4
30
ADC digital output 4
D5
31
ADC digital output 5
D6
32
ADC digital output 6
D7
33
ADC digital output 7
D8
34
ADC digital output 8
D9
35
ADC digital output 9 (MSB)
OGND
36
digital output ground
VCCO
37
digital output supply voltage
1999 Sep 21
5
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
ADC clock input
CLPDM
42
clamp pulse input at dummy pixel
SHP
43
pre-set sample-and-hold pulse input
SHD
44
data sample-and-hold pulse input
VCCA3
45
analog supply voltage 3
INP
46
pre-set input signal from CCD
IND
47
data input signal from CCD
AGND3
48
analog ground 3
43 SHP
41
44 SHD
CLK
45 VCCA3
digital ground 2
46 INP
digital supply voltage 2
47 IND
39
40
48 AGND3
VCCD2
DGND2
37 VCCO
output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance)
38 OE
38
39 VCCD2
OE
40 DGND2
DESCRIPTION
41 CLK
PIN
42 CLPDM
SYMBOL
CLPOB
1
36 OGND
AGND4
2
35 D9
OFDOUT
3
34 D8
AMPOUT
4
33 D7
AGND1
5
32 D6
VCCA1
6
AGCOUT
7
30 D4
CPCDS
8
29 D3
AGND5
9
28 D2
ADCIN 10
27 D1
31 D5
TDA8784H
26 D0
CLPADC 11
Vref 12
1999 Sep 21
6
VCCD1 24
SEN 22
Fig.2 Pin configuration.
STDBY 23
SCLK 21
SDATA 20
AGND6 19
VRT 17
DEC1 18
VRB 16
VCCA2 15
AGND2 14
DACOUT 13
25 DGND1
MGM506
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCCA
analog supply voltage
note 1
−0.3
+7.0
V
VCCD
digital supply voltage
note 1
−0.3
+7.0
V
VCCO
output stages supply voltage
note 1
−0.3
+7.0
V
∆VCC
supply voltage difference
between VCCA and VCCD
−1.0
+1.0
V
between VCCA and VCCO
−1.0
+4.0
V
−1.0
+4.0
V
Vi
input voltage
referenced to AGND
−0.3
+7.0
V
VCLK(p-p)
AC input voltage for switching
(peak-to-peak value)
referenced to DGND
−
VCCD
V
Io
output current
−
10
mA
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
−20
+75
°C
Tj
junction temperature
−
150
°C
between VCCD and VCCO
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply
voltage difference ∆VCC remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1999 Sep 21
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
in free air
7
VALUE
UNIT
76
K/W
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
CHARACTERISTICS
VCCA = VCCD = 5 V; VCCO = 3 V; fCLK = 18 MHz; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
analog supply voltage
4.75
VCCD
digital supply voltage
4.75
VCCO
digital outputs supply voltage
2.5
ICCA
analog supply current
−
ICCD
digital supply current
ICCO
digital outputs supply current
CL = 20 pF on all data outputs;
ramp input
5
5.25
V
5
5.25
V
3
5.25
V
78
85
mA
−
18
20
mA
−
1
−
mA
Digital inputs
CLOCK INPUT: CLK (REFERENCED TO DGND)
VIL
LOW-level input voltage
0
−
0.8
V
VIH
HIGH-level input voltage
2.0
−
VCCD
V
IIL
LOW-level input current
VCLK = 0.8 V
−1
−
+1
µA
IIH
HIGH-level input current
VCLK = 2.0 V
−
−
20
µA
Zi
input impedance
fCLK = 18 MHz
−
46
−
kΩ
Ci
input capacitance
fCLK = 18 MHz
−
1
−
pF
INPUTS: SHP AND SHD
VIL
LOW-level input voltage
0
−
0.8
V
VIH
HIGH-level input voltage
2.0
−
VCCD
V
IIL
LOW-level input current
VIL = 0.6 V
−
−6
−
µA
IIH
HIGH-level input current
VIH = 2.2 V
−
0
−
µA
0
−
0.8
V
INPUTS: SEN, SCLK, SDATA, OE, STDBY, CLPDM, CLPOB AND CLPADC
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
2.0
−
VCCD
V
Ii
input current
−2
−
+2
µA
−
400
1200
mV
−2
−
+2
µA
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
CDS input amplitude
(peak-to-peak value)
ICPCDS,INP,IND input current pins 8, 46
and 47
tCDS(min)
CDS control pulses minimum
active time
fi(CDS1,2) = fCLK(pix);
Vi(CDS) = 1200 mV (p-p)
black-to-white transition in
1 pixel (±1 LSB typ.);
fcut(CDS) = 40 MHz;
fcut(AGC) = 40 MHz
12
−
−
ns
thd1
hold time INP compared to
control pulse SHP
see Fig.5
−
1
−
ns
1999 Sep 21
8
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
SYMBOL
PARAMETER
TDA8784
CONDITIONS
MIN.
TYP.
MAX.
UNIT
−
1
−
ns
0000
−
12
−
ns
0001
−
25
−
ns
0010
−
45
−
ns
0011
−
55
−
ns
0100
−
105
−
ns
0111
−
140
−
ns
1000
−
270
−
ns
1011
−
300
−
ns
1111
−
365
−
ns
thd2
hold time of IND compared to
control pulse SHD
see Fig.5
tset(CDS)
CDS settling time
see Fig.12; control DAC 4 bits
input code; AGC gain = 0 dB;
fcut(AGC) = 54 MHz;
Vi(CDS) = 1200 mV (p-p)
black-to-white transition in 1
pixel (1 LSB typ.)
Amplifier outputs
GAMPOUT
output amplifier gain
−
6
−
dB
ZAMPOUT
output amplifier impedance
−
300
−
Ω
VAMPOUT(p-p)
output amplifier dynamic
voltage (peak-to-peak value)
−
2.4
−
V
VAMPOUT(bl)
output amplifier black level
voltage
−
1.5
−
V
VAGCOUT(p-p)
AGC output amplifier dynamic
voltage level (peak-to-peak
value)
−
2000
−
mV
VAGCOUT
AGC output amplifier
black level voltage
Vref connected to DACOUT
−
Vref
−
V
ZAGCOUT
AGC output amplifier output
impedance
at 10 kHz
−
5
−
Ω
IAGCOUT
AGC output static drive
current
static
−
−
1
mA
GAGC(min)
minimum gain of AGC circuit
AGC DAC input code = 00
(9-bit control)
−
4.5
−
dB
GAGC(max)
maximum gain of AGC circuit
AGC DAC input code ≥319
(9-bit control)
−
34.5
−
dB
fcut(AGC)
cut-off frequency AGC
control DAC 4-bit
input code = 00
−
54
−
MHz
input code = 01
−
40
−
MHz
input code = 15
−
4
−
MHz
1999 Sep 21
9
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
SYMBOL
PARAMETER
TDA8784
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clamps
gm(ADC)
ADC clamp transconductance at clamp level
−
7
−
mS
gm(CDS)
CDS clamp transconductance at clamp level
−
1.5
−
mS
Analog-to-Digital Converter (ADC)
fCLK(max)
maximum clock frequency
18
−
−
MHz
tCPH
clock pulse width HIGH
15
−
−
ns
tCPL
clock pulse width LOW
SRCLK
clock input slew rate (rising
and falling edge)
Vi(ADC)(p-p)
15
−
−
ns
0.5
−
−
V/ns
ADC input voltage level
(peak-to-peak value)
−
2
−
V
VRB
ADC reference voltage output
code 0
−
1.5
−
V
VRT
ADC reference voltage output
code 1023
−
3.5
−
V
IADCIN
input current pin 10
−2
−
+120
µA
10% to 90%
INL
integral non-linearity
ramp input
−
±0.6
±1.5
LSB
DNL
differential non-linearity
ramp input
−
±0.2
±0.75
LSB
td(s)
sampling delay time
−
−
5
ns
−
40
−
ns
GAGC = 4.5 dB
−
0.125
−
LSB
GAGC = 34.5 dB
−
1.6
−
LSB
Total chain characteristics (CDS + AGC + ADC)
td
time delay between
SHD and CLK
see Fig.5; 50% at rising
edges CLK and SHP: transition
full scale code 0 to 1023;
fcut(CDS) = 40 MHz;
fcut(AGC) = 40 MHz;
Vi(CDS) = 1200 mV
Ntot(rms)
total output noise (RMS
value)
fcut(CDS) = 120 MHz;
fcut(AGC) = 40 MHz; note 1
Voffset(fl-d)
maximum offset between
CCD floating level and CCD
dark pixel level
−200
−
+200
mV
Vn(i)(eq)(rms)
equivalent input noise voltage AGC gain = 34.5 dB
(RMS value)
AGC gain = 4.5 dB
−
125
−
µV
−
150
−
µV
Digital-to-analog converter (OFDOUT)
VOFDOUT(p-p)
additional 8-bit control DAC
(OFD) output voltage
(peak-to-peak value)
−
1.4
−
V
VOFDOUT(0)
DC output voltage for code 0
−
2.3
−
V
VOFDOUT(255)
DC output voltage for
code 255
−
3.7
−
V
1999 Sep 21
10
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
SYMBOL
PARAMETER
ZOFDOUT
additional 8-bit control DAC
(OFD) output impedance
IOFDOUT
OFD output current drive
TDA8784
CONDITIONS
MIN.
TYP.
MAX.
UNIT
−
2000
−
Ω
−
−
50
µA
−
1
−
V
code 0
−
1.5
−
V
code 1023
−
2.5
−
V
−
−
250
Ω
static
ADC clamp control DAC (see Fig.8)
VDACOUT(p-p)
ADC clamp 10-bit control
DAC output voltage
(peak-to-peak value)
VDACOUT
DC output voltage
ZDACOUT
ADC clamp control DAC
output impedance
IDACOUT
DAC output current drive
static
−
−
50
µA
OFELOOP
maximum offset error of
DAC + ADC clamp loop
code 0
−
±5
−
LSB
code 1023
−
±5
−
LSB
Digital outputs (fCLK = 18 MHz; CL = 20 pF)
VOH
HIGH-level output voltage
IOH = −1 mA
VCCO − 0.5
−
VCCO
V
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.5
V
IOZ
output current in 3-state mode 0 V < Vo < VCCO
−20
−
+20
µA
to(h)
output hold time
see Fig.5
8
−
−
ns
to(d)
output delay time
Ci = 20 pF; VCCO = 5 V
−
17
23
ns
Ci = 10 pF
−
15
21
ns
Ci = 20 pF; VCCO = 3 V
−
20
29
ns
Ci = 10 pF
−
17
25
ns
Ci = 20 pF; VCCO = 2.5 V
−
22
33
ns
Ci = 10 pF
−
18
28
ns
5
−
−
MHz
Serial interface
fSCLK(max)
maximum frequency of serial
interface
Note
1. Noise measurement at ADC outputs: the coupling capacitor at the input is connected to ground, so that only the noise
contribution of the front-end is evaluated. The front-end operates at 18 Mpix with a line of 1024 pixels. The first 40 are
used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels.
The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise
is taken into account as no signal is input.
1999 Sep 21
11
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
handbook, full pagewidth
TDA8784
SDATA
SHIFT REGISTER
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A0
A1
A2
SCLK
LSB
MSB
10
LATCH
SELECTION
SEN
8
(D7 to D0)
8
(D7 to D0)
8
(D7 to D0)
7
(D6 to D0)
10
(D9 to D0)
OFD
LATCHES
AGC GAIN
LATCHES
FREQUENCY
LATCHES
PARTIAL
STANDBY
AND EDGE
CLAMP
REFERENCE
LATCHES
8-bit DAC
AGC control
frequency
control
CDS and AGC
standby
control
or edge clocks
10-bit DAC
MGM515
Fig.3 Serial interface block diagram.
tsu2
handbook, full pagewidth
thd4
MSB
SDATA
A2
A1
A0
D9
D8
D7
LSB
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
MGE373
tsu1
thd3
tsu3
tsu1 = tsu2 = 4 ns (min.); thd3 = thd4 = 4 ns (min.).
Fig.4 Loading sequence of control DACs input data via the serial interface.
1999 Sep 21
12
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
Table 1
TDA8784
Serial interface programming
ADDRESS BITS
DATA BITS D9 to D0
A2
A1
A0
0
0
0
OFD output control (D7 to D0).
0
0
1
Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for
CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0.
0
1
0
AGC gain control (D8 to D0).
0
1
1
Partial standby controls for power consumption optimization. Only the 4 LSBs
(D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and
clock ADC:
D0 = 1: CDS + AGC in standby; ICCA + ICCD = 48 mA
D1 = 1: OFD DAC in standby; ICCA + ICCD = 98 mA
D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby;
ICCA + ICCD = 98.5 mA
D3 = 1: SHP and SHD activated with falling edge (for positive pulse)
D4 = 1: CLPDM, CLPOB and CLPADC activated on HIGH level; note 1
D5 = 0: CLKADC activated with falling edge
D6 must be set to logic 0.
1
0
0
Clamp reference DAC (D9 to D0).
Note
1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level Vref.
Vref is connected to ground via a capacitance.
Table 2 Standby selection
STDBY
1999 Sep 21
DATA BITS D9 to D0
ICCA + ICCD (TYP.)
1
LOW
4 mA
0
active
99 mA
13
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
handbook, full pagewidth
INP
and
IND
SHP
TDA8784
N+1
N
N+2
N+3
tCDS
1.4 V
thd1
SHD
1.4 V
td
thd2
tCPH
CLK
td(s)
1.4 V
to(d)
N
ADC
to(h)
90%
N−1
DATA
10%
Fig.5 Pixel frequency timing diagram.
1999 Sep 21
14
N
MGR395
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
1 pixel
handbook, full pagewidth
AGCOUT
VIDEO
OPTICAL BLACK
1 pixel
HORIZONTAL FLYBLACK
CLPDM2
CLPADC
WINDOW
DUMMY
VIDEO
CLPDMR
CLPADC
WINDOW
CLPOB
(active HIGH)
CLPDB
WINDOW
CLPDM
(active HIGH)
(1)
CLPADC
(active HIGH)
(1)
MGR396
(1) When dummy pixels are not available.
Fig.6 Line frequency timing diagram.
1999 Sep 21
15
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
MGM507
handbook, halfpage
34.5
GAGC
(dB)
4.5
0
511
319
AGC control DAC input code
Fig.7 AGC gain as a function of DAC input code.
MGM508
handbook, full pagewidth
2.5
3.4
ADC CLAMP DAC
voltage
output
(V)
OFD DAC
voltage
output
(V)
2.0
1.5
0
1023
ADC CLAMP control DAC input code
0
255
OFD control DAC input code
Fig.8 DAC voltage output as a function of DAC input code.
1999 Sep 21
16
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
handbook,I halfpage
(µA)
+100
0
2.85
V (V)
−100
200 mV
MGR397
Fig.9 Typical clamp current for pin CPCDS.
handbook,I halfpage
(µA)
+300
0
2.85
V (V)
−300
400 mV
MGR398
Fig.10 Typical clamp current for pins IND and INP.
handbook,I halfpage
(µA)
+200
0
Vref
V (V)
−200
400 mV
MGR399
Fig.11 Typical clamp current for pin Vref.
1999 Sep 21
17
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
MGR400
160
handbook, full pagewidth
400
fcut
(MHz)
tset
(ns)
120
(3)
300
(2)
(4)
80
200
(1)
40
0
(1)
(2)
(3)
(4)
100
0
1
2
3
4
5
6
7
8
9
A
fcut.
tset (10b).
tset (9b).
tset (8b).
Fig.12 CDS settling time and bandwidth.
1999 Sep 21
18
B
C
D
E
4-bit control DAC input code
F
0
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
MGR401
60
handbook, full pagewidth
fcut
(MHz)
40
20
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
4-bit control DAC input code
F
Fig.13 AGC bandwidth.
MGR402
1.6
handbook, full pagewidth
Vo(CDS)(p-p)
(V)
1.2
0.8
0.4
0
0
0.2
0.4
0.6
0.8
tset(CDS) = 12 ns.
Fig.14 CDS output.
1999 Sep 21
19
1.0
1.2
1.4
Vi(CDS)(p-p) (V)
1.6
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
MGR403
3
handbook, full pagewidth
Ntot(rms)
(LSB)
2
(1)
(2)
(3)
1
(4)
(5)
0
00
40
80
C0
100
code
13F
(4.5)
(10.5)
(16.5)
(22.5)
(28.5)
GAGC (dB)
(34.5)
(1)
(2)
(3)
(4)
fpix = 18 MHz; control DAC = 10H; fcut(CDS) = 120 MHz; fcut(AGC) = 40 MHz.
fpix = 10 MHz; control DAC = 31H; fcut(CDS) = 80 MHz; fcut(AGC) = 30 MHz.
fpix = 5 MHz; control DAC = 43H; fcut(CDS) = 35 MHz; fcut(AGC) = 12 MHz.
fpix = 1 MHz; control DAC = F8H; fcut(CDS) = 6 MHz; fcut(AGC) = 4 MHz.
(5) fpix = 375 kHz; control DAC = FFH; fcut(CDS) = 4 MHz; fcut(AGC) = 4 MHz.
Fig.15 Output noise (RMS value).
1999 Sep 21
20
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
APPLICATION INFORMATION
5.0 V
CCD
5.0 V
(3)
(3)
OE
DGND2
VCCD2
CLK
CLPDM
SHP
SHD
VCCA3
INP
AGND3
(3)
from timing
generator
1 µF
IND
2.5 to 5.25 V
VCCO
handbook, full pagewidth
48 47 46 45 44 43 42 41 40 39 38 37
CLPOB
AGND4
OFDOUT
AMPOUT
AGND1
(3)
5.0 V
1 µF
VCCA1
AGCOUT
CPCDS
AGND5
ADCIN
1 µF
CLPADC
Vref
1
36
2
35
3
34
4
33
5
32
6
31
TDA8784
7
30
8
29
9
28
10
27
11
26
12
25
OGND
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DGND1
STDBY
VCCD1
SEN
SCLK
SDATA
DEC1
AGND6
VRT
VRB
VCCA2
AGND2
DACOUT
13 14 15 16 17 18 19 20 21 22 23 24
(2)
(1)
100
nF
2.2
nF
serial
interface
(3)
5.0 V
5.0 V
(3)
1
nF
1
nF
MGM516
Depending on the application, the following connections must be made:
(1) The clamp level of the signal input at ADCIN can be tuned from code 00 to code 511 in 0.5 LSB steps of ADC via the serial interface
(clamp ADC activated).
(2) Clamp ADC not activated, direct connection from DACOUT to Vref.
(3) All supply pins must be decoupled with 100 nF capacitors as close as possible to the device.
Fig.16 Application diagram.
1999 Sep 21
21
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
• In a two-ground system, in order to minimize the noise
though package and die parasitics, the following
recommendations must be implemented:
Power and grounding recommendations
When designing a printed-circuit board for applications
such as PC cameras, surveillance cameras, camcorders
and digital still cameras, care should be taken to minimize
the noise.
– All the analogue and digital supply pins must be
decoupled to the analogue ground plane. Only the
ground pin associated with the digital outputs must be
connected to the digital ground plane. All the other
ground pins should be connected to the analogue
ground plane. The analogue and digital ground
planes must be connected together at one point as
close as possible to the ground pin associated with
the digital outputs.
For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of
analogue components (such as classical operational
amplifiers) must be respected, particularly with respect to
power and ground connections.
The following additional recommendation is given for the
CDS input pin(s) which is/are internally connected to the
programmable gain amplifier:
– The digital output pins and their associated lines
should be shielded by the digital ground plane which
can be used then as return path for digital signals.
• The connections between CCD interface and CDS input
should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analogue and digital supplies provide the best
solution. If it is not possible to do this on the board then
the analogue supply pins must be decoupled effectively
from the digital supply pins. If the same power supply
and ground are used for all the pins then the decoupling
capacitors must be placed as close as possible to the IC
package.
1999 Sep 21
22
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
94-12-19
97-08-01
SOT313-2
1999 Sep 21
EUROPEAN
PROJECTION
23
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Sep 21
24
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
suitable(2)
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 21
25
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
NOTES
1999 Sep 21
26
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
TDA8784
NOTES
1999 Sep 21
27
Philips Semiconductors – a worldwide company
Argentina: see South America
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Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Tel. +64 9 849 4160, Fax. +64 9 849 7811
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Philippines: Philips Semiconductors Philippines Inc.,
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Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
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Tel. +7 095 755 6918, Fax. +7 095 755 6919
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Uruguay: see South America
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 68
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/25/02/pp28
Date of release: 1999
Sep 21
Document order number:
9397 750 06032