INTEGRATED CIRCUITS DATA SHEET TDA4867J Full bridge current driven vertical deflection booster Preliminary specification 2003 Feb 05 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J FEATURES GENERAL DESCRIPTION • Fully integrated, few external components The TDA4867J is a power booster for use in colour vertical deflection systems for frame frequencies of 50 to 200 Hz. The circuit provides a high CMRR current driven differential input. Due to the bridge configuration of the two output stages DC-coupling of the deflection coil is achieved. In conjunction with the deflection controller family TDA485x and SAA4856 the ICs offer an extremely advanced system solution. • Maximum 2.5 A (p-p) deflection current • No additional components in combination with the deflection controller family TDA485x and SAA4856 • Pre-amplifier with differential high CMRR current mode inputs • Low offsets • High linear sawtooth signal amplification • High efficient DC-coupled vertical output bridge circuit • High deflection frequency up to 200 Hz • Power supply and flyback supply voltage independent adjustable to optimize power consumption and flyback time • Excellent transition behaviour during flyback • Guard circuit for screen protection • Power save mode controlled by input pins (in combination with SAA4856 only) or guard pin. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC supplies; note 1 VP supply voltage VFB flyback supply voltage Iq(VFB) quiescent flyback current 8.2 − 25 V note 2 VP + 6 − 60 V no load; no signal − 2.5 4 mA 0.6 − 2.5 A − ±500 ±600 µA − − 2.5 A 5.5 6.2 − V Vertical circuit Idefl(p-p) deflection current on pins OUTB and OUTA (peak-to-peak value) Ii(dif) differential input current note 3 Flyback generator IFB(p-p) maximum current during flyback on pin VFB (peak-to-peak value) Guard circuit; note 1 VGUARD guard voltage guard on Notes 1. Voltages refer to pin GND. 2. If VFB is between 40 and 60 V a decoupling capacitor CFB = 22 µF (between pin VFB and pin GND) and a resistor RFB = 100 Ω (between pin VFB and flyback supply voltage) are required (see Fig.6). 3. Differential input current Ii(dif) = IINP − IINN. 2003 Feb 05 2 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION TDA4867J DBS9P plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad SOT523-1 BLOCK DIAGRAM guard output or power save mode input handbook, full pagewidth flyback voltage VP GUARD 8 3 GND 5 VFB 7 TDA4867J GUARD CIRCUIT FLYBACK GENERATOR AMPLIFIER A Idefl 6 OUTA INP 1 vertical deflection coil Rp INPUT STAGE 9 FEEDB PROTECTION Rref INN 2 from e.g. TDA485x or SAA4856 AMPLIFIER B 4 OUTB MGU988 Fig.1 Block diagram. 2003 Feb 05 3 Rm Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J PINNING SYMBOL PIN In combination with the SAA4856 the power save mode can be achieved via the input pins without additional components. DESCRIPTION INP 1 non-inverted input INN 2 inverted input Output stages VP 3 supply voltage OUTB 4 output B GND 5 ground OUTA 6 output A VFB 7 flyback supply voltage GUARD 8 guard output or power save mode input FEEDB 9 feedback input The two output stages are current driven in opposite phase and operate in combination with the deflection coil in a full bridge configuration. Therefore, the TDA4867J requires no external coupling capacitor and operates with one supply voltage (VP) and a separate adjustable flyback supply voltage (VFB) only. The deflection current through the coil (Idefl) is measured with the resistor Rm which produces a voltage drop: Urm ≈ Rm × Idefl. At pin FEEDB a part of Idefl is fed back to the input stage. The feedback input has a current input characteristic which holds the differential voltage between pin FEEDB and pin OUTB on zero. Therefore the feedback current (IFEEDB) through Rref is: Rm I FEEDB ≈ ---------- × I defl R ref handbook, halfpage INP 1 INN 2 The input stage directly compares the driver currents into pins INP and INN with the half of the feedback current (IFEEDB). Any difference of this comparison leads to a more or less driver current for the output stages. The relation between the deflection current and the differential input current (Ii(dif) = IINP − IINN) is: VP 3 OUTB 4 GND 5 TDA4867J OUTA 6 VFB 7 GUARD 8 Rm I i ( dif ) = 2 × I FEEDB ≈ ---------- × I defl × 2 or: R ref FEEDB 9 MGU989 R ref I defl ≈ I i ( dif ) × ----------------2 × Rm Fig.2 Pin configuration. The deflection current can be adjusted up to ±1.25 A by varying Rref when Rm is fixed to 1 Ω. FUNCTIONAL DESCRIPTION Flyback generator The TDA4867J consists of a differential input stage, two output stages, a flyback generator, a protection circuit for the output stages and a guard circuit. The flyback generator supplies the output stage A during flyback. This makes it possible to optimize power consumption (supply voltage VP) and flyback time (flyback voltage VFB) separately. Due to the absence of a decoupling capacitor the flyback voltage is fully available. Differential input stage The differential input stage has a high CMRR differential current mode input (pin INP and pin INN) that results in a high electromagnetic immunity and is especially suitable for driver units with differential (e.g. TDA485x or SAA4856) and single-ended current signals. In parallel with the deflection yoke and the damping resistor (Rp) an additional capacitor (CSP) and a series resistor (RSP) have to be used. The flyback time can be optimized depending on the value of CSP. The differential input stage delivers the driver signals for the output stages. 2003 Feb 05 4 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J The internal guard circuit will not be activated, if the input signals on pins INP and INN delivered from the driver circuit are out of range or at short-circuit of the coil (pins OUTB and OUTA). Protection The output stages are protected against: • Thermal overshoot in normal operation • Short-circuit of the coil (pins OUTB and OUTA). For this reason an external guard circuit can be applied to detect failures of the deflection (see Fig.5). This circuit will be activated when flyback pulses are missing, which is the indication of any abnormal operation. Guard circuit The internal guard circuit provides a blanking signal for the CRT. The guard signal is active HIGH: The guard output pin can be used as input for the power save mode. A current or a voltage has to be applied to the pin. In this case the output stages are switched off completely. • At thermal overshoot • During flyback • When missing flyback supply voltage • When power supply voltage too low, VP < VP(min). LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages referenced to ground (pin GND); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage 0 30 V VFB flyback supply voltage 0 60 V IFB flyback supply current 0 ±1.8 A VINP, VINN input voltage 0 5 V IINP, IINN input current 0 ±5 mA VOUTB output voltage on pin OUTB 0 VP V VOUTA output voltage on pin OUTA 0 VFB V 0 ±1.6 A IOUTB, IOUTA output current note 1 VFEEDB feedback voltage 0 VP V IFEEDB feedback current 0 ±5 mA VGUARD guard voltage 0 10 V IGUARD guard current 0 ±5 mA Tstg storage temperature −20 +150 °C Tamb ambient temperature −20 +75 °C Tj junction temperature note 2 −20 +150 °C Vesd electrostatic discharge voltage note 3 −4000 +4000 V note 4 −250 +250 V Notes 1. Maximum output currents IOUTB and IOUTA are limited by current protection. 2. Internally limited by thermal protection; will be activated for Tj ≥ 150 °C. 3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor. 4. Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 µH inductance. 2003 Feb 05 5 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J THERMAL CHARACTERISTICS SYMBOL Rth(j-mb) PARAMETER CONDITIONS thermal resistance from junction to mounting base note 1 VALUE UNIT 4 K/W Note 1. To minimize the thermal resistance from mounting base to heatsink [Rth(mb-h)] follow the recommended mounting instruction: screw mounting preferred; torque = 40 Ncm; use heatsink compound; isolation plate increases Rth(mb-h). CHARACTERISTICS VP = 12 V; Tamb = 25 °C; VFB = 40 V; voltages referenced to ground (pin GND); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC supplies (pins VP and VFB) − VP supply voltage VFB flyback supply voltage note 1 VP + 6 − 60 V Iq(FB) quiescent flyback current no load; no signal − 2.5 4 mA Iq(P) quiescent supply current Idefl = 0 − 80 130 mA 8.2 25 V Input stage (pins INP, INN and FEEDB) Ii(dif) differential input current note 2 − ±500 ±600 µA Ii(dif)(offset) differential input offset current [Ii(dif)(offset) = IINP − IINN] Idefl = 0; Rref = 3 kΩ; Rm = 1 Ω 0 − ±20 µA IINP, IINN single-ended input current 0 ±300 ±600 µA Vclamp(INP) input clamp voltage on pin INP IINP = IINN = 0; note 3 2.7 3.0 3.3 V Vclamp(INN) input clamp voltage on pin INN IINP = IINN = 0; note 3 2.7 3.0 3.3 V IFEEDB feedback current − ±250 ±300 µA VFEEDB feedback voltage 1 − VP − 1 V Output stages (pins OUTA and OUTB) Idefl(p-p) deflection current (peak-to-peak value) 0.6 − 2.5 A IOUTA, IOUTB output current ±0.3 − ±1.25 A Vsat(OUTA-GND) saturation voltage pin OUTA to pin GND IOUTA = 0.7 A − 1.1 1.3 V IOUTA = 1.25 A; note 4 − 1.6 1.8 V Vsat(VP-OUTA) saturation voltage pin VP to pin OUTA IOUTA = 0.7 A − 2.1 2.7 V IOUTA = 1.25 A; note 4 − 2.8 3.4 V Vsat(OUTB-GND) saturation voltage pin OUTB to pin GND IOUTB = 0.7 A − 1.1 1.3 V IOUTB = 1.25 A; note 4 − 1.6 1.8 V Vsat(VP-OUTB) saturation voltage pin VP to pin OUTB IOUTB = 0.7 A − 1.0 1.4 V IOUTB = 1.25 A; note 4 − 1.6 2.0 V LE linearity error Idefl = ±0.7 A; note 5 − − 2 % VOUTA, VOUTB DC output voltage Ii(dif) = 0; closed loop 5.1 5.7 6.3 V 2003 Feb 05 6 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster SYMBOL TDA4867J PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Flyback generator IFB(p-p) maximum current during flyback on pin VFB (peak-to-peak value) VFB-OUTA voltage drop during flyback between pin VFB and pin OUTA − − 2.5 A Idefl = −0.7 A − −2.6 −3 V Idefl = −1.25 A − −3.1 −3.9 V − 5.2 6.1 V reverse forward Idefl = 0.7 A − 5.7 6.9 V VP − 1 − VP + 1 V guard on; IGUARD = −5 mA 5 6 − V guard off; IGUARD = 0 − − 0.4 V Idefl = 1.25 A Vth(OUTA) switch-on threshold voltage on pin OUTA Guard circuit (pin GUARD) VGUARD output voltage IGUARD output current guard on; VGUARD > 5 V −5 − − mA Vext external voltage for guard function 0 − 6.5 V for power save mode; IGUARD = 0.5 mA 8.2 − 9.5 V Notes 1. If VFB is between 40 and 60 V a decoupling capacitor CFB = 22 µF (between pin VFB and pin GND) and a resistor RFB = 100 Ω (between pin VFB and flyback supply voltage) are required (see Fig.6). 2. Differential input current Ii(dif) = IINP − IINN. 3. Input resistance is 500 Ω. 4. Required VP depends on the impedance of the deflection yoke. 5. Deviation of the output slope at a constant input slope. 2003 Feb 05 7 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J handbook, full pagewidth IINP (µA) Driver current from TDA485x, TDA4841PS or SAA4856 on pin INP. t (ms) IINN (µA) Driver current from TDA485x, TDA4841PS or SAA4856 on pin INN. t (ms) VOUTA (V) VFB VP Output voltage on pin OUTA. t (ms) VOUTB (V) VP Output voltage on pin OUTB. t (ms) Idefl (A) t (ms) Deflection current through the coil. VGUARD (V) Output voltage on pin GUARD during normal operation. t (ms) t flb flyback time t flb depends on VFB MGU990 Fig.3 Timing diagram. 2003 Feb 05 8 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J INTERNAL PIN CONFIGURATION handbook, full pagewidth 8 3 7 VP 2 6 TDA4867J 1 5 9 4 VP MGU991 Fig.4 Internal circuits. 2003 Feb 05 9 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J APPLICATION INFORMATION VP VFB handbook, full pagewidth TDA4867J 7 1N4448 VFB 2.2 kΩ guard output, HIGH = error BC556 6 2.2 Ω OUTA 3.3 kΩ BC548 220 kΩ 22 µF vertical output signal MGU992 Fig.5 Application circuit for external guard signal generation. handbook, full pagewidth TDA4867J 1 2 3 IINP 5 4 Rm 1Ω from driver circuit TDA485x or SAA4856 Ldeflcoil = 5.2 mH Rdeflcoil = 4.2 Ω 10 Ω Rp VP 220 Ω 220 µF 7 8 guard output or power save mode input (2) Rref 3.4 kΩ RFB VFB (1) (1) CFB 100 µF (VFB < 40 V) (1) If VFB is between 40 and 60 V a resistor RFB = 100 Ω and a capacitor CFB = 22 µF are required. (2) The value of CSP is application dependent, but 10 nF minimum is required. Fig.6 Application diagram with driver circuit TDA485x or SAA4856. 2003 Feb 05 10 9 CSP RSP IINN 6 MGU993 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J Example Table 1 Table 2 Values given from application diagram Fig.6 SYMBOL VALUE Calculated values SYMBOL UNIT VALUE UNIT VP 8.5 V tflb ≈200 µs Idefl 0.71 A Ldeflcoil 5.2 mH Ptot 3.4 W 5.4 [= 4.2 + 7% + ∆R(ϑ)] Ω Pdefl 0.9 W Rm 1 (+1%) Ω PIC 2.5 W Rp 220 Ω Rth(tot) 10 K/W Tj(max)(1) 75 °C Rdeflcoil Rref 3.4 kΩ VFB 40 V Note Tamb 50 °C 75 °C 1. Tj(max) = PIC × [Rth(j-mb) + Rth(mb-amb)] + Tamb. Tdeflcoil Rth(j-mb) 4 K/W Rth(mb-amb)(1) 6 K/W Note 1. Use heatsink compound. Calculation formulae for supply voltage: Vb1 = Vsat(VP-OUTA) + Rdeflcoil × Idefl − U’L + Rm × Idefl + Vsat(OUTB-GND) Vb2 = Vsat(OUTA-GND) + Rdeflcoil × Idefl + U’L + Rm × Idefl + Vsat(VP-OUTB) for Vb1 > Vb2 : VP = Vb1 for Vb2 > Vb1 : VP = Vb2 where: U’L = Ldeflcoil × 2 × Idefl × fv fv = vertical deflection frequency. Calculation formulae for power consumption: P IC = P tot – P defl I defl P tot = V P × -------- + V P × 0.02 A + 0.1 W + V FB × I FB 2 1 2 P defl = --- × ( R deflcoil + R m ) × I defl 3 where: PIC = power dissipation of the TDA4867J Ptot = total power dissipation Pdefl = power dissipation of the deflection coil. L deflcoil V FB + ( R deflcoil + R m ) × I defl Calculation formulae for flyback time (tflb): t flb ≈ --------------------------------- × ln --------------------------------------------------------------------- V FB – ( R deflcoil + R m ) × I defl R deflcoil + R m 2003 Feb 05 11 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J PACKAGE OUTLINE DBS9P: plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad SOT523-1 q1 non-concave x Eh Dh D D1 view B: mounting base side P A2 k q2 B E q L2 L3 L1 L 1 9 e1 Z e Q w M bp 0 5 scale DIMENSIONS (mm are the original dimensions) UNIT A2(2) bp mm c D(1) D1(2) Dh E(1) Eh 2.7 0.80 0.58 13.2 2.3 0.65 0.48 12.8 10 mm v M c e2 m e e1 e2 L L1 L2 L3 m 6.2 14.7 3.0 12.4 11.4 6.7 3.5 3.5 2.54 1.27 5.08 5.8 14.3 2.0 11.0 10.0 5.5 4.5 3.7 2.8 k P Q q q1 q2 3.4 1.15 17.5 4.85 3.8 3.1 0.85 16.3 3.6 v 0.8 w x 0.3 0.02 Z(1) 1.65 1.10 Notes 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 2. Plastic surface within circle area D1 may protrude 0.04 mm maximum. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 98-11-12 00-07-03 SOT523-1 2003 Feb 05 EUROPEAN PROJECTION 12 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction to soldering through-hole mount packages The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL WAVE suitable(1) suitable Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 2003 Feb 05 13 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection booster TDA4867J DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Feb 05 14