PHILIPS 74LVT245BD

74LVT245B
3.3 V octal transceiver with direction pin (3-state)
Rev. 02 — 8 May 2008
Product data sheet
1. General description
The 74LVT245B is a high-performance BiCMOS product designed for VCC operation at
3.3 V.
This device is an octal transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. The device features an output enable (OE) input for easy
cascading and a direction (DIR) input for direction control.
2. Features
n
n
n
n
n
n
n
n
n
n
n
3-state buffers
Octal bidirectional bus interface
Input and output interface capability to systems at 5 V supply
TTL input and output switching levels
Output capability: +64 mA/−32 mA
Latch-up protection exceeds 500 mA per JEDEC Std 17
ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
Live insertion/extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT245BD
−40 °C to +85 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVT245BDB
−40 °C to +85 °C
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74LVT245BPW −40 °C to +85 °C
74LVT245BBQ
−40 °C to +85 °C
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
SOT764-1
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
4. Functional diagram
1
DIR
OE
2
B0
3
19
3EN1
3EN2
1
14
18
3
17
13
4
16
5
15
6
14
7
13
8
12
A6
12
A7
B7
11
9
mna174
Fig 1.
2
A5
B6
9
G3
2
B5
8
15
A4
B4
7
1
16
A3
B3
6
17
A2
B2
5
18
A1
B1
4
19
A0
Logic diagram
Fig 2.
74LVT245B_2
Product data sheet
11
mna175
IEC logic symbol
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
2 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
5. Pinning information
5.1 Pinning
1
terminal 1
index area
20 VCC
DIR
74LVT245B
A0
2
19 OE
A1
3
18 B0
A2
4
17 B1
DIR
1
A0
2
20 VCC
19 OE
A1
3
18 B0
A3
5
16 B2
A2
4
17 B1
A4
6
15 B3
A3
5
16 B2
A5
7
A4
6
A6
8
A5
7
14 B4
A6
8
13 B5
A7
9
A7
9
12 B6
GND 10
11 B7
14 B4
GND(1)
13 B5
12 B6
B7 11
15 B3
GND 10
74LVT245B
001aah724
Transparent top view
001aah723
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 3.
Pin configuration for SO20 and (T)SSOP20
Fig 4.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
DIR
1
direction control
A0 to A7
2, 3, 4, 5, 6, 7, 8, 9
data input/output
GND
10
ground (0 V)
B0 to B7
18, 17, 16, 15, 14, 13, 12, 11
data input/output
OE
19
output enable input (active LOW)
VCC
20
supply voltage
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
3 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
6. Functional description
Table 3.
Function selection
Inputs
Inputs/outputs
OE
DIR
An
Bn
L
L
An = Bn
inputs
L
H
inputs
Bn = An
H
X
Z
Z
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).[1][2]
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
−0.5
+4.6
V
[3]
−0.5
+7.0
V
[3]
−0.5
+7.0
V
VI
input voltage
VO
output voltage
output in OFF or HIGH state
IIK
input clamping current
VI < 0
−50
-
mA
IOK
output clamping current
VO < 0
−50
-
mA
IO
output current
output in LOW state
-
128
mA
output in HIGH state
−64
-
mA
−65
+150
°C
[2]
-
150
°C
[4]
-
500
mW
storage temperature
Tstg
junction temperature
Tj
total power dissipation
Ptot
Tamb = −40 °C to +85 °C
[1]
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
[2]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
[3]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[4]
For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
4 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
2.7
3.6
V
VI
input voltage
0
5.5
V
IOH
HIGH-level output current
-
−32
mA
IOL
LOW-level output current
-
32
mA
current duty cycle ≤ 50 %; fi ≥ 1 kHz
-
64
mA
Tamb
ambient temperature
in free air
−40
+85
°C
∆t/∆V
input transition rise and fall rate
output enabled
0
10
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIK
input clamping voltage
−40 °C to +85 °C
Conditions
VCC = 2.7 V; IIK = −18 mA
Unit
Min
Typ[1]
Max
−1.2
−0.9
-
V
V
VIH
HIGH-level input voltage
2.0
-
-
VIL
LOW-level input voltage
-
-
0.8
VOH
HIGH-level output voltage
VOL
II
LOW-level output voltage
input leakage current
VCC = 2.7 V to 3.6 V; IOH = −100 µA
VCC − 0.2 VCC − 0.1
VCC = 2.7 V; IOH = −8 mA
2.4
VCC = 3.0 V; IOH = −32 mA
2.0
VCC = 2.7 V; IOL = 100 µA
2.5
-
V
-
2.2
-
V
0.1
0.2
V
VCC = 2.7 V; IOL = 24 mA
-
0.3
0.5
V
VCC = 3.0 V; IOL = 16 mA
-
0.25
0.4
V
VCC = 3.0 V; IOL = 32 mA
-
0.3
0.5
V
VCC = 3.0 V; IOL = 64 mA
-
0.4
0.55
V
-
1
10
µA
-
±0.1
±1
µA
VCC = 3.6 V; VI = 5.5 V
-
1
20
µA
VCC = 3.6 V; VI = VCC
-
0.1
1
µA
VCC = 3.6 V; VI = 0 V
−5
−1
-
µA
-
1
±100 µA
control pins
VCC = 0 V or 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = VCC or GND
[2]
I/O data pins
IOFF
power-off leakage current
VCC = 0 V; VI or VO = 0 V to 4.5 V
ILO
output leakage current
VO = 5.5 V; VCC = 3.6 V; output HIGH
IO(pu/pd)
power-up/power-down
output current
IBHL
µA
-
60
125
VCC ≤ 1.2 V VO = 0.5 V to VCC;
VI = GND or VCC; OE = don’t care
[3]
-
15
±100 µA
bus hold LOW current
VCC = 3.0 V; VI = 0.8 V
[4]
75
150
-
µA
IBHH
bus hold HIGH current
VCC = 3.0 V; VI = 2.0 V
−150
−75
-
µA
IBHLO
bus hold LOW
overdrive current
VCC = 0 V to 3.0 V; VI = 3.6 V
500
-
-
µA
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
5 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
−40 °C to +85 °C
Conditions
Unit
Min
Typ[1]
-
-
outputs HIGH
-
0.13
0.19
mA
outputs LOW
-
3
12
mA
-
0.13
0.19
mA
-
0.1
0.2
mA
IBHHO
bus hold HIGH
overdrive current
VCC = 0 V to 3.0 V; VI = 3.6 V
ICC
supply current
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
outputs disabled
Max
−500 µA
∆ICC
additional supply current
per input pin; VCC = 3.0 V to 3.6 V;
one input = VCC − 0.6 V others = VCC or GND
CI
input capacitance
DIR and OE inputs; VI = 0 V or 3.0 V
-
4
-
pF
CI/O
input/output capacitance
at input/output data pins, outputs disabled;
VI/O = 0 V or 3.0 V
-
10
-
pF
[5]
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
[2]
Unused pins at VCC or GND.
[3]
This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.6 V a
transition time of 100 ms is permitted. This parameter is valid for Tamb = +25 °C only.
[4]
This is the bus hold overdrive current required to force the input to the opposite logic state.
[5]
This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
tPLH
LOW to HIGH propagation delay
VCC = 3.3 V ± 0.3 V
HIGH to LOW propagation delay
VCC = 3.3 V ± 0.3 V
VCC = 3.3 V ± 0.3 V
-
-
4.0
ns
1.2
2.4
3.5
ns
-
-
4.0
ns
1.2
2.4
3.5
ns
-
-
7.1
ns
1.3
3.3
5.5
ns
OFF-state to LOW propagation delay see Figure 6
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
tPHZ
Max
OFF-state to HIGH propagation delay see Figure 6
VCC = 2.7 V
tPZL
Typ[1]
An to Bn or Bn to An
VCC = 2.7 V
tPZH
Unit
Min
An to Bn or Bn to An
VCC = 2.7 V
tPHL
−40 °C to +85 °C
Conditions
-
-
6.5
ns
1.7
3.2
5.5
ns
-
-
6.5
ns
2.2
3.6
5.9
ns
HIGH to OFF-state propagation delay see Figure 6
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
6 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
−40 °C to +85 °C
Conditions
Max
-
-
5.1
ns
2.2
3.4
5.0
ns
Min
tPLZ
LOW to OFF-state propagation delay see Figure 6
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
[1]
Unit
Typ[1]
Typical values are measured at Tamb = 25 °C and VCC = 3.3 V
11. Waveforms
VI
VM
An, Bn input
VM
GND
tPHL
tPLH
VOH
VM
Bn, An output
VM
VOL
001aah732
See Table 8 for measurement points.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Input (An, Bn) to output (Bn, An) propagation delays and output transition times
VI
VM
OE input
GND
tPLZ
tPZL
3.0 V
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aah733
See Table 8 for measurement points.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
3-state output enable and disable times
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
7 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
Table 8.
Measurement points
VCC
Input
2.7 V to 3.6 V
Output
VIN
VM
VM
Vx
Vy
GND to 2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
VI
tf
tr
tr
tf
90 %
positive
pulse
VM
VM
10 %
0V
tW
VEXT
VCC
PULSE
GENERATOR
VI
RL
VO
DUT
RT
CL
RL
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Fig 7.
Table 9.
Test circuit for switching times
Test data
Input
Load
VEXT
VI
fi
tW
tr, tf
RL
CL
tPHZ, tPZH
tPLZ, tPZL
tPLH, tPHL
2.7 V
≤ 10 MHz
500 ns
≤ 2.5 ns
500 Ω
50 pF
GND
6V
open
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
8 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
11
20
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT163-1 (SO20)
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
9 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
D
SOT339-1
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
w M
bp
e
detail X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.9
0.5
8
o
0
o
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT339-1
Fig 9.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Package outline SOT339-1 (SSOP20)
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
10 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
E
D
A
X
c
HE
y
v M A
Z
11
20
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
10
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT360-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 10. Package outline SOT360-1 (TSSOP20)
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
11 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT764-1
20 terminals; body 2.5 x 4.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
9
y
y1 C
v M C A B
w M C
b
L
1
10
Eh
e
20
11
19
12
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT764-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 11. Package outline SOT764-1 (DHVQFN20)
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
12 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
BiCMOS
Bipolar Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVT245B_2
20080508
Product data sheet
ECN07_046
74LVT245B_1
Modifications:
74LVT245B_1
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
DHVQFN20 package added to Section 3 “Ordering information” and Section 12 “Package outline”
19990319
Product specification
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74LVT245B_2
Product data sheet
-
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
13 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LVT245B_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 8 May 2008
14 of 15
74LVT245B
NXP Semiconductors
3.3 V octal transceiver with direction pin (3-state)
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 May 2008
Document identifier: 74LVT245B_2