INTEGRATED CIRCUITS DATA SHEET TDA3617 Multiple voltage regulator Preliminary specification File under Integrated Circuits, IC01 1999 Jul 14 Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 FEATURES • Thermal protection General • Load dump protection • Three VP-state controlled regulators (regulators 1, 2 and 3) • Foldback current limit protection for regulators 1, 2 and 3 • DC short-circuit safe to ground and VP for all regulator outputs. • Very good stability and noise behaviour • Separate control pins for switching regulators 1, 2 and 3 • Supply voltage range from −18 to +50 V GENERAL DESCRIPTION • Low quiescent current (when regulators 1, 2 and 3 are switched off) The TDA3617J is a multiple output voltage regulator with three independent regulators. It contains: • High ripple rejection 1. Three fixed voltage regulators with foldback current protection (regulators 1, 2 and 3) • Hold output for indicating regulator 1 and/or 2 and/or 3 out of regulation. 2. A supply pin that can withstand load dump pulses and negative supply voltages Protections • Reverse polarity safe (down to −18 V without high reverse current) 3. Independent enable inputs for regulators 1, 2 and 3 • Able to withstand voltages up to 18 V at the outputs (supply line may be short circuited) 5. A hold output that can be used to interface with a microprocessor. The hold indicates that the selected output voltages are available and within their ranges. 4. Local temperature protection for regulator 3 • ESD protection on all pins QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP supply voltage operating 9.5 14.4 17.5 V jump start t ≤ 10 minutes − − 30 V load dump protection for 50 ms; tr ≥ 2.5 ms − − 50 V standby mode − 5 40 µA − − 175 °C Iq(tot) total quiescent current Tj junction temperature Voltage regulators VREG1 output voltage regulator 1 1 mA ≤ IREG1 ≤ 1.3 A 8.55 9.0 9.45 V VREG2 output voltage regulator 2 1 mA ≤ IREG2 ≤ 600 mA; VP = 14.4 V 4.75 5.0 5.25 V VREG3 output voltage regulator 3 1 mA ≤ IREG3 ≤ 300 mA 3.14 3.3 3.46 V ORDERING INFORMATION TYPE NUMBER TDA3617J 1999 Jul 14 PACKAGE NAME DBS9P DESCRIPTION plastic DIL-bent-SIL power package; 9 leads (lead length 7.7 mm) 2 VERSION SOT157-4 Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 BLOCK DIAGRAM handbook, full pagewidth VP (14.4 V) 3 TEMPERATURE LOAD DUMP PROTECTION & REGULATOR 1 & REGULATOR 2 & REGULATOR 3 4 (9 V/1.3 A) REG1 2 Ven1 Ven2 9 Ven3 1 6 (5 V/600 mA) REG2 5 (3.3 V/300 mA) 7 REG3 HOLD HOLD TDA3617 8 MGL589 GND Fig.1 Block diagram. PINNING SYMBOL PIN DESCRIPTION Ven3 1 enable input regulator 3 Ven1 2 enable input regulator 1 VP 3 supply voltage REG1 4 REG3 handbook, halfpage Ven3 1 Ven1 2 regulator 1 output VP 3 5 regulator 3 output REG1 4 REG2 6 regulator 2 output REG3 5 HOLD 7 hold output REG2 6 GND 8 ground HOLD 7 Ven2 9 enable input regulator 2 GND 8 Ven2 9 TDA3617 MGL590 Fig.2 Pin configuration. 1999 Jul 14 3 Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 The TDA3617J has a hold circuit which indicates when one of the regulators is out-of-regulation. The hold function is disabled when all the enable inputs are LOW (TDA3617J in standby mode). The HOLD output (open collector output) can be wired OR-ed with other hold outputs of other regulator parts (e.g. TDA3618). When all the regulators of the TDA3617J are disabled (switched off), the HOLD output will be high ohmic. Because of this feature, the hold will not influence the hold information when wired OR-ed with other regulator parts. FUNCTIONAL DESCRIPTION The TDA3617J is a multiple output voltage regulator with three independent switchable regulators. When the supply voltage (VP > 4.5 V) is available, regulators 1, 2 and 3 can be operated by means of three independent enable inputs. Schmitt trigger functions are included to switch the regulators off at low battery voltage (VP < 4 V). A hysteresis is included to avoid random switching. All output pins are fully protected. The regulators are protected against load dump (the regulators switch off at supply voltages higher than 20 V) and short circuit (foldback current protection). handbook, full pagewidth Figure 3 shows the total timing of a semi-on/off logic set. Figure 4 shows the total timing of the HOLD signal. load dump 18.0 V VP 9.4 V 4.5 V 4.0 V ≥2.2 V enable regulator 1 ≤2.0 V 9.0 V regulator 1 0V ≥2.2 V enable regulator 2 ≤2.0 V 5.0 V regulator 2 0V ≥2.2 V enable regulator 3 ≤2.0 V 3.3 V regulator 3 0V MGL621 Fig.3 Timing diagrams of a semi-on/off logic set. 1999 Jul 14 4 Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 load dump handbook, full pagewidth VP enable regulator 2 and/or 3 enable regulator 1 out of regulation regulator output 2 and/or 3 out of regulation short circuit out of regulation regulator output 1 temperature active protection >150 °C passive HOLD MGL622 Fig.4 Timing diagrams of the HOLD signal. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP PARAMETER CONDITIONS MIN. MAX. UNIT supply voltage − operating 17.5 V jump start t ≤ 10 minutes − 30 V load dump protection for 50 ms; tr ≥ 2.5 ms − 50 V non-operating − −18 V Vbat(rp) reverse polarity battery voltage Ptot total power dissipation − 62 W Tstg storage temperature non-operating −55 +150 °C Tamb ambient temperature operating −40 +85 °C Tj junction temperature operating − 175 °C 1999 Jul 14 5 Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth(j-c) thermal resistance from junction to case regulator and switch-on 2 K/W Rth(j-a) thermal resistance from junction to ambient in free air 50 K/W QUALITY SPECIFICATION In accordance with “SNW-FQ-611-E”. The number of the quality specification can be found in the “Quality Reference Handbook”. CHARACTERISTICS VP = 14.4 V; Tamb = 25 °C; measured in test circuit of Fig.6; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VP supply voltage operating Iq 9.5 14.4 17.5 V REGn on note 1 6 14.4 17.5 V jump start t ≤ 10 minutes − − 30 V load dump protection for 50 ms; tr ≥ 2.5 ms − − 50 V VP = 12.4 V; note 2 − 5 40 µA VP = 14.4 V; note 2 − 5 − µA quiescent current Power supply Schmitt trigger for regulators 1, 2 and 3 Vthr rising voltage threshold Ven = 3 V 6.2 6.8 7.5 V Vthf falling voltage threshold Ven = 3 V 4.0 4.5 5.0 V Vhys hysteresis 1.5 2.3 3.0 V +1.2 V Enable input (regulators 1, 2 and 3) −0.2 Vi(off) off-level input voltage Vi(on) on-level input voltage − 1.8 − V ILI input leakage current Ven = 5 V 5 30 50 µA IsinkL LOW-level sink current VHOLD ≤ 0.8 V 2 − − mA ILO output leakage current VHOLD = 5 V − 0 5 µA Hold buffer 1999 Jul 14 6 Philips Semiconductors Preliminary specification Multiple voltage regulator SYMBOL TDA3617 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Regulator 1 (IREG1 = 5 mA) VREG1(off) output voltage off VREG1 output voltage − 1 400 mV 1 mA ≤ IREG1 ≤ 1.3 A 8.55 9.0 9.45 V 10.5 V ≤ VP ≤ 17.5 V 8.55 9.0 9.45 V ∆VREG1 line regulation 10.5 V ≤ VP ≤ 17.5 V − 20 50 mV ∆VREGL1 load regulation 1 mA ≤ IREG1 ≤ 1.3 A − 35 70 mV IqREG1 quiescent current IREG1 = 1.3 A − 45 110 mA SVRR1 supply voltage ripple rejection f = 3 kHz; Vi(p-p) = 2 V 60 70 − dB VREG1d drop-out voltage IREG1 = 1.3 A; note 3 − 0.5 1 V IREG1m current limit VREG1 > 7.5 V; note 4 1.3 1.4 − A IREG1sc short-circuit current RL ≤ 0.5 Ω; note 5 250 500 − mA αct cross talk noise note 6 − 25 150 µV Schmitt trigger for hold of regulator 1 Vthr rising threshold voltage of regulator 1 VP rising − VREG1 − 0.15 VREG1 − 0.075 V Vthf falling threshold voltage of regulator 1 VP falling 8.1 VREG1 − 0.35 − V Vhys hysteresis voltage 0.1 0.2 0.3 V − 1 400 mV 0.5 mA ≤ IREG2 ≤ 600 mA 4.75 5.0 5.25 V 8 V ≤ VP ≤ 17.5 V 4.75 5.0 5.25 V Regulator 2 (IREG2 = 5 mA) VREG2(off) output voltage off VREG2 output voltage ∆VREG2 line regulation 8 V ≤ VP ≤ 17.5 V − 2 50 mV ∆VREGL2 load regulation 1 mA ≤ IREG2 ≤ 600 mA − 20 85 mV IqREG2 quiescent current IREG2 = 0.4 A − 10 40 mA SVRR2 supply voltage ripple rejection f = 3 kHz; Vi(p-p) = 2 V 60 70 − dB VREG2d drop-out voltage IREG2 = 600 mA; VP = 6 V; note 3 − 1 1.5 V IREG2m current limit VREG2 > 4 V; note 4 0.65 0.8 − A IREG2sc short-circuit current RL ≤ 0.5 Ω; note 5 100 300 − mA αct cross talk noise note 6 − 25 150 µV Schmitt trigger for hold of regulator 2 Vthr rising threshold voltage of regulator 2 VP rising − VREG1 − 0.15 VREG1 − 0.075 V Vthf falling threshold voltage of regulator 2 VP falling 4.3 VREG1 − 0.35 − V Vhys hysteresis voltage 0.1 0.2 0.3 V 1999 Jul 14 7 Philips Semiconductors Preliminary specification Multiple voltage regulator SYMBOL TDA3617 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Regulator 3 (IREG3 = 5 mA) VREG3(off) output voltage off VREG3 output voltage − 1 400 mV 1 mA ≤ IREG3 ≤ 300 mA 3.14 3.3 3.46 V 5 V ≤ VP ≤ 17.5 V 3.14 3.3 3.46 V ∆VREG3 line regulation 5 V ≤ VP ≤ 17.5 V − 2 50 mV ∆VREGL3 load regulation 1 mA ≤ IREG3 ≤ 300 mA − 20 50 mV IqREG3 quiescent current IREG3 = 300 mA − 10 15 mA SVRR3 supply voltage ripple rejection f = 3 kHz; Vi(p-p) = 2 V 60 70 − dB IREG3m current limit VREG3 > 3 V; note 4 0.35 0.45 − A IREG3sc short circuit current RL ≤ 0.5 Ω; note 5 15 50 − mA αct cross talk noise note 6 − 25 150 µV Schmitt trigger for hold of regulator 3 Vthr rising threshold voltage of regulator 3 VP rising − VREG1 − 0.15 VREG1 − 0.075 V Vthf falling threshold voltage of regulator 2 VP falling 2.7 VREG1 − 0.35 − V Vhys hysteresis voltage 0.1 0.2 0.3 V Notes 1. Minimum operating voltage, only if VP has exceeded 4.5 V. 2. The quiescent current is measured in the standby mode. Therefore, the enable inputs of regulators 1, 2 and 3 are LOW (Ven < 1 V). 3. The drop-out voltage of regulators 1, 2 and 3 is measured between VP and VREGn. 4. At current limit, IREGmn is held constant (see Fig.5 for the behaviour of IREGmn). 5. The foldback current protection limits the dissipated power at short circuit (see Fig.5). 6. Perform the load regulation test with sine wave load of 10 kHz on the regulator output under test. Measure the RMS ripple voltage on each of the remaining regulator outputs, using a 80 kHz low-pass filter. 1999 Jul 14 8 Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 handbook, halfpage MGL623 9V handbook, halfpage VREG2 VREG1 MGL592 5V 1V 2V IREG2sc ≥50 mA IREG1sc ≥300 mA IREG1 a. Regulator 1. b. Regulator 2. handbook, halfpage VREG3 MGL591 3.3 V 1V ≥200 mA IREG3sc IREG3m IREG3 c. Regulator 3. Fig.5 Foldback current protection for regulators 1, 2 and 3. 1999 Jul 14 IREG2m IREG2 IREG1m 9 Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 TEST AND APPLICATION INFORMATION Test information handbook, full pagewidth VP C1 220 nF VP (1) 3 7 9 6 enable input regulator 2 Ven2 HOLD regulator 2 C2 47 µF TDA3617 enable input regulator 3 5V RL(REG2) 1 kΩ 5 1 regulator 3 3.3 V C3 47 µF Ven3 enable input regulator 1 regulator 1 2 4 1 kΩ 9V C4 47 µF 8 Ven1 RL(REG3) GND RL(REG1) 1 kΩ MGL593 (1) Capacitor not required for stability. Fig.6 Test circuit. Application information when a high frequency capacitor of 220 nF in parallel with an electrolytic capacitor of 100 µF is connected directly to pins 3 and 8 (supply and ground). NOISE Table 1 Noise figures STABILITY NOISE FIGURE (µV)(1) REGULATOR The regulators are stabilized with the externally connected output capacitors. The value of the output capacitors can be selected by referring to the graph illustrated in Fig.7. Co = 10 µF Co = 47 µF Co = 100 µF 1 tbf 150 tbf 2 tbf 150 tbf 3 tbf 200 tbf When an electrolytic capacitor is used, its temperature behaviour can cause oscillations at temperatures lower than −20 °C. In this case, use a tantalum capacitor. Note The two examples on the next page show how an output capacitor value is selected. 1. Measured at a bandwidth of 200 kHz. The noise on the supply line depends on the value of the supply capacitor and is caused by a current noise (output noise of the regulators is translated to a current noise by means of the output capacitors). The noise is minimum 1999 Jul 14 10 Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 Example 1 Regulators 1, 2 and 3 are stabilized with an electrolytic output capacitor of 220 µF (ESR = 0.15 Ω). At −30 °C, the capacitor value is decreased to 73 µF and the ESR is increased to 1.1 Ω. The regulator will remain stable at −30 °C. MGK612 handbook, halfpage 20 R (Ω) 15 maximum ESR Example 2 10 Regulators 1, 2 and 3 are stabilized with an electrolytic output capacitor of 10 µF (ESR = 3.18 Ω). At −30 °C, the capacitor value is decreased to 3.3 µF and the ESR is increased to 23 Ω. The regulator will be instable at −30 °C. 5 stable region 0 0.1 Solution Use a 47 nF HF capacitor in parallel with the output electrolytic output capacitor. As can be seen from the graph in Fig.7, the regulators will remain stable with an output capacitor of 47 nF onwards. The electrolytic output capacitor is only needed to minimize the output noise. 1999 Jul 14 Fig.7 11 1 10 C (µF) 100 Curve for selecting the value of output capacitor for regulator 1. Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 PACKAGE OUTLINE DBS9P: plastic DIL-bent-SIL power package; 9 leads (lead length 7.7 mm) SOT157-4 non-concave Dh x D Eh view B: mounting base side d A2 B j E A L3 L Q 1 c v M 9 e1 Z bp e e2 m w M 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A2 bp c D (1) d Dh E (1) e mm 17.0 15.5 4.6 4.2 0.75 0.60 0.48 0.38 24.0 23.6 20.0 19.6 10 12.2 11.8 5.08 e1 e2 2.54 5.08 Eh j L L3 m Q v w x Z (1) 6 3.4 3.1 8.4 7.0 2.4 1.6 4.3 2.1 1.8 0.6 0.25 0.03 2.00 1.45 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-03-11 97-12-16 SOT157-4 1999 Jul 14 EUROPEAN PROJECTION 12 Philips Semiconductors Preliminary specification Multiple voltage regulator TDA3617 The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction to soldering through-hole mount packages The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL WAVE suitable(1) suitable Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545002/01/pp16 Date of release: 1999 Jul 14 Document order number: 9397 750 04839