PHILIPS TDA4886

INTEGRATED CIRCUITS
DATA SHEET
TDA4886
140 MHz video controller with
I2C-bus
Product specification
Supersedes data of 1998 Nov 04
File under Integrated Circuits, IC02
1998 Nov 11
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
QUICK REFERENCE DATA
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
7.9
7.10
Signal input stage (input clamping, blanking
and clipping)
Electronic potentiometer stages
Output stage
Pedestal blanking
Output clamping, feedback references and
DAC outputs
Clamping and blanking pulses
On Screen Display (OSD)
Subcontrast/contrast modulation and beam
current limiting
I2C-bus control
I2C-bus data buffer
8
LIMITING VALUES
9
THERMAL CHARACTERISTICS
10
CHARACTERISTICS
11
I2C-BUS PROTOCOL
12
TEST AND APPLICATION INFORMATION
12.1
12.2
Test boards
Recommendations for building the application
board
13
INTERNAL CIRCUITRY
14
PACKAGE OUTLINE
15
SOLDERING
15.1
15.2
15.3
Introduction
Soldering by dipping or by wave
Repairing soldered joints
16
DEFINITIONS
17
LIFE SUPPORT APPLICATIONS
18
PURCHASE OF PHILIPS I2C COMPONENTS
7.2
7.3
7.4
7.5
7.6
7.7
7.8
1998 Nov 11
2
TDA4886
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
1
TDA4886
FEATURES
• 140 MHz pixel rate
• 3.2 ns rise time, 4 ns fall time
• I2C-bus control
• I2C-bus data buffer for synchronization of adjustments
• Grey scale tracking
2
• On Screen Display (OSD) mixing with 50 MHz pixel rate
The TDA4886 is a monolithic integrated RGB pre-amplifier
for colour monitor systems (e.g. 15" and 17") with I2C-bus
control and OSD. In addition to bus control, beam current
limiting and contrast modulation are possible. The signals
are amplified in order to drive commonly used video
modules or discrete solutions. Individual black level control
with negative feedback from the cathode (DC coupling) or
gradually adaptable black level control with positive
feedback and 3 DAC outputs for external cut-off control
(AC coupling) is possible.
• OSD contrast
• Negative feedback for DC-coupled cathodes
• Especially for AC-coupled cathodes
– Black level adaptable to kind of post amplifier
– Internal positive feedback
– DAC outputs for black level restoration.
• Integrated black level storage capacitors
• Beam current limiting
GENERAL DESCRIPTION
With special advantages the circuit can be used in
conjunction with the TDA485X monitor deflection IC
family.
• Subcontrast/contrast modulation
• Pedestal blanking
• Sync clipping.
3
ORDERING INFORMATION
TYPE
NUMBER
TDA4886
1998 Nov 11
PACKAGE
NAME
SDIP24
DESCRIPTION
plastic shrink dual in-line package; 24 leads (400 mil)
3
VERSION
SOT234-1
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
4
TDA4886
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VP
supply voltage (pin 7)
7.6
8.0
8.8
V
IP
supply current (pin 7)
−
21
25
mA
VP1,2,3
channel supply voltage (pins 21, 18 and 15)
7.6
8.0
8.8
V
IP1,2,3
channel supply current (pins 21, 18 and 15)
−
21
25
mA
Vi(b-w)
input voltage
(black-to-white value; pins 6, 8 and 10)
−
0.7
1.0
V
Vo(b-w)
nominal output voltage swing
(black-to-white value; pins 22, 19 and 16)
nominal contrast;
maximum gain
−
2.8
−
V
Vo(b-w)(max)
maximum output voltage swing
(black-to-white value; pins 22, 19 and 16)
maximum contrast;
maximum gain
−
4.54
−
V
Vo
output voltage level (pins 22, 19 and 16)
0.05
−
VP − 1 V
Vbl(DC)
typical reference black level for DC coupling control bit FPOL = 0
(pins 22, 19 and 16)
0.5
−
2.5
V
Vbl(AC)
typical reference black level for AC coupling control bit FPOL = 1 and
(pins 22, 19 and 16)
PEDST = 0
BLH2 = 0; BLH1 = 0
−
0.77
−
V
BLH2 = 0; BLH1 = 1
−
1.01
−
V
BLH2 = 1; BLH1 = 0
−
1.25
−
V
BLH2 = 1; BLH1 = 1
−
1.49
−
V
during fast signal transients −
−
20
mA
Io(sink)
peak output sink current
Io(source)
peak output source current
during fast signal transients −40
−
−
mA
B
bandwidth
−3 dB (small signal)
−
160
−
MHz
tr(o)
video rise time at signal outputs
(pins 22, 19 and 16)
−
3.2
−
ns
tf(o)
video fall time at signal outputs
(pins 22, 19 and 16)
−
4
−
ns
dVo
over/undershoot at signal outputs
(pins 22, 19 and 16)
minimum rise/fall time
−
−
10
%
αct(f)
crosstalk suppression by frequency
f = 50 MHz
25
−
−
dB
CC
contrast control related to nominal contrast
−28
−
+4.2
dB
TRo
tracking of output signals for contrast
variation from maximum to minimum
−
0.0
0.5
dB
GC
gain control related to maximum gain
−7.3
−
0
dB
BC
brightness control (typical black level
voltage change related to nominal output
signal amplitude)
−10
−
+30
%
−
120
−
%
−12
−
0
dB
Vo(OSD)(max) maximum OSD output voltage swing related maximum OSD contrast;
to nominal output voltage swing
maximum gain
(pins 22, 19 and 16)
COSD
1998 Nov 11
OSD contrast control related to maximum
OSD contrast
4
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6
LIM
VI1
PEDST
DISO
DISV
FPOL
BLH1
BLH2
24
6
6-BIT
DAC
I2C-BUS
6
4-BIT
DAC
6
6-BIT
DAC
6
6-BIT
DAC
6-BIT
DAC
6
8
6-BIT
DAC
8
8
SUBCONTRAST
CONTRAST MODULATION
LIMITING
BRIGHTNESS
BLANKING
CHANNEL 1
REFERENCE
FPOL
8-BIT
DAC
CHANNEL 2
REFERENCE
FPOL
8-BIT
DAC
CHANNEL 3
REFERENCE
FPOL
TDA4886
21
FPOL
OSD
CONTRAST
22
PEDESTAL
BLANKING
18
PEDST
8
CONTRAST
5
INPUT
CLAMPING
BLANKING
FPOL
19
20
15
FPOL
10
FPOL
OSD
CONTRAST
BRIGHTNESS
16
17
14
fast
blanking
FPOL
vertical
blanking
input clamping
INPUT CLAMPING
VERTICAL BLANKING
OSD INPUT
2
3
4
VP3
5
VO3
output
clamping
blanking
BLANKING
OUTPUT CLAMPING
11
BLH2
FB/R3
GNDX
BLH1
DISV
SUPPLY
7
9
MHB185
OSD1 OSD2 OSD3
CLI
Fig.1 Block diagram.
HFB
VP
GND
TDA4886
FBL
Product specification
1
FB/R2
PEDESTAL
BLANKING
PEDST
DISO
VO2
GAIN
CONTRAST
INPUT
CLAMPING
BLANKING
VP2
PEDESTAL
BLANKING
BRIGHTNESS
PEDST
VI3
FB/R1
GAIN
FPOL
OSD
CONTRAST
VO1
BRIGHTNESS
23
VI2
VP1
GAIN
CONTRAST
INPUT
CLAMPING
BLANKING
8-BIT
DAC
Philips Semiconductors
4
140 MHz video controller with I2C-bus
13
6
REGISTER
BLOCK DIAGRAM
12
5
dbook, full pagewidth
1998 Nov 11
SDA SCL
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
6
TDA4886
PINNING
SYMBOL
PIN
DESCRIPTION
FBL
1
fast blanking input for OSD insertion
OSD1
2
OSD input channel 1
OSD2
3
OSD input channel 2
OSD3
4
OSD input channel 3
CLI
5
input clamping; vertical blanking
input
VI1
6
signal input channel 1
VP
7
supply voltage
VI2
8
signal input channel 2
GND
9
ground
VI3
10
signal input channel 3
HFB
11
horizontal flyback input
(output clamping, blanking)
SDA
12
I2C-bus serial data input/output
SCL
13
I2C-bus clock input
GNDX
14
ground channels 1, 2 and 3
VP3
15
supply voltage channel 3
VO3
16
signal output channel 3
FB/R3
17
feedback input/reference voltage
output channel 3
VP2
18
supply voltage channel 2
VO2
19
signal output channel 2
FB/R2
20
feedback input/reference voltage
output channel 2
VP1
21
supply voltage channel 1
VO1
22
signal output channel 1
FB/R1
23
feedback input/reference voltage
output channel 1
LIM
24
subcontrast, contrast modulation,
beam current limiting input
1998 Nov 11
handbook, halfpage
24 LIM
FBL 1
OSD1 2
23 FB/R1
OSD2 3
22 VO1
OSD3 4
21 VP1
20 FB/R2
CLI 5
19 VO2
VI1 6
TDA4886
VP 7
18 VP2
VI2 8
17 FB/R3
GND 9
16 VO3
VI3 10
15 VP3
HFB 11
14 GNDX
SDA 12
13 SCL
MHB186
Fig.2 Pin configuration.
6
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
7
FUNCTIONAL DESCRIPTION
7.2.3
Gain control is used for white point adjustment (correction
for different voltage to light amplification of the three colour
channels) and therefore individual for the three channels.
The video signals related to the reference black level can
be gain controlled within a range of typically 7.3 dB.
The nominal setting is maximum gain. The video signal is
the addition of the contrast controlled input signal and the
brightness shift. The gain setting is also valid for OSD
signals, thus the complete ‘grey scale’ is effected by gain
control.
Signal input stage (input clamping, blanking
and clipping)
The RGB input signals with nominal signal amplitude of
0.7 V are capacitively coupled into the TDA4886 from a
low-ohmic source (75 Ω recommended) and actively
clamped to an internal DC voltage during signal black
level. Because of the high-ohmic input impedance of the
TDA4886 the coupling capacitor (which also functions as
a storage capacitor during clamping pulses) can be
relatively small (10 nF recommended). Very small input
currents will discharge the coupling capacitor resulting in
black output signals for missing input clamping pulses.
7.3
A fast signal blanking stage belongs to the input stage
which is driven by several blanking pulses (see Section
“Clamping and blanking pulses”) and control bit DISV = 1.
During the off condition the internal reference black level
will be inserted instead of the input signals.
7.2.1
7.4
Electronic potentiometer stages
CONTRAST CONTROL (DRIVEN BY I2C-BUS,
6-BIT DAC)
7.5
BRIGHTNESS CONTROL (DRIVEN BY I2C-BUS,
6-BIT DAC)
Output clamping, feedback references and
DAC outputs
The aim of the output clamping (pins FB/R1, FB/R2
and FB/R3 with control bit FPOL = 0, internal feedback
with control bit FPOL = 1) is to set the reference black level
of the signal outputs to a value which corresponds to the
‘extended cut-off voltage’ of the CRT cathodes. With a lack
of output clamping pulses the integrated storage
capacitors will be discharged resulting in output signals
going to switch-off voltage. Feedback references are
driven by the I2C-bus.
With brightness control the video black level will be shifted
in relation to the reference black level simultaneously for
all three channels. With a negative setting (maximum 10%
of nominal signal amplitude) dark signal parts will be lost in
ultra black while for positive settings (maximum 30% of
nominal signal amplitude) the background will alter from
black to grey. The nominal brightness setting (10H) is no
shift. The brightness setting is also valid for OSD signals.
During blanking and output clamping the video black level
will be blanked to reference black level (brightness
blanking).
1998 Nov 11
Pedestal blanking
For the video portion the reference black level should
correspond to the ‘extended cut-off voltage’ at the
cathode. Nevertheless during vertical flyback retrace lines
may be visible, though blanking to spot cut-off is useful.
With control bit PEDST = 1 the pedestal black level will be
adjusted by output clamping instead of the reference black
level (see Fig.5). The pedestal black level is more negative
than the video black level at minimum brightness setting
and the voltage difference to reference black level is fixed.
The input signals related to the internal reference black
level can be simultaneously adjusted by contrast control
with a control range of typically 32 dB. The nominal
contrast setting is defined for 26H (4.2 dB below
maximum).
7.2.2
Output stage
In the output stage the nominal input signal will be
amplified to 2.8 V output colour signal at nominal contrast
and maximum gain. The maximum input to output
amplification at maximum contrast and gain settings is
16.2 dB. By output clamping the reference black level
can be adjusted. In order to achieve fast rise and fall times
of the output signals with minimum crosstalk between the
channels, each output stage has its own supply voltage
pin.
Composite signals will not disturb normal operation
because a clipping circuit cuts all signal parts below
black level.
7.2
GAIN CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC)
AND GREY SCALE TRACKING
See block diagram (Fig.1) and definition of levels and
output signals (see Chapter “Characteristics” notes 1 to 3;
Figs 3 to 6).
7.1
TDA4886
7
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
During the vertical blanking pulse at pin CLI signal
blanking, brightness blanking and with control bit
PEDST = 1 pedestal blanking will be activated. Input
clamping pulses during vertical blanking will not switch off
blanking.
1. Control bit FPOL = 0
The cathode voltage (DC-coupled) is divided by a
voltage divider and fed back to the IC. During the
output clamping pulse it is compared with an
adjustable feedback reference voltage with a range of
approximately 5.77 to 4.05 V. Any difference will lead
to a reference black level correction (control bit
PEDST = 0) or pedestal black level correction (control
bit PEDST = 1) by charging or discharging the
integrated capacitor which stores the black level
information between the output clamping pulses.
The DC voltages of the output stages should be
designed in such a way that the reference black
level/pedestal black level is within the range of
0.5 to 2.5 V.
For proper input clamping the input signals have to be at
black level during the input clamping pulse.
An input pulse at pin HFB (e.g. horizontal flyback pulse)
will be scanned with two thresholds. If the input pulse
exceeds the first one (typical 1.4 V) signal blanking,
brightness blanking and if control bit PEDST = 1
pedestal blanking will be activated. If the input pulse
exceeds the second one (typical 3 V) additionally output
clamping will be activated. The vertical blanking pulse can
also be mixed with the horizontal flyback pulse at pin HFB.
For correct operation it is necessary that there is
enough headroom for ultra black signals (negative
brightness setting, pedestal black level if control bit
PEDST = 1). Any clipping with the video supply
voltage at the cathode can disturb the signal rise/fall
times or the black level stabilization.
7.7
For applications with AC-coupled cathodes the signal
outputs are fed back internally. During the output
clamping pulse they are compared with a feedback
reference voltage of approximately 0.75, 1.0, 1.25 or
1.5 V (depending on the values of control bits BLH2
and BLH1). These values ensure a good adaptability
to discrete and integrated post amplifiers as well.
For black level restoration the DAC outputs (FB/R1,
FB/R2 and FB/R3) with a range of approximately
5.77 to 4.05 V can be used.
With control bit DISO = 1 OSD, signal insertion and fast
blanking (pin FBL) are disabled.
The use of pedestal blanking allows a very simple
black level restoration with a DC diode clamp instead
of a complicated pulse restoration circuit because the
pedestal black level is the most negative output signal.
7.8
Subcontrast/contrast modulation and beam
current limiting
The pin LIM is a linear contrast control pin which allows
subcontrast setting, contrast modulation and beam current
limiting. The maximum contrast is defined by the actual
I2C-bus setting. Input signals at pin LIM act on video and
OSD signals and do not affect the contrast bit resolution.
Clamping and blanking pulses
The pin CLI of TDA4886 can be directly connected to
pin CLBL of e.g. TDA4855 sync processor for input
clamping pulses and vertical blanking pulses.
The threshold for the input clamping pulse (typical 3 V) is
higher than the threshold for the vertical blanking pulse
(typical 1.4 V) but there must be no blanking during input
clamping. Thus vertical blanking only is enabled if no input
clamping is detected. For this reason the input clamping
pulse must have rise/fall times faster than 75 ns/V during
the transition from 1.2 to 3.5 V and vice versa. The internal
vertical blanking pulse will be delayed by typical 270 ns.
1998 Nov 11
On Screen Display (OSD)
If the fast blanking input signal at pin FBL exceeds the
threshold (typical 1.4 V) the input signals are blanked
(signal blanking) and OSD signals are enabled. Then any
signal at pins OSD1, OSD2 or OSD3 exceeding the same
threshold will create an insertion signal with an amplitude
of 120% of the nominal colour signal (approximately 74%
of the maximum colour signal). The amplitude can be
controlled by OSD contrast (driven by the I2C-bus) with a
range of 12 dB. The OSD signals are inserted at the same
point as the contrast controlled input signals and will be
treated with brightness and gain control like normal input
signals.
2. Control bit FPOL = 1
7.6
TDA4886
To achieve brightness uniformity over the screen, scan
dependent contrast modulation is possible.
8
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
2. Direct mode
I2C-bus control
7.9
Adjustments via the I2C-bus take effect immediately.
The TDA4886 contains an I2C-bus receiver for several
control functions:
a) Most significant bit (MSB) of subaddresses is set to
logic 0.
1. Contrast control with 6-bit DAC
b) Number of I2C-bus transmissions in direct mode is
unlimited.
2. Brightness control with 6-bit DAC
3. OSD contrast control with 4-bit DAC
c) Adjustments take effect directly at the end of each
I2C-bus transmission.
4. Gain control for each channel with 6-bit DAC
5. Internal feedback reference and external reference
voltage control for each channel with 8-bit DAC
d) Direct mode can be used for all adjustments but
large changes of control values may appear as
visual disturbances in the picture on the monitor.
6. Control register with control bits BLH2, BLH1, FPOL,
DISV, DISO and PEDST.
e) Auto-increment is possible.
After power-up and after internal power-on reset of the
I2C-bus the registers are set to the following values:
f) Vertical blanking pulse is not necessary.
• Control bit FPOL to logic 1
• Control bits BLH2, BLH1, DISV, DISO and PEDST to
logic 0
• All other alignment registers to logic 0 (minimum value
for control registers).
7.10
I2C-bus data buffer
1. Buffered mode
Adjustments via the I2C-bus are synchronized with
vertical blanking pulse at CLI.
a) Most significant bit (MSB) of subaddresses is set to
logic 1.
b) Only one I2C-bus transmission in buffered mode is
accepted before the start of the vertical blanking
pulse. Following transmission trials will get no
acknowledge.
c) Received data is stored in one internal 8-bit buffer.
d) Adjustments will take effect with detection of the
first vertical blanking pulse after the end of
according I2C-bus transmission.
e) Waiting for vertical blanking pulse in buffered mode
can be interrupted by power-on reset.
f) Auto-increment is impossible.
g) Buffered mode should be used for user
adjustments such as contrast, OSD contrast and
brightness while picture on monitor is visible.
1998 Nov 11
TDA4886
9
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VP
supply voltage (pin 7)
0
8.8
V
VP1, 2, 3
supply voltage channels 1, 2 and 3 (pins 21,
18 and 15)
0
8.8
V
Vi
input voltage (pins 6, 8 and 10)
−0.1
VP
V
Vext
external DC voltage applied to the following pins:
pins 1 to 4
−0.1
VP
V
pins 5 and 11
−0.1
VP + 0.7
V
pins 12 and 13
−0.1
VP
V
pins 23, 20 and 17
−0.1
VP + 0.7
V
pins 22, 19 and 16
note 1
note 1
pin 24
−0.1
VP
V
Io(av)
average output current (pins 22, 19 and 16)
−
20
mA
IOM
peak output current (pins 22, 19 and 16)
−
50
mA
Ptot
total power dissipation
−
1400
mW
Tstg
storage temperature
−25
+150
°C
Tamb
operating ambient temperature
−20
+70
°C
Tj
junction temperature
−25
+150
°C
VESD
electrostatic handling for all pins
machine model
note 2
−250
+250
V
human body model
note 3
−2000
+2000
V
Notes
1. No external voltages.
2. Equivalent to discharging a 200 pF capacitor via a 0.75 µH inductance (“UZW-B0/FQ-B302” ).
3. Equivalent to discharging a 100 pF capacitor via a 1500 Ω series resistor (“UZW-B0/FQ-A302” ).
9
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1998 Nov 11
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
10
in free air
VALUE
UNIT
55
K/W
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
10 CHARACTERISTICS
All voltages and currents are measured in a dedicated test circuit which is optimized for best high frequency
performance; all voltages are measured with respect to GND (pins 9 and 14); VP = VP1, 2, 3 = 8 V (pins 7, 21,
18 and 15); Tamb = 25 °C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; nominal colour signals at signal
outputs (pins 22, 19 and 16); reference black level (Vrbl) approximately 0.77 V; nominal settings for brightness and
contrast; maximum settings for OSD contrast and gain; no subcontrast, modulation of contrast or limiting (V24 ≥ 5 V); no
OSD fast blanking (pin 1 connected to ground); notes 1 to 3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VP
supply voltage (pin 7)
IP
supply current (pin 7)
VP1,2,3
channel supply voltage
(pins 21, 18 and 15)
IP1,2,3
channel supply current
(pins 21, 18 and 15)
VPSO
supply voltage for signal switch signal outputs switched to
off (threshold at pin 7)
switch-off voltage
note 4
signal outputs (pins 22,
19 and 16) open-circuit;
Vrbl ≈ 0.77 V; notes 4 and 5
7.6
8.0
8.8
V
−
21
25
mA
7.6
8.0
8.8
V
−
21
25
mA
−
−
7.2
V
Input clamping and vertical blanking input, validation of buffered I2C-bus data (pin 5)
V5
I5
input clamping and vertical
blanking input signal
input current
notes 6 and 7
no vertical blanking,
no input clamping
−0.1
−
+1.2
V
vertical blanking,
no input clamping
1.6
−
2.6
V
input clamping,
no vertical blanking
3.5
−
VP
V
V5 = 1 V
−
−0.2
−
µA
pin 5 connected to ground;
note 8
−80
−60
−30
µA
V5 = −0.1 V; note 8
−250
−200 −100
µA
note 6; see Fig.7
−
−
75
ns/V
0.6
−
−
µs
tr/f5
rise/fall time for input clamping
pulse, disable for vertical
blanking
tW5
width of input clamping pulse
tW5I2C
width of vertical blanking pulse
for validation of buffered
I2C-bus data
leading and trailing edge
threshold V5 = 1.4 V; note 7
10
−
−
µs
tI2Cvalid
delay between leading edge of
vertical blanking pulse and
validation of buffered I2C-bus
data
I2C-bus transmission in
buffered mode completed;
leading edge threshold
V5 = 1.4 V; note 7
−
−
2
µs
tI2Cdead
dead time of I2C-bus receiver
after synchronizing vertical
blanking pulse in case of a
completed I2C-bus
transmission in buffered mode
leading edge threshold
V5 = 1.4 V; note 7
15
−
−
µs
1998 Nov 11
11
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
SYMBOL
PARAMETER
TDA4886
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tdl5
delay between leading edges
of vertical blanking input pulse
and signal blanking at signal
outputs
V11 < 0.8 V; input pulse with
50 ns/V; threshold for rising
input pulse V5 = 1.4 V;
threshold after input clamping
pulse V5 = 3 V; VI(b-w) = 0.7 V;
see Fig.7
−
270
−
ns
tdt5
delay between trailing edges of V11 < 0.8 V; input pulse with
vertical blanking input pulse
50 ns/V; threshold V5 = 1.4 V;
see Fig.7
and internal blanking pulse
−
115
−
ns
no blanking,
no output clamping
−0.1
−
+0.8
V
blanking, no output clamping
2.0
−
2.6
V
Output clamping and blanking input (pin 11)
V11
output clamping and blanking
input signal
note 9
3.5
−
VP
V
V11 = 0.8 V
−
−0.4
−
µA
pin 11 connected to ground;
note 8
−80
−60
−30
µA
blanking, output clamping
I11
tW11
input current
width of output clamping pulse
V11 = −0.1 V; note 8
−250
−200 −100
µA
threshold V11 = 3 V
1
−
−
µs
−
0.7
1.0
V
no input clamping;
VI6,8,10 = VI(clamp)6, 8, 10;
Tamb = −20 to +70 °C
0.02
0.20
0.35
µA
during input clamping;
VI6,8,10 = VI(clamp)6,8,10 ±0.7 V
±100
±135 ±170
µA
control bit DISV = 1; f = 80 MHz 20
−
−
dB
control bit DISV = 1;
f = 120 MHz
10
−
−
dB
−
−
2
%
−
4.2
−
dB
−
0
−
dB
00H (minimum)
−
−28
−
dB
3FH to 00H; note 12
−
0.0
0.5
dB
Video signal inputs (channel 1: pin 6; channel 2: pin 8; channel 3: pin 10)
Vi(b-w)6,8,10
positive input signal referred to
black
II6,8,10
DC input current
Signal blanking
αct(blank)
crosstalk suppression from
input to output during blanking
Clipping of negative input signals (measured at signal outputs)
∆Vclipp
offset during sync clipping
VI6,8,10 = VI(clamp)6,8,10; note 10;
related to nominal colour signal see Fig.3
Contrast control; see Fig.8 and note 11
dC
∆Gtrack
1998 Nov 11
colour signal related to nominal 3FH (maximum)
colour signal
26H (nominal)
tracking of output colour
signals of channels 1, 2 and 3
12
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
SYMBOL
PARAMETER
TDA4886
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fast blanking (pin 1) and OSD signal insertion (channel 1: pin 2; channel 2: pin 3; channel 3: pin 4); note 13
V1
V2,3,4
fast blanking input signal
OSD input signal
no video signal blanking,
OSD signal insertion disabled
0
−
1.1
V
video signal blanking,
OSD signal insertion enabled
1.7
−
VP
V
no internal OSD signal
insertion
0
−
1.1
V
internal OSD signal insertion
1.7
−
VP
V
V1 > 1.7 V
tr(OSD)
rise time of OSD colour signals
(pins 22, 19 and 16)
10 to 90% amplitude;
input pulse with 1.2 ns/V
−
−
4
ns
tf(OSD)
fall time of OSD colour signals
(pins 22, 19 and 16)
90 to 10% amplitude;
input pulse with 1.2 ns/V
−
−
7
ns
tg(CO)
width of (negative going) OSD
signal insertion glitch, leading
edge (pins 22, 19 and 16)
identical pulses at fast blanking
input (pin 1) and OSD signal
inputs (pins 2, 3 and 4)
0
−
6
ns
tg(OC)
width of (negative going) OSD
signal insertion glitch, trailing
edge (pins 22, 19 and 16)
identical pulses at fast blanking
input (pin 1) and OSD signal
inputs (pins 2, 3 and 4)
0
−
6
ns
dVOSD
overshoot/undershoot of OSD
colour signal related to actual
OSD output pulse amplitude
(pins 22, 19 and 16)
pulse with 1.2 ns/V at OSD
signal inputs (pins 2, 3 and 4)
−
−
10
%
VOSD(max)
maximum OSD colour signal
maximum OSD contrast;
related to nominal colour signal maximum gain
(pins 22, 19 and 16)
100
120
140
%
0FH (maximum)
−
0
−
dB
00H (minimum)
−14
−12
−10
dB
OSD contrast control; see Fig.9 and note 14
dOC
OSD colour signal related to
maximum OSD colour signal
Subcontrast/contrast modulation and beam current limiting (pin 24); see Fig.8 and note 15
V24(nom)
nominal input voltage
V24(start)
starting voltage for contrast
and OSD contrast reduction
V24(stop)
stop voltage for contrast and
OSD contrast reduction
B24
I24(max)
pin 24 open-circuit
4.7
5.0
5.3
V
4.2
4.5
4.8
V
−32 dB below maximum colour
signal (contrast setting 3FH)
1.5
2.0
2.5
V
bandwidth of contrast
modulation
−3 dB
4
−
−
MHz
maximum input current
V24 = 0 V
−1.0
−
−
µA
3FH (maximum)
25
30
35
%
10H (nominal)
−
0
−
%
00H (minimum)
−12
−10
−8
%
Brightness control; see Fig.10 and notes 16 and 17
∆Vbl
1998 Nov 11
difference between black level
and reference black level at
signal outputs related to
nominal colour signal
13
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
SYMBOL
PARAMETER
TDA4886
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Gain control; see Fig.11 and note 18
dG
video signal related to video
signal at maximum gain
3FH (maximum)
−
0
−
dB
00H (minimum)
−8.3
−7.3
−6.3
dB
note 19; see Fig.5
−18
−16
−14
%
Pedestal blanking
∆V22,19,16(PED)
difference from pedestal black
level to video black level at
nominal brightness, measured
at signal output pins related to
nominal colour signal
Signal outputs (channel 1: pin 22; channel 2: pin 19; channel 3: pin 16)
V22,19,16(nom)
nominal colour signal
nominal contrast; maximum
gain; Vi(b-w) = 0.7 V; without
load
2.5
2.8
3.1
V
V22,19,16(max)
maximum colour signal
maximum contrast; maximum
gain; Vi(b-w) = 0.7 V; without
load
4.1
4.54
5
V
V22,19,16(min)
switch-off voltage
(minimum output voltage level)
−
0.05
0.1
V
V22,19,16(top)
maximum output voltage level
VP − 2
−
VP − 1
V
R(o)22,19,16
output resistance
−
75
−
Ω
I22,19,16(source)
maximum source current
−15
−
−
mA
at arbitrary input signals,
contrast, brightness and gain
adjustments; without load
I22,19,16(M)(source) peak source current
during fast positive signal
transients
−40
−
−
mA
I22,19,16(sink)
output voltage
V22,19,16 ≈ 0.77 V; note 20
3.2
4
−
mA
output voltage V22,19,16 = 6 V;
note 20
1.6
2
−
mA
maximum sink current
(built-in current source)
I22,19,16(M)(sink)
peak sink current
during fast negative signal
transients
−
−
20
mA
S/N
signal-to-noise ratio
note 21
44
−
−
dB
D22,19,16(th)
output thermal distortion
note 22
−
−
0.6
%
1998 Nov 11
14
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
SYMBOL
PARAMETER
TDA4886
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Frequency response at signal outputs (channel 1: pin 22; channel 2: pin 19; channel 3: pin 16)
∆G22,19,16(f)
amplification decrease by
frequency response
f = 160 MHz;
Vi(b-w) ≤ 0.2 V (small signal)
−
1.2
3.0
dB
tr(22,19,16)
rise time of fast transients
input rise time = 1 ns;
10 to 90% amplitude;
nominal colour signal; note 23
−
3.2
3.5
ns
tf(22,19,16)
fall time of fast transients
input fall time = 1 ns;
90 to 10% amplitude;
nominal colour signal; note 23
−
4.0
4.3
ns
dV22,19,16
over/undershoot of output
signal pulse related to actual
output pulse amplitude
input rise/fall time = 1 ns;
nominal colour signal
−
−
10
%
Crosstalk at signal outputs (channel 1: pin 22; channel 2: pin 19; channel 3: pin 16)
αct(tr)
transient crosstalk suppression input rise/fall time = 1 ns;
note 24
10
−
−
dB
αct(f)
crosstalk suppression by
frequency
f = 50 MHz
25
−
−
dB
f = 100 MHz
10
−
−
dB
Internal feedback reference voltage; see Fig.12 and note 25
Vref(n)
Vref(p)
internal reference voltage for
negative feedback polarity
FFH (minimum); FPOL = 0
3.85
4.05
4.2
V
00H (maximum); FPOL = 0
5.6
5.77
5.9
V
internal reference voltage for
positive feedback polarity
FPOL = 1
BLH2 = 0; BLH1 = 0
0.71
0.77
0.83
V
BLH2 = 0; BLH1 = 1
0.95
1.01
1.07
V
BLH2 = 1; BLH1 = 0
1.19
1.25
1.31
V
BLH2 = 1; BLH1 = 1
1.43
1.49
1.55
V
Output clamping, feedback inputs for DC coupling (channel 1: pin 23; channel 2: pin 20; channel 3: pin 17)
I23,20,17(max)
maximum input current
during output clamping;
V11 > 3.5 V; V23,20,17 = 0.5 V;
FPOL = 0
−500
−200 −60
nA
V22,19,16(rbl)(min)
minimum reference black level
PEDST = 0; V11 > 3.5 V;
FPOL = 0
0.01
0.1
0.5
V
minimum pedestal black level
PEDST = 1; V11 > 3.5 V;
FPOL = 0
0.01
0.1
0.5
V
maximum reference black level PEDST = 0; V11 > 3.5 V;
FPOL = 0
2.4
2.8
−
V
maximum pedestal black level
PEDST = 1; V11 > 3.5 V;
FPOL = 0
2.4
2.8
−
V
∆Vbl(CRT)
black level variation at CRT
FPOL = 0; note 26
−
−
200
mV
∆V22,19,16(bl)(lf)
black level variation between
clamping pulses related to
nominal colour signal
FPOL = 0;
line frequency = 60 kHz;
10% duty cycle
−
0.25
0.5
%
V22,19,16(rbl)(max)
1998 Nov 11
15
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
SYMBOL
PARAMETER
TDA4886
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Output clamping for AC coupling (internal feedback of signal outputs)
V22,19,16(rbl)
reference black level
pedestal black level
V11 > 3.5 V; FPOL = 1;
PEDST = 0
BLH2 = 0; BLH1 = 0
0.71
0.77
0.83
V
BLH2 = 0; BLH1 = 1
0.95
1.01
1.07
V
BLH2 = 1; BLH1 = 0
1.19
1.25
1.31
V
BLH2 = 1; BLH1 = 1
1.43
1.49
1.55
V
BLH2 = 0; BLH1 = 0
0.71
0.77
0.83
V
BLH2 = 0; BLH1 = 1
0.95
1.01
1.07
V
BLH2 = 1; BLH1 = 0
1.19
1.25
1.31
V
V11 > 3.5 V; FPOL = 1;
PEDST = 1
BLH2 = 1; BLH1 = 1
∆V22,19,16(bl)(lf)
black level variation between
clamping pulses related to
nominal colour signal
FPOL = 1;
line frequency = 60 kHz;
10% duty cycle
1.43
1.49
1.55
V
−
0.25
0.5
%
External reference voltages for AC coupling (FB/R1: pin 23; FB/R2: pin 20; FB/R3: pin 17); see Fig.13 and
note 27
V23,20,17
external reference voltage
FFH (minimum); FPOL = 1
3.85
4.05
4.2
V
00H (maximum); FPOL = 1
5.6
5.77
5.9
V
R23,20,17
output resistance
FPOL = 1
−
100
−
Ω
I23,20,17(sink)
maximum sink current
FPOL = 1
−
−
400
µA
I23,20,17(source)
maximum source current
FPOL = 1
−
−330 −280
µA
I2C-bus inputs (SDA: pin 12; SCL: pin 13); note 28
fSCL
SCL clock frequency
−
−
100
kHz
VIL
LOW-level input voltage
0.0
−
1.5
V
VIH
HIGH-level input voltage
3.0
−
5.0
V
IIL
LOW-level input current
VIL = 0 V
−10
−
−
µA
IIH
HIGH-level input current
VIH = 5 V
−10
−
−
µA
VOL
LOW-level output voltage
during acknowledge
0.0
−
0.4
V
I12(ack)
output current at pin 12 during
acknowledge
VOL = 0.4 V
3.0
−
5.0
mA
Vth(POR)(r)
threshold for power-on reset on rising supply voltage
−
1.5
2.0
V
falling supply voltage
−
3.5
−
V
Vth(POR)(f)
threshold for power-on reset off rising supply voltage
−
−
7.0
V
falling supply voltage
−
1.5
−
V
1998 Nov 11
16
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
Notes to the characteristics
1. Definition of levels (see Figs 3 to 5)
Reference black level: this is the level to which the input level is clamped during the input clamping pulse
(V5 > 3.5 V). It is used internally as a reference for the gain settings. It can be observed on the outputs:
a) When the input is at black and the brightness setting is nominal (subaddress 01H = 10H)
b) During output blanking/clamping (V11 > 3.5 V) if control bit PEDST = 0.
Video black level: this is the black level of the actual video. On the input it is still equal to the reference black level.
On the output it may deviate from it according to the brightness setting. Contrast setting leaves the video black level
unaltered . Gain setting biases the video black level due to its influence on brightness. This is important for correct
grey scale tracking.
Pedestal black level: this is an ultra black level which deviates from reference black level by a fixed amount. It can
be observed on the output during output blanking/clamping (V11 > 3.5 V) if control bit PEDST = 1.
Switch-off voltage: this is the lowest signal voltage at outputs. The signals will be switched off by discharging the
internal black level storage capacitors if the supply voltage is less than VPSO.
Blanking level: this level equals reference black (control bit PEDST = 0) or pedestal black (control bit PEDST = 1).
2. Explanation to black level adjustment:
The three reference black levels are aligned correctly when they are made equal to the ‘extended cut-off levels’ of
the three cathodes. Full raster and spot cut-off can only be achieved by enabling the pedestal blanking or by applying
a negative pulse to the control grid G1.
Negative feedback for DC-coupled cathodes (control bit FPOL = 0): the actual blanking level on the outputs
depends on the external feedback application for output clamping. The loop will function correctly only if it is within
the control range of V22,19,16(rbl)(min) to V22,19,16(rbl)(max). It should be noted that changing control bit PEDST in a given
application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three black
levels).
Positive feedback for AC-coupled cathodes (control bit FPOL = 1): the feedback loop for output clamping is
closed internally. The actual blanking level at the outputs depends on control bits BLH2 and BLH1 only. Four discrete
blanking levels between approximately 0.75 and 1.5 V can be chosen. It should be noted that changing control bit
PEDST will not affect the blanking level selected by control bits BLH2 and BLH1, but instead shifts the video (and
needs re-alignment of the three black levels).
3. Definition of output signals (see Fig.6):
Colour signal: all positive voltages referred to black level at signal outputs.
Nominal colour signal: colour signal with nominal input signal (0.7 Vb-w), nominal contrast setting and maximum
gain setting.
Video signal: all positive voltages referred to reference black level at signal outputs. The video signal is the
superimposing of the brightness information (∆Vbl) and the colour signal.
4. The total supply current IP = I7 + I21 + I18 + I15 depends on the supply voltage with a factor of approximately 4.4 mA/V
and varies in the temperature range from −20 to +70 °C by approximately ±5% (V22,19,16 = 0.77 V).
5. The channel supply current depends on the signal output current, the channel supply voltage and the signal output
voltage. With Ipx = I21,18,15 at VP1,2,3 = 8 V and V22,19,16 = 0.77 V:
mA
mA
I 21,18,15 ≈ I px + I 22,19,16 + 4.4 --------- × ( V P1,2,3 – 8 V ) – 1 --------- × ( V 22, 19, 16 – 0.77 V )
V
V
1998 Nov 11
17
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and
if control bit PEDST = 1 pedestal blanking). With a fast clamping pulse (transition between V5 = 1.2 to 3.5 V and vice
versa in less than 75 ns/V) no blanking will occur during input clamping.
For 75 ns/V < tr/f5 ≤ 280 ns/V the generation of the internal vertical blanking pulse is uncertain. For tr/f5 > 280 ns/V
the internal blanking pulse will be generated.
Pin 5 open-circuited will activate permanent input clamping and undefined blanking.
7. Pin 5 can be used to synchronize all adjustments via the I2C-bus (one by one). In case of a completed I2C-bus
transmission in buffered mode only the leading edge of a vertical blanking pulse activates an adjustment. See also
Section 7.10.
After the adjustment has been activated (validation of buffered I2C-bus data) the I2C-bus will be reset and further
transmissions in direct or buffered mode are enabled.
I2C-bus transmissions in direct mode need no synchronization pulses.
8. Input voltages less than −0.1 V can produce internal substrate currents which disturb the leakage currents at the
signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or less. Feeding
clamping/blanking pulses via a resistor of some kΩ protects the pin from negative voltages.
9. Pin 11 should be used for output clamping and/or blanking. Pin 11 open-circuited will activate permanent blanking
and output clamping.
10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below
input reference black level (see Fig.3).
11. Contrast control acts on internal colour signals under I2C-bus control; subaddress 02H (bit resolution 1.6% of
contrast range).

 A 1 A 20 
 A 1 A 30 
 A 2 A 30  
12. ∆G track = 20 × maximum of  log  --------- × ---------  ; log  --------- × ---------  ; log  --------- × ---------   dB
 A 10 A 2 
 A 10 A 3 
 A 20 A 3  

An: colour signal output amplitude in channel n = 1, 2 or 3 at any contrast setting.
An0: colour signal output amplitude in channel n = 1, 2 or 3 at nominal contrast setting and same gain setting.
13. When OSD fast blanking is active and V2,3,4 are HIGH (V1 > 1.7 V, V2,3,4 > 1.7 V) the OSD colour signals will be
inserted in front of the gain potentiometers. This assures a correct grey scale of all video signals. The amplitudes of
the inserted OSD signals can be controlled simultaneously by OSD contrast via the I2C-bus.
14. OSD contrast control acts on inserted OSD colour signals under I2C-bus control; subaddress 03H (bit resolution
6.7% of OSD contrast range).
15. This pin can be used for subcontrast setting, beam current limiting and contrast modulation. Both the video and OSD
contrast are reduced simultaneously (see Figs 8 and 9). Because of the high-ohmic input impedance the pin should
be tied to a voltage of more than 5 V or applied with a capacitor of some nF if not used.
16. Brightness control adds an I2C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution
1.6% of brightness range).
17. The voltage difference between video black level and reference black level is related to the colour signal (see note 3)
with nominal 0.7 V (p-p) input signal, at nominal contrast (subaddress 02H = 26H) and for any gain setting.
The voltage difference (in Volts) is proportional to the gain setting (grey scale tracking). Therefore ∆Vbl (in percent)
is constant for any gain setting. The given values of ∆Vbl are valid only for video black levels higher than the signal
output switch-off voltage V22,19,16(min).
18. Gain control acts on video signals and inserted OSD video signals under I2C-bus control; subaddress 04H
(channel 1), 05H (channel 2) and 06H (channel 3; bit resolution 1.6% of gain range respectively).
1998 Nov 11
18
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
19. Pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative
signal at the signal output pins. The reference black level which should correspond to the ‘extended cut-off voltage’
at the cathodes is approximately ∆V22,19,16(PED) higher (see Fig.5). The use of pedestal blanking with AC-coupled
cathodes (control bit FPOL = 1) allows a very simple black level restoration with a DC diode clamp instead of a
complicated pulse restoration circuit.
20. DC load currents of signal outputs must not exceed maximum sink currents, otherwise signal distortions may occur.
21. The signal-to-noise ratio is calculated by the formula (range 1 to 120 MHz):
peak-to-peak value of the nominal signal output voltage
S
---- = 20 × log --------------------------------------------------------------------------------------------------------------------------------------------------- dB
RMS value of the noise output voltage
N
22. Large output currents e.g. I22,19,16(M)(source) lead to signal depending power dissipation in output transistors. Thermal
VBE variation is compensated.
23. Following formula can be used to approximately determine the output rise/fall time for any other input rise/fall time:
2
2
2
 2
t r/f, measured = t r/f (22,19,16) +  t r/f, input – ( 1ns ) 
24. Transient crosstalk between any two output pins:
a) Input conditions: any channel (channel A) with nominal input signal and 1 ns rise time. The inputs of the other
two channels are capacitively coupled to ground (channel B). Gain setting to maximum (3FH). Contrast setting to
nominal (26H). No limiting/modulation of contrast (V24 ≥ 5 V)
b) Output conditions: black level set to approximately 0.77 V for each channel at signal outputs. Output signals
are VA and VB respectively
VA
c) Transient crosstalk suppression: α ct(tr) = 20 × log ------- dB
VB
25. The internal feedback reference voltages are not influenced by the value of control bit PEDST but depend on the
individual adjustments via the I2C-bus, the selected feedback polarity (control bit FPOL = 0 or 1) and the selected
black level for positive feedback polarity (control bit FPOL = 1 and control bits BLH2 = 0 or 1 and BLH1 = 0 or 1):
Control bit FPOL = 0: the internal feedback reference voltage acts under I2C-bus control; subaddress 07H
(channel 1), 08H (channel 2) and 09H (channel 3; bit resolution 0.4% of voltage range). Rising values of the data
bytes, e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs
(pins 22, 19 and 16). The internal feedback reference voltages can be measured at feedback inputs
(pins 23, 20 and 17) during output clamping (V11 > 3.5 V) in closed feedback loop. The feedback loop remains
operative at reference black levels between the specified values of V22,19,16(rbl)(min) and V22,19,16(rbl)(max).
Control bit FPOL = 1: the internal feedback reference voltage can be measured at signal outputs
(pins 22, 19 and 16) during output clamping (V11 > 3.5 V). By means of control bits BLH2 and BLH1 it is possible to
choose one of the four specified values between approximately 0.75 and 1.5 V. This facilitates the adaption to
different kinds of post amplifiers.
26. Slow variations of video supply voltage VCRT will be suppressed at the CRT cathode by the clamping feedback loop.
A change of VCRT with 5 V leads to a specified change of the cathode voltage.
27. The external reference voltages act under I2C-bus control for control bit FPOL = 1; subaddress 07H (FB/R1), 08H
(FB/R2) and 09H (FB/R3; bit resolution 0.4% of voltage range).
28. All adjustments via the I2C-bus can be synchronized with vertical blanking pulse at pin CLI. This is called I2C-bus
transmission in buffered mode. The adjustments via the I2C-bus will take effect immediately in the so called direct
mode.
The timing of I2C-bus transmissions in buffered mode is related to the vertical blanking. See specification of pin 5
(vertical blanking input) and note 7.
1998 Nov 11
19
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
handbook, full pagewidth
TDA4886
input signals
input video signal
with syncs
at pins 6, 8 and 10
input reference
black level
the syncs will be clipped
to reference black level
internally
input clamping pulses
at pin 5
blanking/output
clamping pulses
at pin 11
MHA344
The input video signals have to be on black level during input clamping.
Fig.3 Input signals.
1998 Nov 11
20
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
handbook, full pagewidth
blanking pulse,
output clamping pulse
at pin 11
blanking signal
output signals
pins 22, 19 and 16
(1)
maximum gain setting,
nominal contrast setting,
maximum/nominal/minimum
brightness setting
(2)
(3)
video black levels at
maximum brightness
nominal brightness
minimum brightness
reference black level
switch-off voltage
ground
(1)
(2)
maximum gain setting,
maximum brightness setting,
maximum/nominal/minimum
contrast setting
(3)
video black level
(maximum brightness)
reference black level
switch-off voltage
ground
maximum brightness setting,
nominal contrast setting,
maximum/minimum
gain setting
(1)
(3)
video black level
(maximum brightness)
reference black level
switch-off voltage
ground
MHB187
(1) Maximum.
(2) Nominal.
(3) Minimum.
Fig.4
Definition of levels, function of brightness setting, contrast setting, gain setting, no pedestal blanking
(PEDST = 0).
1998 Nov 11
21
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
handbook, full pagewidth
blanking pulse,
output clamping pulse
at pin 11
blanking signal
output signals
pins 22, 19 and 16
PEDST = 0
no pedestal blanking
(1)
maximum gain setting,
nominal contrast setting,
maximum/minimum
brightness setting
(2)
video black levels at
maximum brightness
minimum brightness
reference black level
switch-off voltage
ground
PEDST = 1
pedestal blanking
(1)
maximum gain setting,
nominal contrast setting,
maximum/minimum
brightness setting
(2)
video black levels at
maximum brightness
minimum brightness
reference black level
pedestal black level
switch-off voltage
ground
MHB188
(1) Maximum.
(2) Minimum.
Fig.5 Output signals without (PEDST = 0) and with pedestal blanking (PEDST = 1).
1998 Nov 11
22
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
handbook,
full pagewidth
output
signals
pins 22, 19 and 16
PEDST = 0
no pedestal blanking
colour signals
video signals
maximum gain setting,
nominal contrast setting,
maximum/minimum
brightness setting
reference black level
video black levels at
maximum brightness
minimum brightness
MHB189
Fig.6 Definition of output signals.
handbook, full pagewidth
3V
trf5 ≤ 75 ns/V
input pulses at pin 5
1.4 V
internal pulse for
input clamping
tdl5
tdt5
internal pulse for
vertical blanking
MHB190
Fig.7 Timing of pulses at pin 5 and derived internal pulses.
1998 Nov 11
tdl5
23
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
handbook, full pagewidth
TDA4886
MHB191
4.2
colour signal
amplitude
related to
nominal colour
signal amplitude
(dB)
(1)
0
(2)
(3)
−28
10H
00H
20H
26H
3FH
30H
contrast control data byte
(1) No contrast reduction by subcontrast.
(2) Partial contrast reduction by subcontrast.
(3) Full contrast reduction by subcontrast.
Fig.8 Contrast control characteristic with subcontrast (equal to contrast modulation and limiting).
handbook, full pagewidth
160
OSD signal
amplitude
related to
nominal colour
signal amplitude
(%)
125
100
maximum colour signal amplitude
MHA351
maximum OSD signal amplitude
nominal colour signal amplitude
(1)
(2)
30
00H
(3)
0FH
OSD contrast control data byte
(1) No OSD contrast reduction by subcontrast.
(2) Partial OSD contrast reduction by subcontrast.
(3) Full OSD contrast reduction by subcontrast.
Fig.9 OSD contrast control characteristic with subcontrast (equal to contrast modulation and limiting).
1998 Nov 11
24
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
MHA352
handbook, full pagewidth
30
difference of
video black level
and reference
black level
related to
nominal colour
signal amplitude
(1)
(%)
0
(2)
−10
00H
10H
20H
3FH
30H
brightness control data byte
(1) Nominal adjustment.
(2) Nominal brightness reference black level.
Fig.10 Brightness control characteristic.
MHA353
handbook, full pagewidth
100
video signal gain
related to
maximum video
signal gain
(%)
45
0
00H
10H
20H
3FH
30H
gain control data byte
Fig.11 Gain control characteristic.
1998 Nov 11
25
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
handbook, full pagewidth
TDA4886
MHB192
5.77
(1)
internal feedback
reference voltage
(V)
4.05
(2)
(3)
(4)
(5)
1.49
1.25
1.01
0.77
0
00H
20H
40H
60H
80H
A0H
C0H
E0H
FFH
feedback reference data byte
(1)
(2)
(3)
(4)
(5)
Control bit FPOL = 0.
Control bits FPOL = 1, BLH2 = 1, BLH1 = 1.
Control bits FPOL = 1, BLH2 = 1, BLH1 = 0.
Control bits FPOL = 1, BLH2 = 0, BLH1 = 1.
Control bits FPOL = 1, BLH2 = 0, BLH1 = 0.
Fig.12 Internal feedback reference voltages.
handbook, full pagewidth
MHB193
5.77
(1)
external
reference voltage
(V)
4.05
0
00H
20H
40H
60H
80H
A0H
C0H
E0H
feedback reference data byte
(1) Control bit FPOL = 1.
Fig.13 External feedback reference voltages.
1998 Nov 11
26
FFH
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
11 I2C-BUS PROTOCOL
Table 1
Slave address
A6(1)
A5(1)
A4(1)
A3(1)
A2(1)
A1(1)
A0(1)
W(2)
1
0
0
0
1
0
0
0
Notes
1. Address bit.
2. Write bit.
Table 2
Slave receiver format
S(1)
SLAVE ADDRESS A(2)
SUBADDRESS A(3)
DATA BYTE A(4)
P(5)
Notes
1. START condition.
2. A = acknowledge.
3. All subaddresses within the range 00H to 09H are automatically incremented. The subaddress counter wraps around
from 09H to 00H. For subaddresses within the range 80H to 8FH no auto-increment takes place. Subaddresses
outside the ranges 00H to 0FH and 80H to 8FH are acknowledged by the device but neither auto-increment nor any
other internal operation takes place.
4. Single data byte in case of no auto-increment of subaddresses. More than one data byte with auto-increment of
subaddresses.
5. STOP condition.
1998 Nov 11
27
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
Table 3
TDA4886
Subaddress byte format
SUBADDRESS(1)
FUNCTION
Control register
DIRECT
MODE
00H
SUBADDRESS BYTE
BUFFERED
S7(2) S6(2) S5(2) S4(2) S3(2) S2(2) S1(2) S0(2)
MODE
80H
B(3)
0
0
0
0
0
0
0
Brightness control
01H
81H
B(3)
0
0
0
0
0
0
1
Contrast control
02H
82H
B(3)
0
0
0
0
0
1
0
83H
B(3)
0
0
0
0
0
1
1
OSD contrast control
03H
Gain control channel 1
04H
84H
B(3)
0
0
0
0
1
0
0
Gain control channel 2
05H
85H
B(3)
0
0
0
0
1
0
1
86H
B(3)
0
0
0
0
1
1
0
Gain control channel 3
06H
Black level reference channel 1
07H
87H
B(3)
0
0
0
0
1
1
1
Black level reference channel 2
08H
88H
B(3)
0
0
0
1
0
0
0
89H
B(3)
0
0
0
1
0
0
1
Black level reference channel 3
09H
0AH to 0FH 8AH to 8FH not used
Notes
1. The most significant bit (MSB) of the subaddress enables an I2C-bus transmission in direct or in buffered mode
(see note 3). Subaddresses outside the ranges 00H to 0FH and 80H to 8FH are not used.
2. Subaddress bit.
3. Most significant bit of subaddress byte. I2C-bus transmission in direct mode: B = 0. I2C-bus transmission in
buffered mode: B = 1.
1998 Nov 11
28
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
Table 4
TDA4886
Subaddress and data byte format
SUBADDRESS(1)
FUNCTION
Control register
DATA BYTE(2)
DIRECT BUFFERED
D7(4) D6(4) D5(4)
MODE
MODE
00H
80H
X(5)
X(5)
X(5)
D4(4)
D3(4)
D2(4) D1(4)
D0(4)
BLH2 BLH1 FPOL DISV DISO PEDST
NOMINAL
VALUE(3)
08H
Brightness control
01H
81H
X(5)
A15
A14
A13
A12
A11
A10
10H
Contrast control
02H
82H
X(5)
X(5)
A25
A24
A23
A22
A21
A20
26H
X(5)
X(5)
X(5)
A33
A32
A31
A30
0FH
OSD contrast
control
03H
83H
X(5)
Gain control
channel 1
04H
84H
X(5)
X(5)
A45
A44
A43
A42
A41
A40
3FH
Gain control
channel 2
05H
85H
X(5)
X(5)
A55
A54
A53
A52
A51
A50
3FH
Gain control
channel 3
06H
86H
X(5)
X(5)
A65
A64
A63
A62
A61
A60
3FH
Black level
reference channel 1
07H
87H
A77
A76
A75
A74
A73
A72
A71
A70
−
Black level
reference channel 2
08H
88H
A87
A86
A85
A84
A83
A82
A81
A80
−
Black level
reference channel 3
09H
89H
A97
A96
A95
A94
A93
A92
A91
A90
−
Notes
1. See Table 3 (Subaddress byte format).
2. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0).
3. Under certain conditions the nominal values lead to nominal colour signals etc. (see note 3 of Chapter
“Characteristics”).
After power-up and after internal power-on reset of the I2C-bus the registers are set to the following values:
a) Control bit FPOL to logic 1.
b) Control bits BLH2, BLH1, DISV, DISO and PEDST to logic 0.
c) All other alignment registers to logic 0 (minimum value for control registers).
4. Data bit.
5. X means don’t care but for software compatibility with other video ICs with the same slave address, they are
preferably set to logic 0.
1998 Nov 11
29
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
Table 5
TDA4886
Control register
BIT
FUNCTION
PEDST = 0
no pedestal blanking
PEDST = 1
pedestal blanking enabled
DISO = 0
OSD signals enabled
DISO = 1
OSD signals disabled
DISV = 0
video signals enabled
DISV = 1
video signals disabled
FPOL = 0
negative feedback polarity; pins 23, 20 and 17 as external feedback inputs; no external
feedback reference voltages
FPOL = 1
positive feedback polarity; pins 23, 20 and 17 as external reference voltage outputs;
internal feedback of signal outputs
BLH2 = 0
BLH1 = 0
for positive feedback polarity only: internal feedback reference voltage switched to
approximately 0.75 V
BLH2 = 0
BLH1 = 1
for positive feedback polarity only: internal feedback reference voltage switched to
approximately 1.0 V
BLH2 = 1
BLH1 = 0
for positive feedback polarity only: internal feedback reference voltage switched to
approximately 1.25 V
BLH2 = 1
BLH1 = 1
for positive feedback polarity only: internal feedback reference voltage switched to
approximately 1.5 V
1998 Nov 11
30
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
handbook, full pagewidth
TDA4886
START
LOAD PRESET CONTROL BITS
FPOL
PEDST
DISV = 1
DISO = 1
BLH2
BLH1
load from program
ROM code or EEPROM
LOAD FACTORY SETTINGS
GAIN
(CHANNEL 1, 2, 3)
FEEDBACK REFERENCES
(CHANNEL 1, 2, 3)
load from EEPROM
LOAD USER PRESET VALUES
load from EEPROM
CONTRAST
BRIGHTNESS
OSD CONTRAST
DEFLECTION
CONTROL
IC LOCKED
no
yes
DISV = 0
DISO = 0
DISPLAY NEW MODE(1)
DISO = 1
USER INPUT
no
yes
DISO = 0
RESPONSE TO USER INPUTS(2)
(CONTRAST, BRIGHTNESS, OSD CONTRAST)
DISO = 1
(1) Only synchronized video should
be displayed. Each new mode
can be displayed by OSD.
(2) Data transmission should be
synchronized with vertical
blanking of the monitor.
DEFLECTION
CONTROL
IC LOCKED
no
DISV = 1
yes
Fig.14 I2C-bus control flow.
1998 Nov 11
31
MHB194
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
12 TEST AND APPLICATION INFORMATION
contrast modulation input
handbook, full pagewidth
limiting input
subcontrast setting
fast blanking
OSD
inputs
1
24
2
23
3
22
Application with integated
post amplifier, DC-coupled cathode
and negative feedback.
to cathode
90 V
4
21
5
20
BLACK LEVEL
RESTORATION
19
6
TDA4886
70 V
7
18
8
17
9
16
10
15
11
14
12
13
to cathode
Application with integated
post amplifier, AC-coupled cathode
and black level restoration cicuit.
90 V
Application with discrete
post amplifier, DC-coupled
cathode and negative
feedback.
to cathode
8V
pull-up
resistors
MHB195
5V
I2C-BUS
output clamping
blanking
input clamping
vertical blanking
Fig.15 Basic applications for different kinds of post amplifiers with DC or AC coupling.
1998 Nov 11
32
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
12.1
Test boards
For high frequency measurements a special test
application and printed-circuit board with only a few
external components is built. It utilizes the internal positive
feedback of the output signals during output clamping with
control bit FPOL = 1. Figure 16 shows the test application
circuit and Figs 17 and 18 show the layout and mounting
of the double-sided printed-circuit board. Most
components are of SMD type. Short HF loops and
minimum crosstalk between the channels and between
signal inputs and outputs are achieved by properly shaped
ground areas.
1998 Nov 11
33
TDA4886
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
1 kΩ
handbook, full pagewidth
5.6 Ω
FBL
FBL
50 Ω
OSD1
OSD1
50 Ω
1
24
2
23
LIM
FB/R1
FB/R1
solder pin
channel 1
OSD2
OSD2
50 Ω
50 Ω
VO1
4
21
50 Ω
5
20
100
nF
0.47 µF
(63 V)
FB/R2
solder pin
channel 2
VI1
VI1
6
5 kΩ
19
VO2
VO2
3.3
pF
TDA4886
VP
J1
0.47 µF
(63 V)
10 nF
100
nF
7
18
100
pF
VI2
8
17
100
nF
0.47 µF
(63 V)
FB/R3
FB/R3
solder pin
5 kΩ
channel 3
GND
J2
9
16
VO3
VO3
3.3
pF
10 nF
VI3
VI3
50
Ω 150 pF
10
kΩ
5.6 Ω
VP2
150
pF
VI2
50
Ω 150 pF
10
kΩ
FB/R2
10 nF
50
Ω 150 pF
3.3
pF
5.6 Ω
VP1
150
pF
CLI
CLI
22
1 kΩ
OSD3
OSD3
3
VO1
10
15
5.6 Ω
VP3
150
pF
5 kΩ
HFB
J3
11
14
12
13
10
kΩ
100
nF
0.47 µF
(63 V)
GNDX
HFB
50
Ω
150
pF
SDA
10
nF
SCL
10 nF
VPX
LIMAC
VP1 sense
50
Ω
10 kΩ
VP sense
10 kΩ
SDA
5V
VP
10 nF
GND
10 kΩ
VINDC
SCL
LIM
5V
MHB196
Fig.16 Test board utilizing internal positive feedback only (FPOL = 1).
1998 Nov 11
34
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
103
handbook, full pagewidth
81
CLI
OSD3
OSD2
OSD1
5.6 Ω
FBL
1 kΩ
50 Ω
50 Ω
50 Ω
50 Ω
10 nF
10 nF
VI2
VI3
100 nF
150 pF
5 kΩ
50 Ω
150 pF
5 kΩ
J1
J2
+
100
nF
150 pF 10 kΩ
TDA4886
−
150 pF
J3
100 nF
50 Ω 10 nF
10 kΩ
VO3
3.3 pF
5 kΩ
150 pF
1 kΩ
U19
5.6 Ω
VO2
0.47 µF
50 Ω
50 Ω
−
+
0.47 µF
150 pF
10 kΩ
3.3 pF
10 nF
HFB
VO1
3.3 pF
50 Ω
VI1
10 kΩ
50 Ω
−
0.47 µF
+
−
0.47 µF
+
5.6 Ω
5.6 Ω
10 kΩ
10 kΩ
10 nF
SDA
SCL
LIMAC
MHB216
Dimensions are in mm.
Fig.17 Top view of the printed-circuit board (for the bottom view see Fig.18).
1998 Nov 11
35
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
handbook, full pagewidth
TDA4886
103
81
100 pF
100 nF
100 nF
100 pF
MHB217
Dimensions are in mm.
Fig.18 Bottom view of the printed-circuit board (for the top view see Fig.17).
1998 Nov 11
36
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
12.2
Recommendations for building the application
board
• General
– Double-sided board
– Short HF loops by large ground plane on the rear
– SMD components with minimum parasitics.
• Voltage outputs
– Capacitive loads as small as possible
– Be aware of internal output resistance
(typically 75 Ω).
• Supply voltages
– Capacitors as near as possible to the pins
– Use electrolytic capacitors with small serial
resistance and inductance.
1998 Nov 11
37
TDA4886
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1
SYMBOL AND
DESCRIPTION
FBL; fast
blanking input
for OSD
insertion
CHARACTERISTIC
WAVEFORM
open-circuit base
EQUIVALENT CIRCUIT
50 µA
5V
50 µA
50 µA
50 µA
VP
signal
blanking
0V
MHA653
OSD1
blanking
OSD2
blanking
OSD3
blanking
1
1 kΩ
MHA928
2
OSD1; OSD
input channel 1
open-circuit base
5V
VP
50 µA
VP
0V
signal blanking
MHA653
1 kΩ
2
disable OSD
38
1 kΩ
FBL
3
OSD2; OSD
input channel 2
open-circuit base
5V
Philips Semiconductors
PIN
140 MHz video controller with I2C-bus
1998 Nov 11
13 INTERNAL CIRCUITRY
MHB197
VP
50 µA
VP
0V
signal blanking
MHA653
3
1 kΩ
disable OSD
1 kΩ
FBL
MHB198
Product specification
TDA4886
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OSD3; OSD
input channel 3
CHARACTERISTIC
WAVEFORM
open-circuit base
EQUIVALENT CIRCUIT
5V
VP
50 µA
VP
0V
signal blanking
MHA653
1 kΩ
4
disable OSD
1 kΩ
FBL
5
CLI; vertical
blanking input
(input clamping)
V5 > 0.2 V:
open-circuit base
V5 ≤ 0.2 V:
source current rising
with decreasing
voltage
5V
2.5 V
0V
2VBE
VP
6 kΩ
10 kΩ
MHB199
26 µA
MHA651
3 V + VBE
39
VP
Philips Semiconductors
4
SYMBOL AND
DESCRIPTION
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
1 kΩ
5
10 kΩ
power
on/down
MHA619
Product specification
TDA4886
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VI1; signal input
channel 1
CHARACTERISTIC
outside clamping
pulse: open-circuit
base with base
current
compensation
during clamping:
−135 to +135 µA
WAVEFORM
EQUIVALENT CIRCUIT
4.7 V
MIRROR
1:1
black
shoulder
VP
VP
video signal
sync
4V
3.7 V
6
input clamping (pin 5)
MHA652
700 Ω
1.8 V + VBE
signal
135 µA
240 µA
220 µA
0 µA
MHB200
7
40
VP; supply
voltage
21 mA
7
Philips Semiconductors
6
SYMBOL AND
DESCRIPTION
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
MHA621
Product specification
TDA4886
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VI2; signal input
channel 2
CHARACTERISTIC
outside clamping
pulse: open-circuit
base with base
current
compensation
during clamping:
−135 to +135 µA
WAVEFORM
EQUIVALENT CIRCUIT
4.7 V
MIRROR
1:1
black
shoulder
VP
VP
video signal
sync
4V
3.7 V
8
input clamping (pin 5)
MHA652
700 Ω
1.8 V + VBE
signal
135 µA
240 µA
220 µA
0 µA
MHB201
9
GND; ground
41
9
Philips Semiconductors
8
SYMBOL AND
DESCRIPTION
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
MHA623
10
VI3; signal input
channel 3
outside clamping
pulse: open-circuit
base with base
current
compensation
during clamping:
−135 to +135 µA
4.7 V
MIRROR
1:1
black
shoulder
VP
VP
video signal
sync
4V
3.7 V
10
input clamping (pin 5)
MHA652
700 Ω
1.8 V + VBE
240 µA
220 µA
0 µA
MHB202
TDA4886
135 µA
Product specification
signal
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HFB; horizontal
flyback input
(output
clamping,
blanking)
CHARACTERISTIC
WAVEFORM
EQUIVALENT CIRCUIT
V11 > 0.2 V:
open-circuit base
V11 ≤ 0.2 V: source
current rising with
decreasing voltage
5V
2VBE
VP
0V
27 µA
27 µA
clamping
blanking
12 kΩ
10 kΩ
6 kΩ
MHA649
VP
1.7 V
3 V + VBE
10 kΩ
1 kΩ
11
power on/down
12
SDA; I2C-bus
serial data
input/output
no acknowledge:
open-circuit base
42
during
acknowledge:
I12 = 4 mA
5V
3 µA
70 µA
19 µA
0V
MHA647
10
kΩ
2.46 V + VBE
12
acknowledge
13
SCL; I2C-bus
clock input
open-circuit base
5V
MHA625
Philips Semiconductors
11
SYMBOL AND
DESCRIPTION
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
MHB203
19 µA
0V
MHA648
10 kΩ
MHB204
TDA4886
2.46 V + VBE
Product specification
13
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CHARACTERISTIC
WAVEFORM
EQUIVALENT CIRCUIT
GNDX; signal
channel ground
14
MHB205
15
VP3; supply
voltage
channel 3
I15 = 21 mA
15
MHB206
16
VO3; signal
reference black level
output channel 3 0.1 to 2.8 V
MHA655
VP
brightness
500 Ω
VP
16
8 kΩ
75 Ω
1.5 kΩ
reference black level during output clamping
43
1 kΩ
Philips Semiconductors
14
SYMBOL AND
DESCRIPTION
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
3.5 pF
control bit PEDST = 0
pedestal black level
0.1 to 2.8 V
MHA656
10 µA
brightness
MHB207
pedestal black level during output clamping
control bit PEDST = 1
Product specification
TDA4886
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FB/R3;
feedback input/
reference
voltage output
channel 3
CHARACTERISTIC
open-circuit base
WAVEFORM
EQUIVALENT CIRCUIT
feedback reference 5.77 to 4.05 V
VP
40 I
PEDST = 0
2I
100 Ω
17
PEDST = 1
5.77 to 4.05 V
MHB215
1 kΩ
control bit FPOL = 0
−300 to +300 µA;
5.77 to 4.05 V
3 kΩ
control bit FPOL = 1
I
10 µA
10 µA
44
15 kΩ
Philips Semiconductors
17
SYMBOL AND
DESCRIPTION
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
Vs1
15 kΩ
Vs2
1 kΩ
MHB208
5.77 to 4.05 V
DC coupling; Vs1 = 0 V; Vs2 = 1 V; I = 0 (control bit FPOL = 0)
AC coupling; Vs1 = 1 V; Vs2 = 0 V; I = 7.5 µA (control bit FPOL = 1)
18
VP2; supply
voltage
channel 2
I18 = 21 mA
18
Product specification
TDA4886
MHB218
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CHARACTERISTIC
WAVEFORM
reference black level
VO2; signal
output channel 2 0.1 to 2.8 V
EQUIVALENT CIRCUIT
MHA655
VP
brightness
500 Ω
VP
19
8 kΩ
75 Ω
1.5 kΩ
reference black level during output clamping
1 kΩ
3.5 pF
control bit PEDST = 0
pedestal black level
0.1 to 2.8 V
MHA656
10 µA
brightness
MHB209
pedestal black level during output clamping
Philips Semiconductors
19
SYMBOL AND
DESCRIPTION
45
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
control bit PEDST = 1
Product specification
TDA4886
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FB/R2;
feedback input/
reference
voltage output
channel 2
CHARACTERISTIC
open-circuit base
WAVEFORM
EQUIVALENT CIRCUIT
feedback reference 5.77 to 4.05 V
VP
40 I
PEDST = 0
2I
100 Ω
20
PEDST = 1
5.77 to 4.05 V
MHB215
1 kΩ
control bit FPOL = 0
−300 to +300 µA;
5.77 to 4.05 V
3 kΩ
control bit FPOL = 1
I
10 µA
10 µA
46
15 kΩ
Philips Semiconductors
20
SYMBOL AND
DESCRIPTION
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
Vs1
15 kΩ
Vs2
1 kΩ
MHB210
5.77 to 4.05 V
DC coupling; Vs1 = 0 V; Vs2 = 1 V; I = 0 (control bit FPOL = 0)
AC coupling; Vs1 = 1 V; Vs2 = 0 V; I = 7.5 µA (control bit FPOL = 1)
21
VP1; supply
voltage
channel 1
I21 = 21 mA
21
Product specification
TDA4886
MHB211
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CHARACTERISTIC
WAVEFORM
reference black level
VO1; signal
output channel 1 0.1 to 2.8 V
EQUIVALENT CIRCUIT
MHA655
VP
brightness
500 Ω
VP
22
8 kΩ
75 Ω
1.5 kΩ
reference black level during output clamping
1 kΩ
3.5 pF
control bit PEDST = 0
pedestal black level
0.1 to 2.8 V
MHA656
10 µA
brightness
MHB212
pedestal black level during output clamping
Philips Semiconductors
22
SYMBOL AND
DESCRIPTION
47
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
control bit PEDST = 1
Product specification
TDA4886
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FB/R1;
feedback input/
reference
voltage output
channel 1
CHARACTERISTIC
open-circuit base
WAVEFORM
EQUIVALENT CIRCUIT
feedback reference 5.77 to 4.05 V
VP
40 I
PEDST = 0
2I
100 Ω
23
PEDST = 1
5.77 to 4.05 V
MHB215
1 kΩ
control bit FPOL = 0
−300 to +300 µA;
5.77 to 4.05 V
3 kΩ
control bit FPOL = 1
I
10 µA
10 µA
48
15 kΩ
Philips Semiconductors
23
SYMBOL AND
DESCRIPTION
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
Vs1
15 kΩ
1 kΩ
5.77 to 4.05 V
Vs2
MHB213
DC coupling; Vs1 = 0 V; Vs2 = 1 V; I = 0 (control bit FPOL = 0)
AC coupling; Vs1 = 1 V; Vs2 = 0 V; I = 7.5 µA (control bit FPOL = 1)
Product specification
TDA4886
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LIM; beam
current limiting
input
CHARACTERISTIC
WAVEFORM
EQUIVALENT CIRCUIT
open-circuit voltage
V24 = 5.0 V
V24 < 4.5 V:
open-circuit base
VP
24
21 µA
1 kΩ
5.0 V
10 kΩ
MHB214
Philips Semiconductors
24
SYMBOL AND
DESCRIPTION
49
140 MHz video controller with I2C-bus
1998 Nov 11
PIN
Product specification
TDA4886
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886
14 PACKAGE OUTLINE
SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
SOT234-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
(e 1)
w M
MH
b
13
24
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.7
0.51
3.8
1.3
0.8
0.53
0.40
0.32
0.23
22.3
21.4
9.1
8.7
1.778
10.16
3.2
2.8
10.7
10.2
12.2
10.5
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT234-1
1998 Nov 11
EUROPEAN
PROJECTION
50
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
15 SOLDERING
15.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
15.3
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
15.2
TDA4886
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
16 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Nov 11
51
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For all other countries apply to: Philips Semiconductors,
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/750/02/pp52
Date of release: 1998 Nov 11
Document order number:
9397 750 04763