GTL2018 8-bit LVTTL to GTL transceiver Rev. 01 — 15 February 2007 Product data sheet 1. General description The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL−/GTL/GTL+ bus. The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling receiver or as an LVTTL-to-GTL interface. The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL or 5 V CMOS inputs. 2. Features n Operates as an octal GTL−/GTL/GTL+ sampling receiver or as an LVTTL to GTL−/GTL/GTL+ driver n 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input n GTL input and output 3.6 V tolerant n Vref adjustable from 0.5 V to 0.5VCC n Partial power-down permitted n Latch-up protection exceeds 500 mA per JESD78 n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-CC101 n Package offered: TSSOP24 3. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Ci input capacitance control inputs; VI = 3.0 V or 0 V - 2 2.5 pF Cio input/output capacitance A port; VO = 3.0 V or 0 V - 4.6 6 pF B port; VO = VTT or 0 V - 3.4 4.3 pF GTL; Vref = 0.8 V; VTT = 1.2 V tPLH LOW-to-HIGH propagation delay An to Bn; see Figure 3 - 2.8 5 ns tPHL HIGH-to-LOW propagation delay An to Bn; see Figure 3 - 3.4 7 ns tPLH LOW-to-HIGH propagation delay Bn to An; see Figure 4 - 5.2 8 ns tPHL HIGH-to-LOW propagation delay Bn to An; see Figure 4 - 4.9 7 ns GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 4. Ordering information Table 2. Ordering information Tamb = −40 °C to +85 °C. Type number GTL2018PW Topside mark GTL2018PW Package Name Description Version TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 5. Functional diagram GTL2018 & B0 A0 & B1 A1 & B2 A2 & B3 A3 & B4 A4 & B5 A5 & B6 A6 & B7 A7 002aab603 VREF DIR Fig 1. Logic diagram of GTL2018 GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 2 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 6. Pinning information 6.1 Pinning GND 1 B0 2 24 VCC 23 A0 B1 3 22 A1 B2 4 21 A2 B3 5 20 A3 VREF 6 GND 7 B4 8 17 A5 B5 9 16 A6 B6 10 15 A7 B7 11 14 VCC 13 DIR GTL2018PW GND 12 19 GND 18 A4 002aab604 Fig 2. Pin configuration for TSSOP24 6.2 Pin description Table 3. Pin description Symbol Pin Description GND 1, 7, 12, 19 ground (0 V) B0 2 data inputs/outputs (B side, GTL) B1 3 B2 4 B3 5 B4 8 B5 9 B6 10 B7 11 VREF 6 GTL reference voltage DIR 13 direction control input (LVTTL) VCC 14, 24 positive supply voltage A7 15 data inputs/outputs (A side, LVTTL) A6 16 A5 17 A4 18 A3 20 A2 21 A1 22 A0 23 GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 3 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 7. Functional description Refer to Figure 1 “Logic diagram of GTL2018”. 7.1 Function table Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Input Input/output DIR An (LVTTL) Bn (GTL) H input Bn = An L An = Bn input 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC supply voltage IIK VI Unit −0.5 4.6 V input clamping current VI < 0 V - −50 mA input voltage A port −0.5[1] 7.0 V B port −0.5[1] 4.6 V IOK output clamping current VO < 0 V - −50 mA VO output voltage output in OFF or HIGH state; A port −0.5[1] 7.0 V output in OFF or HIGH state; B port −0.5[1] 4.6 V IOL IOH Tstg LOW-level output current HIGH-level output current A port [2] - 32 mA B port [2] - 80 mA A port [3] - −32 mA [4] −60 +150 °C storage temperature [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] Current into any output in the LOW state. [3] Current into any output in the HIGH state. [4] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. GTL2018_1 Product data sheet Max © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 4 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 9. Recommended operating conditions Table 6. Recommended operating conditions[1] Symbol Parameter VCC supply voltage termination VTT Conditions voltage[2] reference voltage Vref input voltage VI Min Typ Max Unit 3.0 - 3.6 V GTL− 0.85 0.9 0.95 V GTL 1.14 1.2 1.26 V GTL+ 1.35 1.5 1.65 V overall 0.5 2⁄ V 3 TT 0.5VCC V GTL− 0.5 0.6 0.63 V GTL 0.76 0.8 0.84 V GTL+ 0.87 1.0 1.10 V 0 VTT 3.6 V 0 3.3 5.5 V B port except B port HIGH-level input voltage B port Vref + 0.050 - - V except B port 2 - - V LOW-level input voltage B port - - Vref − 0.050 V except B port - - 0.8 V IOH HIGH-level output current A port - - −16 mA IOL LOW-level output current B port - - 40 mA A port - - 16 mA ambient temperature operating in free air −40 - 85 °C VIH VIL Tamb [1] Unused inputs must be held HIGH or LOW to prevent them from floating. [2] VTT maximum of 3.6 V with resistor sized to so IOL maximum is not exceeded. [3] A0 to A7 VI(max) is 3.6 V if configured as outputs (DIR = LOW). GTL2018_1 Product data sheet [3] © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 5 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 10. Static characteristics Table 7. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C. Symbol VOH VOL Parameter Conditions HIGH-level output voltage LOW-level output voltage input current II Min Typ[1] Max Unit VCC − 0.2 - - V 2.0 - - V - 0.23 0.4 V A port; VCC = 3.0 V; IOL = 8 mA [2] - 0.28 0.4 V A port; VCC = 3.0 V; IOL = 12 mA [2] - 0.40 0.55 V A port; VCC = 3.0 V; IOL = 16 mA [2] A port; VCC = 3.0 V to 3.6 V; IOH = −100 µA [2] A port; VCC = 3.0 V; IOH = −16 mA [2] B port; VCC = 3.0 V; IOL = 40 mA [2] - 0.55 0.8 V control inputs; VCC = 3.6 V; VI = VCC or GND - - ±1 µA B port; VCC = 3.6 V; VI = VTT or GND - - ±1 µA A port; VCC = 0 V or 3.6 V; VI = 5.5 V - - 10 µA A port; VCC = 3.6 V; VI = VCC - - ±1 µA A port; VCC = 3.6 V; VI = 0 V - - −5 µA IOZ off-state output current A port; VCC = 0 V; VI or VO = 0 V to 3.6 V - - ±100 µA ICC supply current A port; VCC = 3.6 V; VI = VCC or GND; IO = 0 mA - 8 12 mA B port; VCC = 3.6 V; VI = VTT or GND; IO = 0 mA - 8 12 mA ∆ICC[3] additional supply current per input; A port or control inputs; VCC = 3.6 V; VI = VCC − 0.6 V - - 500 µA Ci input capacitance control inputs; VI = 3.0 V or 0 V - 2 2.5 pF Cio input/output capacitance A port; VO = 3.0 V or 0 V - 4.6 6 pF B port; VO = VTT or 0 V - 3.4 4.3 pF [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. [2] The input and output voltage ratings my be exceeded if the input and output current ratings are observed. [3] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 6 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 11. Dynamic characteristics Table 8. Dynamic characteristics VCC = 3.3 V ± 0.3 V. Symbol Parameter Conditions Min Typ[1] Max Unit GTL−; Vref = 0.6 V; VTT = 0.9 V tPLH LOW-to-HIGH propagation delay An to Bn; see Figure 3 - 2.8 5 ns tPHL HIGH-to-LOW propagation delay An to Bn; see Figure 3 - 3.3 7 ns tPLH LOW-to-HIGH propagation delay Bn to An; see Figure 4 - 5.3 8 ns tPHL HIGH-to-LOW propagation delay Bn to An; see Figure 4 - 5.2 8 ns GTL; Vref = 0.8 V; VTT = 1.2 V tPLH LOW-to-HIGH propagation delay An to Bn; see Figure 3 - 2.8 5 ns tPHL HIGH-to-LOW propagation delay An to Bn; see Figure 3 - 3.4 7 ns tPLH LOW-to-HIGH propagation delay Bn to An; see Figure 4 - 5.2 8 ns tPHL HIGH-to-LOW propagation delay Bn to An; see Figure 4 - 4.9 7 ns GTL+; Vref = 1.0 V; VTT = 1.5 V tPLH LOW-to-HIGH propagation delay An to Bn; see Figure 3 - 2.8 5 ns tPHL HIGH-to-LOW propagation delay An to Bn; see Figure 3 - 3.4 7 ns tPLH LOW-to-HIGH propagation delay Bn to An; see Figure 4 - 5.1 8 ns tPHL HIGH-to-LOW propagation delay Bn to An; see Figure 4 - 4.7 7 ns [1] All typical values are at VCC = 3.3 V and Tamb = 25 °C. 11.1 Waveforms VM = 1.5 V at VCC ≥ 3.0 V; VM = 0.5VCC at VCC ≤ 2.7 V for A ports and control pins; VM = Vref for B ports. 3.0 V input 1.5 V 1.5 V 0V tPLH tp tPHL VOH 3.0 V VM output VM Vref Vref VOL 0V 002aab141 002aab140 VM = 1.5 V for A port and Vref for B port a. Pulse duration A port to B port b. Propagation delay times Fig 3. Voltage waveforms GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 7 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver VTT input Vref Vref 1/ V 3 TT tPLH tPHL VOH 1.5 V output 1.5 V VOL 002aab142 PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns Fig 4. Propagation delay, Bn to An 12. Test information VCC PULSE GENERATOR VI VO DUT RL 500 Ω CL 50 pF RT 002aab006 Fig 5. Load circuitry for switching times VTT VCC PULSE GENERATOR VI 25 Ω VO DUT RT CL 30 pF 002aab143 RL = load resistor. CL = load capacitance; includes jib and probe capacitance. RT = termination resistance; should be equal to Zo of pulse generators. Fig 6. Load circuit for B outputs GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 8 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 13. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 7. Package outline SOT355-1 (TSSOP24) GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 9 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 10 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 8) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10 Table 9. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 10. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 8. GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 11 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 8. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge GTL Gunning Transceiver Logic HBM Human Body Model LVTTL Low Voltage Transistor-Transistor Logic MM Machine Model PRR Pulse Repetition Rate TTL Transistor-Transistor Logic 16. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes GTL2018_1 20070215 Product data sheet - - GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 12 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] GTL2018_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 February 2007 13 of 14 GTL2018 NXP Semiconductors 8-bit LVTTL to GTL transceiver 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Introduction to soldering . . . . . . . . . . . . . . . . . 10 Wave and reflow soldering . . . . . . . . . . . . . . . 10 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 10 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 February 2007 Document identifier: GTL2018_1