PHILIPS LD6806F

LD6806 series
Ultra low-dropout regulator, low noise, 200 mA
Rev. 3 — 9 December 2011
Product data sheet
1. Product profile
1.1 General description
The LD6806 series is a small-size Low-DropOut regulator (LDO) family with a typical
voltage drop of 60 mV at 200 mA current rating.
The device is available in three different surface-mounted packages, one 0.4 mm pitch
CSP, one leadless plastic package SOT886 and one gull wing package SOT753.
The operating voltage ranges from 2.3 V to 5.5 V and the output voltage ranges from
1.2 V to 3.6 V.
LD6806x/xxH devices show a high-ohmic state at the output pin, while the LD6806x/xxP
contains a pull-down switching transistor, to provide a low-ohmic output stage when the
device is disabled. All devices use the same regulator design and are manufactured in
monolithic silicon technology.
These features make the LD6806 series ideal for use in applications requiring component
miniaturization, such as mobile phone handsets, cordless telephones and personal digital
devices.
1.2 Features and benefits
















Input voltage range 2.3 V to 5.5 V
Output voltage range 1.2 V to 3.6 V
Dropout voltage 60 mV at 200 mA output rating
Low quiescent current in shutdown mode (typical 1.0 A)
30 V RMS output noise voltage (typical value) at 10 Hz to 100 kHz
Turn-on time just 200 s
55 dB Power Supply Rejection Ratio (PSRR) at 1 kHz
Temperature watchdog
Current limiter
LD6806xxxH: high-ohmic (3-state) output state when disabled
LD6806xxxP: low-ohmic output state when disabled
Integrated ESD protection of 10 kV Human Body Model
WLCSP with 0.4 mm pitch and package size of 0.76 mm  0.76 mm  0.47 mm
SOT886 leadless package 1.0 mm  1.45 mm  0.5 mm
SOT753 plastic surface-mounted device
Pb-free, RoHS compliant and free of Halogen and Antimony (dark green compliant)
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
1.3 Applications
 Analog and digital interfaces requiring lower than standard supply voltage in mobile
appliances such as mobile phones, media players and so on.
2. Pinning information
2.1 Pinning
LD6806
bump A1
index area
1
4
1
6
IN
n.c.
2
5
n.c.
GND
3
4
EN
2
A
5
OUT
B
001aao107
1
Fig 1.
2
001aao333
transparent top view,
solder balls facing down
3
Configuration for SOT753
Fig 2.
Configuration for WLCSP4
Transparent top view
Fig 3.
Configuration for SOT886
2.2 Pin description
Table 1.
Symbol
Pin
Description
IN
1
supply voltage input
GND
2
supply ground
EN
3
device enable input; active HIGH
n.c.
4
not connected
OUT
5
regulator output voltage
Table 2.
Product data sheet
Pin description for WLCSP4
Symbol
Pin
Description
GND
A1
supply ground
EN
A2
device enable input; active HIGH
OUT
B1
regulator output voltage
IN
B2
supply voltage input
Table 3.
LD6806_SER
Pin description for SOT753
Pin description for SOT886
Symbol
Pin
Description
OUT
1
regulator output voltage
n.c.
2
not connected
GND
3
supply ground
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
2 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
Table 3.
Pin description for SOT886
Symbol
Pin
Description
EN
4
device enable input; active HIGH
n.c.
5
not connected
IN
6
supply voltage input
3. Ordering information
Table 4.
Ordering information
Type number
Package
Name
Description
LD6806CX4/xxx
WLCSP4
wafer level chip-size package; 4 bumps (2 
LD6806CX4/C/xxx
WLCSP4
wafer level chip-size package; 4 bumps (2  2)
with backside coating[1]
-
LD6806F/xxx
XSON6
plastic extremely thin small outline package; no
leads; 6 terminals; body 1  1.45  0.5 mm
SOT886
LD6806TD/xxx
TSOP5
plastic surface-mounted package; 5 leads
SOT753
[1]
Version
2)[1]
-
Size 0.76 mm  0.76 mm.
3.1 Ordering options
Further information on output voltage is available on request; see Section 21 “Contact
information”.
Table 5.
Type number
Nominal
output
voltage
Type number
Nominal
output
voltage
LD6806[CX4, CX4/C, F, TD]/12H
1.2 V
LD6806[CX4, CX4/C, F, TD]/23H
2.3 V
LD6806[CX4, CX4/C, F, TD]/13H
1.3 V
LD6806[CX4, CX4/C, F, TD]/25H
2.5 V
LD6806[CX4, CX4/C, F, TD]/14H
1.4 V
LD6806[CX4, CX4/C, F, TD]/28H
2.8 V
LD6806[CX4, CX4/C, F, TD]/16H
1.6 V
LD6806[CX4, CX4/C, F, TD]/29H
2.9 V
LD6806[CX4, CX4/C, F, TD]/18H
1.8 V
LD6806[CX4, CX4/C, F, TD]/30H
3.0 V
LD6806[CX4, CX4/C, F, TD]/20H
2.0 V
LD6806[CX4, CX4/C, F, TD]/33H
3.3 V
LD6806[CX4, CX4/C, F, TD]/22H
2.2 V
LD6806[CX4, CX4/C, F, TD]/36H
3.6 V
Table 6.
LD6806_SER
Product data sheet
Type number and nominal output voltage of high-ohmic output
Type number and nominal output voltage of low.ohmic output
Type number
Nominal
output
voltage
Type number
Nominal
output
voltage
LD6806[CX4, CX4/C, F, TD]/12P
1.2 V
LD6806[CX4, CX4/C, F, TD]/23P
2.3 V
LD6806[CX4, CX4/C, F, TD]/13P
1.3 V
LD6806[CX4, CX4/C, F, TD]/25P
2.5 V
LD6806[CX4, CX4/C, F, TD]/14P
1.4 V
LD6806[CX4, CX4/C, F, TD]/28P
2.8 V
LD6806[CX4, CX4/C, F, TD]/16P
1.6 V
LD6806[CX4, CX4/C, F, TD]/29P
2.9 V
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
3 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
Table 6.
Type number and nominal output voltage of low.ohmic output …continued
Type number
Nominal
output
voltage
Type number
Nominal
output
voltage
LD6806[CX4, CX4/C, F, TD]/18P
1.8 V
LD6806[CX4, CX4/C, F, TD]/30P
3.0 V
LD6806[CX4, CX4/C, F, TD]/20P
2.0 V
LD6806[CX4, CX4/C, F, TD]/33P
3.3 V
LD6806[CX4, CX4/C, F, TD]/22P
2.2 V
LD6806[CX4, CX4/C, F, TD]/36P
3.6 V
4. Block diagram
VIN
VOUT
R1
VEN
Vreference
GENERATOR
THERMAL
PROTECTION
R2
OVERCURRENT
PROTECTION
GND
001aan756
Fig 4.
Block diagram of LD6806x/xxH
VIN
VOUT
R1
VEN
Vreference
GENERATOR
THERMAL
PROTECTION
R2
OVER CURRENT
PROTECTION
GND
Fig 5.
LD6806_SER
Product data sheet
001aan299
Block diagram of LD6806x/xxP
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Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
4 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
5. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VIN
voltage on pin IN
4 ms transient
total power dissipation
Ptot
Min
Max
Unit
0.5
+6.0
V
LD6806CX4/xxx,
LD6806CX4/Cxxx
[1]
-
770
mW
LD6806F/xxx
[1]
-
450
mW
LD6806TD/xxx
[1]
-
800
mW
Tstg
storage temperature
55
+150
C
Tj
junction temperature
40
+125
C
Tamb
ambient temperature
40
+85
C
10
kV
400
V
VESD
electrostatic discharge voltage
human body model level 6
[2]
machine model class 3
[3]
-
[1]
The (absolute) maximum power dissipation depends on the junction temperature Tj. Higher power dissipation is allowed with lower
ambient temperatures. The conditions to determine the specified values are Tamb = 25 C and the use of a two layer PCB.
[2]
According to IEC 61340-3-1.
[3]
According to JESD22-A115C.
6. Recommended operating conditions
Table 8.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
Tamb
ambient temperature
40
+85
C
Tj
junction temperature
-
+125
C
voltage on pin IN
2.3
5.5
V
voltage on pin EN
0
VIN
V
1.0
-
F
Pin IN
VIN
Pin EN
VEN
Pin OUT
CL(ext)
[1]
[1]
external load capacitance
See Section 10.1 “Output capacitor values”.
LD6806_SER
Product data sheet
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Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
5 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
7. Thermal characteristics
Table 9.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
thermal resistance from junction to ambient
Typ
Unit
LD6806CX4/xxx,
LD6806CX4/Cxxx
[1][2]
130
K/W
LD6806F/xxx
[1][2]
220
K/W
LD6806TD/xxx
[1][2]
125
K/W
[1]
The overall Rth(j-a) can vary depending on the board layout. To minimize the effective Rth(j-a), all pins must have a solid connection to
larger Cu layer areas for example to the power and ground layer. In multi-layer PCB applications, the second layer should be used to
create a large heat spreader area directly below the LDO. If this layer is either ground or power, it should be connected with several vias
to the top layer connecting to the device ground or supply. Avoid the use of solder-stop varnish under the chip.
[2]
Use the measurement data given for a rough estimation of the Rth(j-a) in your application. The actual Rth(j-a) value can vary in applications
using different layer stacks and layouts.
8. Characteristics
Table 10. Electrical characteristics
At recommended input voltages and Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VO
output voltage variation
VOUT < 1.8 V; IOUT = 1 mA
Tamb = +25 C
3
0.5
+3
%
30 C  Tamb  +85 C
4
-
+4
%
Tamb = +25 C
2
0.5
+2
%
30 C  Tamb  +85 C
3
-
+3
%
+0.1
%/V
VOUT  1.8 V; IOUT = 1 mA
Line regulation error
VO/(VOxVI)
relative output voltage
variation with input voltage
VIN = (VO(nom) + 0.2 V) to 5.5 V
[1]
0.1 -
Load regulation error
VO/(VOxIO)
relative output voltage
variation with output current
1 mA  IOUT  200 mA
LD6806CX4/xxx, LD6806CX4/Cxxx
-
0.0025 0.01
%/mA
-
0.005
0.02
%/mA
LD6806CX4/xxx, LD6806CX4/Cxxx
-
60
100
mV
LD6806F/xxx, LD6806TD/xxx
-
80
130
mV
LD6806F/xxx, LD6806TD/xxx
Vdo
dropout voltage
IOUT = 200 mA; VIN > VO(nom)
[1]
VIL
LOW-level input voltage
pin EN
0
-
0.4
V
VIH
HIGH-level input voltage
pin EN
1.4
-
5.5
V
IOUT
current on pin OUT
-
-
200
mA
IOM
peak output current
300
-
-
mA
300
-
-
mA
VIN = (VO(nom) + 0.2 V) to 5.5 V
VO(nom) > 1.8 V;
[1]
VOUT  0.95  VO(nom)
VO(nom) < 1.8 V;
VOUT  0.9  VO(nom)
LD6806_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
6 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
Table 10. Electrical characteristics …continued
At recommended input voltages and Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Isc
short-circuit current
pin OUT
-
600
-
mA
Iq
quiescent current
VEN = 1.4 V; IOUT = 0 mA
-
70
100
A
VEN = 1.4 V; 1 mA  IOUT  200 mA
-
155
250
A
VEN  0.4 V
-
0.1
1.0
A
-
160
-
C
[2]
-
20
-
K
[1]
-
55
-
dB
-
30
-
V
shutdown temperature
Tsd
Tsd(hys)
shutdown temperature
hysteresis
PSRR
power supply rejection ratio
VIN = VO(nom) + 1 V; IOUT = 30 mA;
fripple = 1 kHz
Vn(o)(RMS)
RMS output noise voltage
bandwidth = 10 Hz to 100 kHz;
CL(ext) = 1 F
tstartup(reg)
regulator start-up time
VIN = 5.5 V; VOUT = 0.95  VO(nom);
IOUT = 200 mA; CL(ext) = 1 F
[1]
-
-
200
s
tsd(reg)
regulator shutdown time
VIN = 5.5 V; CL(ext) = 1 F
[3]
-
300
-
s
Rpd
pull-down resistance
[3]
-
100
-

[1]
VO(nom) = nominal output voltage (device specific).
[2]
The junction temperature must decrease by Tsd(hys) to enable the device after Tsd was reached and the device was disabled.
[3]
LD6806x/xxP only.
9. Dynamic behavior
All results described in Section 9 are based on measurements of types LD6806CX4xxx
and LD6806Fxxx from the LD6806 product series within Section 6 “Recommended
operating conditions”.
9.1 Dropout
The dropout voltage is defined as the smallest input to output voltage difference at a
specified load current when the regulator operates within its linear region with the pass
transistor functioning as a plain resistor. This means that the input voltage is below the
nominal output voltage value.
A small dropout voltage guaranties lower power consumption and efficiency maximization.
LD6806_SER
Product data sheet
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Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
7 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
001aan929
100
Vdo
(mV)
001aan930
100
Vdo
(mV)
80
80
60
60
(1)
(2)
(3)
40
40
20
0
(1)
(2)
(3)
20
0
40
80
120
0
160
200
IOUT (mA)
0
(1) +85 C
(1) +85 C
(2) +25 C
(2) +25 C
(3) 40 C
(3) 40 C
Fig 6.
Dropout as a function of temperature for
LD6806CX4/25H
001aan935
100
Vdo
(mV)
Fig 7.
80
120
160
200
IOUT (mA)
Dropout as a function of temperature for
LD6806F/25H
001aan936
100
Vdo
(mV)
80
80
60
60
40
0
(1)
(2)
(3)
40
(1)
(2)
(3)
20
20
0
40
80
120
0
160
200
IOUT (mA)
0
(1) +85 C
(1) +85 C
(2) +25 C
(2) +25 C
(3) 40 C
(3) 40 C
Fig 8.
40
Dropout as a function of temperature for
LD6806CX4/36H
LD6806_SER
Product data sheet
Fig 9.
40
80
120
160
200
IOUT (mA)
Dropout as a function of temperature for
LD6806F/36H
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Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
8 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
018aaa223
100
Vdo
(mV)
80
60
(1)
40
(2)
(3)
20
0
0
40
80
120
160
200
IOUT (mA)
(1) +85 C
(2) +25 C
(3) 40 C
Fig 10. Dropout as a function of temperature for LD6806TD/36P
9.2 Output voltage variation
The guaranteed output voltages are specified in Table 10.
001aan942
1.24
VOUT
(V)
VOUT
(V)
1.22
2.52
(1)
(2)
(3)
(1)
(2)
(3)
1.20
2.50
1.18
2.48
1.16
-60
001aan943
2.54
-20
20
60
100
140
Tamb (°C)
2.46
-60
-20
(1) IOUT = 1 mA
(1) IOUT = 1 mA
(2) IOUT = 100 mA
(2) IOUT = 100 mA
(3) IOUT = 200 mA
(3) IOUT = 200 mA
Fig 11. Output voltage variation for LD6806CX4/12H
LD6806_SER
Product data sheet
20
60
100
140
Tamb (°C)
Fig 12. Output voltage variation for LD6806CX4/25H
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Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
9 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
9.3 Quiescent current
Quiescent or ground current is the difference between the input and the output current of
the regulator.
001aao106
80
IGND
(μA)
001aan944
85
IGND
(μA)
75
80
(1)
70
(2)
(1)
75
(2)
65
60
-60
-20
20
60
100
140
Tamb (°C)
(1) IOUT = 10 mA
(2) IOUT = 0 mA
Product data sheet
-20
20
60
100
140
Tamb (°C)
(1) IOUT = 10 mA
(2) IOUT = 0 mA
Fig 13. Quiescent current for LD6806CX4/12H
LD6806_SER
70
-60
Fig 14. Quiescent current for LD6806CX4/25H
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Rev. 3 — 9 December 2011
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10 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
9.4 Noise
Output noise voltage of an LDO circuit is given as noise density or RMS output noise
voltage over a defined range of frequencies (10 Hz to 100 kHz). Permanent conditions are
a constant output current and a ripple-free input voltage. The output noise voltage is
generated by the LDO regulator.
001aan941
10
noise
(μV/√Hz)
noise
(μV/√Hz)
(1)
(2)
(3)
(4)
(5)
(6)
1
(1)
(2)
(3)
(4)
(5)
(6)
1
10-1
10-2
001aao104
10
10-1
10
102
103
104
105
frequency (Hz)
10-2
10
(1) 0 mA
(1) 0 mA
(2) 1 mA
(2) 1 mA
(3) 50 mA
(3) 50 mA
(4) 100 mA
(4) 100 mA
(5) 150 mA
(5) 150 mA
(6) 200 mA
(6) 200 mA
Fig 15. Noise density for LD6806CX4/25H
LD6806_SER
Product data sheet
102
103
104
105
frequency (Hz)
Fig 16. Noise density for LD6806CX4/36H
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LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
9.5 Line regulation
Line regulation response is the capability of the circuit to maintain the nominal output
voltage while varying the input voltage.
V OUT 100
Regulation  %  V  = -----------------  ------------V IN V OUT
001aan925
6
(1)
2.0
VOUT
(V)
VIN
(V)
1.8
001aan926
6
(1)
VOUT
(V)
VIN
(V)
4
1.8
4
1.6
1.6
1.4
1.4
2
2
(2)
0
0
0.2
(2)
1.2
0.4
0.6
time (ms)
0
1.0
0.8
0
(1) VIN
(1) VIN
(2) VOUT
(2) VOUT
Fig 17. Line regulation for LD6806CX4/12H
0.1
0.2
0.3
1.2
0.4
0.5
1.0
0.6
0.7
time (ms)
Fig 18. Line regulation for LD6806F/12H
001aan931
6
(1)
VIN
(V)
2.55
VOUT
2.54 (V)
2.53
2.52
4
001aan932
6
(1)
VIN
(V)
2.52
4
2.51
(2)
2.50
2.50
2.49
2
2.48
0
0.1
0.2
0.3
time (ms)
(1) VIN
(2) VOUT
Product data sheet
2.49
2
2.48
2.47
2.47
2.46
2.46
2.45
0.4
0
0
0.1
0.2
0.3
time (ms)
2.45
0.4
(1) VIN
(2) VOUT
Fig 19. Line regulation for LD6806CX4/25H
LD6806_SER
2.55
VOUT
2.54 (V)
2.53
2.51
(2)
0
2.0
Fig 20. Line regulation for LD6806F/25H
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Rev. 3 — 9 December 2011
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12 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
001aan937
6
(1)
VIN
(V)
VOUT
(V)
4
001aan938
6
3.75
(1)
VIN
(V)
VOUT
(V)
4
3.65
3.65
(2)
(2)
2
0
0
0.2
3.75
0.4
0.6
time (ms)
3.55
2
3.45
0.8
0
3.55
0
(1) VIN
(1) VIN
(2) VOUT
(2) VOUT
Fig 21. Line regulation for LD6806CX4/36H
0.1
0.2
0.3
0.4
3.45
0.6
0.7
time (ms)
0.5
Fig 22. Line regulation for LD6806F/36H
9.6 Load regulation
Load regulation is the capability of the circuit to maintain the nominal output voltage while
varying the output load current.
V OUT
------------------  100
V O  nom 
Load regulation  %  mA  = ----------------------------------I OUT  max 
001aan927
0.5
(2)
1.3
1.2
IOUT
(A)
VOUT
(V)
001aan928
0.5
IOUT
(A)
1.1
0.3
1.0
(1)
0.8
-0.1
0
0.1
0.2
0.3
0.4
0.5
1.15
(1)
1.05
0.1
1.00
0.6
0.95
-0.1
0
(1) IOUT
(1) IOUT
(2) VOUT
(2) VOUT
LD6806_SER
Product data sheet
1.10
0.7
0.5
0.6
0.7
time (ms)
Fig 23. Load regulation for LD6806CX4/12H
1.20
(2)
0.3
0.9
0.1
1.30
VOUT
(V)
1.25
0.2
0.4
0.6
time (ms)
0.90
0.8
Fig 24. Load regulation for LD6806F/12H
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001aan933
0.5
001aan934
2.6
IOUT
(A)
VOUT
(V)
2.6
IOUT
(A)
VOUT
(V)
(2)
(2)
0.3
0.5
2.5
0.3
2.5
2.4
0.1
2.4
(1)
0.1
(1)
-0.1
0
0.1
0.2
0.3
time (ms)
2.3
0.4
-0.1
0
(1) IOUT
(1) IOUT
(2) VOUT
(2) VOUT
Fig 25. Load regulation for LD6806CX4/25H
IOUT
(A)
0.2
0.3
time (ms)
2.3
0.4
Fig 26. Load regulation for LD6806F/25H
001aan939
0.5
0.1
3.7
VOUT
(V)
001aan940
0.5
IOUT
(A)
3.7
VOUT
(V)
(2)
(2)
0.3
3.6
0.3
3.6
3.5
0.1
3.5
(1)
0.1
(1)
-0.1
0
0.1
0.2
0.3
0.4
0.5
3.4
0.6
0.7
time (ms)
-0.1
0
(1) IOUT
(1) IOUT
(2) VOUT
(2) VOUT
Fig 27. Load regulation for LD6806CX4/36H
LD6806_SER
Product data sheet
0.1
0.2
0.3
0.4
0.5
3.4
0.6
0.7
time (ms)
Fig 28. Load regulation for LD6806F/36H
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9.7 Start-up and shut down
Start-up time defines the time needed for the LDO to achieve 95 % of its typical output
voltage level after activation via the enable pin.
Shut down time defines the time needed for the LDO to pull-down the output voltage to
10% of its nominal output voltage after deactivation via the enable pin.
001aan946
1.6
VOUT
(V)
2.5
(1)
Venable
(V)
3
1.2
(2)
2
001aan947
1.4
Venable
(V)
1.2
3
VOUT
(V)
2.5
1
2
0.8
0.8
1.5
(1)
1.5
(2)
0.6
1
0.4
0.5
0
1
0.4
0
0.05
0.1
0
0.15
0.2
time (ms)
0.5
0.2
0
0
(1) VEN.
(1) VEN.
(2) VOUT.
(2) VOUT.
Fig 29. Start-up for LD6806CX4/23H
LD6806_SER
Product data sheet
0.1
0.2
0.3
time (ms)
0
0.4
Fig 30. Shut down for LD6806F/25P
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Ultra low-dropout regulator, low noise, 200 mA
9.8 Power Supply Rejection Ratio (PSRR)
PSRR stands for the capability of the regulator to suppress unwanted signals on the input
voltage like noise or ripples.
V out  ripple 
for all frequencies
PSRR  dB  = 20 log -------------------------V in  ripple 
001aan945
0
PSRR
(dB)
-10
001aao105
0
PSSR
(dB)
-20
-20
-30
(1)
(2)
(3)
(4)
-40
-50
-40
(1)
(2)
(3)
(4)
-60
-70
102
103
104
105
frequency (Hz)
-60
102
(1) 1 mA
(1) 1 mA
(2) 50 mA
(2) 50 mA
(3) 100 mA
(3) 100 mA
(4) 200 mA
(4) 200 mA
Fig 31.
PSRR for LD6806CX4/25H
LD6806_SER
Product data sheet
Fig 32.
103
104
105
frequency (Hz)
PSRR for LD6806CX4/36H
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9.9 Enable threshold voltage
An active HIGH signal enables the LDO when the signal exceeds the minimum input
HIGH voltage threshold. The device is in Off state as long the signal is below the
maximum LOW threshold. The input voltage threshold is independent from the LDO
supply voltage.
001aan808
3.5
VOUT
(V)
2.5
1.5
(2)
(1)
0.5
-0.5
0.3
0.5
0.7
0.9
1.1
1.3
VEN (V)
1.5
(1) LOW to HIGH
(2) HIGH to LOW
Fig 33. Enable threshold voltage
LD6806_SER
Product data sheet
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Ultra low-dropout regulator, low noise, 200 mA
10. Application information
10.1 Output capacitor values
The LD6806 series requires external capacitors at the output to guarantee a stable
regulator behavior. Also an input capacitor is recommended to keep the input voltage
stable. These capacitors should not under-run the specified minimum Equivalent Series
Resistance (ESR).
The absolute value of the total capacitance attached to the output pin OUT influences the
shutdown time (tsd(reg)) of the LD6806 series.
Table 11.
External load capacitor
Symbol
Parameter
Conditions
[1]
CL(ext)
external load capacitance
ESR
equivalent series resistance
[1]
Min
Typ
Max
Unit
-
1.0
-
F
5
-
500
m
The minimum value of capacitance for stability and correct operation is 0.7 F. The capacitor tolerance
should be 30 % or better over the temperature range. The full range of operating conditions for the
capacitor in the application should be considered during device selection to ensure that this minimum
capacitance specification is met. The recommended capacitor type is X7R to meet the full device
temperature specification of 40 C to +125 C.
IN
IN
OUT
EN
GND
1μF
OUT
1μF
001aan647
Fig 34. Application diagram
11. Test information
11.1 Quality information
This product has been qualified in accordance with NX2-00001 NXP Semiconductors
Quality and Reliability Specification and is suitable for use in consumer applications.
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12. Package outline
WLCSP4: wafer level chip-size package; 4 bumps (2 x 2)
D
bump A1
index area
A2
E
A
A1
detail X
e
b
B
e
A
1
2
X
European
projection
wlcsp4_2x2_po
Fig 35. Package outline WLCSP4
Table 12.
Dimensions of LD6806CX4/xxx for package outline WLCSP4; see Figure 35
Symbol
Min
Typ
Max
Unit
A
0.44
0.47
0.50
mm
A1
0.18
0.20
0.22
mm
A2
0.26
0.27
0.28
mm
b
0.21
0.26
0.31
mm
D
0.71
0.76
0.81
mm
E
0.71
0.76
0.81
mm
e
-
0.4
-
mm
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Product data sheet
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LD6806 series
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Ultra low-dropout regulator, low noise, 200 mA
WLCSP4: wafer level chip-size package with backside coating; 4 bumps (2 x 2)
D
A3
bump A1
index area
A2
E
A
A1
detail X
e
b
B
e
A
1
2
X
European
projection
wlcsp4_2x2_c_po
Fig 36. Package outline WLCSP4 with backside coating
Table 13.
Dimensions of LD6806CX4/Cxxx for package outline WLCSP4 with backside coating; see Figure 36
Symbol
Min
Typ
Max
Unit
A
0.47
0.51
0.55
mm
A1
0.18
0.20
0.22
mm
A2
0.26
0.27
0.28
mm
A3
0.03
0.04
0.05
mm
b
0.21
0.26
0.31
mm
D
0.71
0.76
0.81
mm
E
0.71
0.76
0.81
mm
e
-
0.4
-
mm
LD6806_SER
Product data sheet
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Ultra low-dropout regulator, low noise, 200 mA
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L1
e
6
5
4
e1
e1
6×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
1.5
1.4
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE
VERSION
SOT886
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-07-15
04-07-22
MO-252
Fig 37. Package outline SOT886 (XSON6)
LD6806_SER
Product data sheet
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LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
Plastic surface-mounted package; 5 leads
SOT753
D
E
B
y
A
X
HE
5
v M A
4
Q
A
A1
c
1
2
3
Lp
detail X
bp
e
w M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
c
D
E
e
HE
Lp
Q
v
w
y
mm
1.1
0.9
0.100
0.013
0.40
0.25
0.26
0.10
3.1
2.7
1.7
1.3
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
0.1
OUTLINE
VERSION
SOT753
REFERENCES
IEC
JEDEC
JEITA
SC-74A
EUROPEAN
PROJECTION
ISSUE DATE
02-04-16
06-03-16
Fig 38. SOT753; Plastic surface-mounted package; 5 leads
LD6806_SER
Product data sheet
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Ultra low-dropout regulator, low noise, 200 mA
13. Soldering
D
e
c
(4×)
e
solder resist
E
solder paste = solderland
f
(4×)
occupied area
Dimensions in mm
wlcsp4_2x2_fr
Fig 39. Soldering footprint WLCSP4
Table 14.
Dimensions of soldering footprint WLCSP4; see Figure 39
Symbol
Min
Typ
Max
Unit
c
-
0.25
-
mm
D
0.71
0.76
0.81
mm
E
0.71
0.76
0.81
mm
e
-
0.4
-
mm
f
-
0.325
-
mm
1.250
0.675
0.370
(6×)
0.500
1.700
0.500
0.270
(6×)
solder resist
solder paste = solderland
occupied area
Dimensions in mm
0.325
(6×)
0.425
(6×)
sot886_fr
Fig 40. Soldering footprint SOT886 (XSON6)
LD6806_SER
Product data sheet
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Ultra low-dropout regulator, low noise, 200 mA
3.45
1.95
0.45 0.55
(5×) (5×)
0.95
3.3
2.825
solder lands
solder resist
0.95
solder paste
occupied area
2.4
Dimensions in mm
0.7
(5×)
0.8
(5×)
sot753_fr
Fig 41. SOT753 (TSOP5); Reflow soldering footprint
5.3
1.5
(4×)
solder lands
1.475
solder resist
5.05
0.45
occupied area
1.475
Dimensions in mm
preferred transport
direction during soldering
1.45
(5×)
2.85
sot753_fw
Fig 42. SOT753 (TSOP5); Wave soldering footprint
14. Soldering of WLCSP packages
14.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
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Product data sheet
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Ultra low-dropout regulator, low noise, 200 mA
All NXP WLCSP packages are lead-free.
14.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
14.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 43) than a PbSn process, thus
reducing the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 15.
Table 15.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 43.
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Product data sheet
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Ultra low-dropout regulator, low noise, 200 mA
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 43. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
14.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
14.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
14.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
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Ultra low-dropout regulator, low noise, 200 mA
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
14.3.4 Cleaning
Cleaning can be done after reflow soldering.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
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Ultra low-dropout regulator, low noise, 200 mA
•
•
•
•
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 44) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 16 and 17
Table 16.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 17.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
LD6806_SER
Product data sheet
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LD6806 series
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Ultra low-dropout regulator, low noise, 200 mA
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 44.
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 44. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Mounting
16.1 PCB design guidelines
It is recommended, for optimum performance, to use a Non-Solder Mask Defined
(NSMD), also known as a copper-defined design, incorporating laser-drilled micro-vias
connecting the ground pads to a buried ground-plane layer. This results in the lowest
possible ground inductance and provides the best high frequency and ESD performance.
Refer to Table 18 for the recommended PCB design parameters.
Table 18.
Recommended PCB design parameters
Parameter
LD6806_SER
Product data sheet
Value or specification
PCB pad diameter
250 m
Micro-via diameter
100 m (0.004 inch)
Solder mask aperture diameter
325 m
Copper thickness
20 m to 40 m
Copper finish
AuNi or OSP
PCB material
FR4
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
29 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
16.2 PCB assembly guidelines for Pb-free soldering
Table 19.
Assembly recommendations
Parameter
Value or specification
Solder screen aperture diameter
250 m
Solder screen thickness
100 m (0.004 inch)
Solder paste: Pb-free
SnAg (3 % to 4 %); Cu (0.5 % to 0.9 %)
Solder to flux ratio
50 : 50
Solder reflow profile
see Figure 45
T
(°C)
Treflow(peak)
250
230
cooling rate
217
preheat
t1
t (s)
t2
t3
t4
t5
001aai943
The device is capable of withstanding at least three reflows at this profile.
Fig 45. Pb-free solder reflow profile
Table 20.
LD6806_SER
Product data sheet
Characteristics
Symbol
Parameter
Treflow(peak)
peak reflow temperature
t1
time 1
t2
Conditions
Min
Typ
Max
Unit
230
-
260
C
soak time
60
-
180
s
time 2
time during T  250 C
-
-
30
s
t3
time 3
time during T  230 C
10
-
50
s
t4
time 4
time during T > 217 C
30
-
150
s
t5
time 5
-
-
540
s
dT/dt
rate of change of
temperature
cooling rate
-
-
6
C/s
preheat
2.5
-
4.0
C/s
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
30 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
17. Abbreviations
Table 21.
Abbreviations
Acronym
Description
CSP
Chip-Size Package
DUT
Device Under Test
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
FR4
Flame Retard 4
HBM
Human Body Model
LDO
Low DropOut
MM
Machine Model
NSMD
Non-Solder Mask Design
OSP
Organic Solderability Preservation
PCB
Printed-Circuit Board
PSRR
Power Supply Rejection Ratio
PSU
Power Supply Unit
QRS
Quality and Reliability Specification
RMS
Root Mean Square
WLCSP
Wafer Level Chip-Size Package
18. References
LD6806_SER
Product data sheet
[1]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[2]
IEC 61340-3-1 — Methods for simulation of electrostatic effects - Human body
model (HBM) electrostatic discharge test waveforms
[3]
JESD22-A115C — Electrostatic discharge (ESD) Sensitivity Testing Machine
Model (MM)
[4]
NX2-00001 — NXP Semiconductors Quality and Reliability Specification
[5]
AN10439 — Wafer Level Chip Size Package
[6]
AN10365 — Surface mount reflow soldering description
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
31 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
19. Revision history
Table 22.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
LD6806_SER v.3
20111209
Product data sheet
-
LD6806_SER v.2
Modifications:
LD6806_SER v.2
Modifications:
LD6806_SER v.1
LD6806_SER
Product data sheet
•
•
•
•
WLCSP4 package with backside coating added
SOT753 package added
Subtype LD6806x/xxP introduced
Minor text changes
20110719
•
•
•
•
•
•
•
Product data sheet
-
LD6806_SER v.1
Descriptive title updated
Table 5: title changed
Table 10: three parameters updated
Table 3: pin number updated
Section 9.4 and Section 9.8 drawings updated
Section 16: values updated
Minor text changes
20110516
Preliminary data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
-
© NXP B.V. 2011. All rights reserved.
32 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
LD6806_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
33 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
LD6806_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
34 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Pin description for SOT753 . . . . . . . . . . . . . . . .2
Pin description for WLCSP4 . . . . . . . . . . . . . . . .2
Pin description for SOT886 . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Type number and nominal output voltage of
high-ohmic output . . . . . . . . . . . . . . . . . . . . . . .3
Table 6. Type number and nominal output voltage of
low.ohmic output . . . . . . . . . . . . . . . . . . . . . . . .3
Table 7. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 8. Operating conditions . . . . . . . . . . . . . . . . . . . . .5
Table 9. Thermal characteristics . . . . . . . . . . . . . . . . . . .6
Table 10. Electrical characteristics . . . . . . . . . . . . . . . . . .6
Table 11. External load capacitor . . . . . . . . . . . . . . . . . . .18
Table 12. Dimensions of LD6806CX4/xxx for package
outline WLCSP4; see Figure 35 . . . . . . . . . . . 19
Table 13. Dimensions of LD6806CX4/Cxxx for package
outline WLCSP4 with backside coating;
see Figure 36 . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. Dimensions of soldering footprint WLCSP4;
see Figure 39 . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Lead-free process (from J-STD-020C) . . . . . . 25
Table 16. SnPb eutectic process (from J-STD-020C) . . . 28
Table 17. Lead-free process (from J-STD-020C) . . . . . . 28
Table 18. Recommended PCB design parameters . . . . 29
Table 19. Assembly recommendations . . . . . . . . . . . . . . 30
Table 20. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 22. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32
23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Fig 31.
Fig 32.
Fig 33.
Configuration for SOT753 . . . . . . . . . . . . . . . . . . .2
Configuration for WLCSP4 . . . . . . . . . . . . . . . . . .2
Configuration for SOT886 . . . . . . . . . . . . . . . . . . .2
Block diagram of LD6806x/xxH . . . . . . . . . . . . . . .4
Block diagram of LD6806x/xxP . . . . . . . . . . . . . . .4
Dropout as a function of temperature for
LD6806CX4/25H . . . . . . . . . . . . . . . . . . . . . . . . . .8
Dropout as a function of temperature for
LD6806F/25H . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Dropout as a function of temperature for
LD6806CX4/36H . . . . . . . . . . . . . . . . . . . . . . . . . .8
Dropout as a function of temperature for
LD6806F/36H . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Dropout as a function of temperature for
LD6806TD/36P . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output voltage variation for LD6806CX4/12H . . . .9
Output voltage variation for LD6806CX4/25H . . . .9
Quiescent current for LD6806CX4/12H . . . . . . . .10
Quiescent current for LD6806CX4/25H . . . . . . . .10
Noise density for LD6806CX4/25H . . . . . . . . . . . 11
Noise density for LD6806CX4/36H . . . . . . . . . . . 11
Line regulation for LD6806CX4/12H . . . . . . . . . .12
Line regulation for LD6806F/12H. . . . . . . . . . . . .12
Line regulation for LD6806CX4/25H . . . . . . . . . .12
Line regulation for LD6806F/25H. . . . . . . . . . . . .12
Line regulation for LD6806CX4/36H . . . . . . . . . .13
Line regulation for LD6806F/36H. . . . . . . . . . . . .13
Load regulation for LD6806CX4/12H. . . . . . . . . .13
Load regulation for LD6806F/12H . . . . . . . . . . . .13
Load regulation for LD6806CX4/25H. . . . . . . . . .14
Load regulation for LD6806F/25H . . . . . . . . . . . .14
Load regulation for LD6806CX4/36H. . . . . . . . . .14
Load regulation for LD6806F/36H . . . . . . . . . . . .14
Start-up for LD6806CX4/23H . . . . . . . . . . . . . . . .15
Shut down for LD6806F/25P . . . . . . . . . . . . . . . .15
PSRR for LD6806CX4/25H . . . . . . . . . . . . . . . .16
PSRR for LD6806CX4/36H . . . . . . . . . . . . . . . .16
Enable threshold voltage . . . . . . . . . . . . . . . . . . .17
LD6806_SER
Product data sheet
Fig 34. Application diagram. . . . . . . . . . . . . . . . . . . . . . . 18
Fig 35. Package outline WLCSP4. . . . . . . . . . . . . . . . . . 19
Fig 36. Package outline WLCSP4 with backside
coating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Fig 37. Package outline SOT886 (XSON6). . . . . . . . . . . 21
Fig 38. SOT753; Plastic surface-mounted package;
5 leads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fig 39. Soldering footprint WLCSP4 . . . . . . . . . . . . . . . . 23
Fig 40. Soldering footprint SOT886 (XSON6) . . . . . . . . . 23
Fig 41. SOT753 (TSOP5); Reflow soldering footprint . . . 24
Fig 42. SOT753 (TSOP5); Wave soldering footprint . . . . 24
Fig 43. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Fig 44. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fig 45. Pb-free solder reflow profile . . . . . . . . . . . . . . . . 30
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 9 December 2011
© NXP B.V. 2011. All rights reserved.
35 of 36
LD6806 series
NXP Semiconductors
Ultra low-dropout regulator, low noise, 200 mA
24. Contents
1
1.1
1.2
1.3
2
2.1
2.2
3
3.1
4
5
6
7
8
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10
10.1
11
11.1
12
13
14
14.1
14.2
14.3
14.3.1
14.3.2
14.3.3
14.3.4
15
15.1
15.2
15.3
15.4
16
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 6
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Dynamic behavior . . . . . . . . . . . . . . . . . . . . . . . 7
Dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output voltage variation . . . . . . . . . . . . . . . . . . 9
Quiescent current . . . . . . . . . . . . . . . . . . . . . . 10
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Line regulation . . . . . . . . . . . . . . . . . . . . . . . . 12
Load regulation . . . . . . . . . . . . . . . . . . . . . . . . 13
Start-up and shut down. . . . . . . . . . . . . . . . . . 15
Power Supply Rejection Ratio (PSRR). . . . . . 16
Enable threshold voltage . . . . . . . . . . . . . . . . 17
Application information. . . . . . . . . . . . . . . . . . 18
Output capacitor values . . . . . . . . . . . . . . . . . 18
Test information . . . . . . . . . . . . . . . . . . . . . . . . 18
Quality information . . . . . . . . . . . . . . . . . . . . . 18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Soldering of WLCSP packages. . . . . . . . . . . . 24
Introduction to soldering WLCSP packages . . 24
Board mounting . . . . . . . . . . . . . . . . . . . . . . . 25
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25
Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Quality of solder joint . . . . . . . . . . . . . . . . . . . 26
Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Soldering of SMD packages . . . . . . . . . . . . . . 27
Introduction to soldering . . . . . . . . . . . . . . . . . 27
Wave and reflow soldering . . . . . . . . . . . . . . . 27
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28
Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
16.1
16.2
17
18
19
20
20.1
20.2
20.3
20.4
21
22
23
24
PCB design guidelines. . . . . . . . . . . . . . . . . .
PCB assembly guidelines for Pb-free
soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
30
31
31
32
33
33
33
33
34
34
35
35
36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]com
Date of release: 9 December 2011
Document identifier: LD6806_SER