ADC1115S125 Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs Rev. 01 — 12 April 2010 Preliminary data sheet 1. General description The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. The ADC1115S125 supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1115S125 is ideal for use in communications, imaging and medical applications - especially in high Intermediate Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures that the input impedance remains constant and low and the performance consistent over a wide frequency range. 2. Features and benefits SNR, 66.5 dBFS / SFDR, 86 dBc Sample rate up to 125 Msps Input bandwidth, 600 MHz Power dissipation, 840 mW including analog input buffer SPI Duty cycle stabilizer 11-bit pipelined ADC core Clock input divider by 2 for less jitter contribution Integrated input buffer Fast OuT of Range (OTR) detection Flexible input voltage range: 1 V (p-p) to INL ±1.25 LSB, DNL ±0.25 LSB 2 V (p-p) CMOS or LVDS DDR digital outputs Offset binary, two’s complement, gray code Pin compatible with the ADC1415S Power-down and Sleep modes series, the ADC1215S series and the ADC1015S series HVQFN40 package ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 3. Applications Wireless and wired broadband communications Portable instrumentation Imaging systems Digital predistortion loop, power amplifier linearization Spectral analysis Ultrasound equipment Software defined radio 4. Ordering information Table 1. Ordering information Type number fs (Msps) Package ADC1115S125HN/C1 125 Name Description Version HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-6 5. Block diagram SDIO/ODS CS SCLK/DFS ADC1115S ERROR CORRECTION AND DIGITAL PROCESSING SPI OTR CMOS: D10 to D0 or LVDS/DDR: D10P, D10M to D0P, D0M INP S/H INPUT STAGE INPUT BUFFER ADC CORE 11-BIT PIPELINED OUTPUT DRIVERS INM CMOS: DAV or LVDS/DDR: DAVP DAVM OUTPUT DRIVERS CLOCK INPUT STAGE AND DUTY CYCLE CONTROL SYSTEM REFERENCE AND POWER MANAGEMENT CLKP CLKM VREF REFB VCM SENSE REFT PWD OE 005aaa146 Fig 1. ADC1115S125_1 Preliminary data sheet Block diagram All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 2 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 6. Pinning information 31 DAV 32 n.c. 33 VDDO 34 OGND 35 OTR 36 SCLK/DFS 37 SDIO/ODS 38 CS 39 SENSE 40 VREF terminal 1 index area 31 DAV 32 n.c. 33 VDDO 34 OGND 35 OTR 36 SCLK/DFS 37 SDIO/ODS 38 CS terminal 1 index area 39 SENSE 40 VREF 6.1 Pinning REFB 1 30 n.c. REFB 1 30 n.c. REFT 2 29 n.c. REFT 2 29 n.c. AGND 3 28 LOW_D0_P AGND 3 28 n.c. VCM 4 VCM 4 27 D0 VDDA5V 5 VDDA5V 5 26 D1 AGND 6 AGND 6 25 D2 INM 7 24 D3_D4_P INM 7 24 D3 INP 8 23 D3_D4_M INP 8 23 D4 AGND 9 22 D5_D6_P AGND 9 22 D5 VDDA3V 10 21 D5_D6_M VDDA3V 10 21 D6 26 D1_D2_P D7_D8_P 20 D7_D8_M 19 25 D1_D2_M D9_D10_P 18 PWD 16 OE 15 DEC 14 CLKM 13 D9_D10_M 17 005aaa147 CLKP 12 VDDA3V 11 D7 20 D8 19 D9 18 D10 17 PWD 16 OE 15 DEC 14 CLKM 13 CLKP 12 VDDA3V 11 ADC1115S HVQFN40 27 LOW_D0_M ADC1115S HVQFN40 005aaa148 Transparent top view Transparent top view Fig 2. Pin configuration with CMOS digital outputs selected Fig 3. Pin configuration with LVDS/DDR digital outputs selected 6.2 Pin description Table 2. ADC1115S125_1 Preliminary data sheet Pin description (CMOS digital outputs) Symbol Pin Type [1] Description REFB 1 O bottom reference REFT 2 O top reference AGND 3 G analog ground VCM 4 O common-mode output voltage VDDA5V 5 P analog power supply 5 V AGND 6 G analog ground INM 7 I complementary analog input INP 8 I analog input AGND 9 G analog ground VDDA3V 10 P analog power supply 3 V VDDA3V 11 P analog power supply 3 V CLKP 12 I clock input CLKM 13 I complementary clock input DEC 14 O regulator decoupling node OE 15 I output enable, active LOW PWD 16 I power down, active HIGH All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 3 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 2. Symbol Pin Type [1] Description D10 17 O data output bit 10 (MSB) D9 18 O data output bit 9 D8 19 O data output bit 8 D7 20 O data output bit 7 D6 21 O data output bit 6 D5 22 O data output bit 5 D4 23 O data output bit 4 D3 24 O data output bit 3 D2 25 O data output bit 2 D1 26 O data output bit 1 D0 27 O data output bit 0 (LSB) n.c. 28 - not connected n.c. 29 - not connected n.c. 30 - not connected DAV 31 O data valid output clock n.c. 32 - not connected VDDO 33 P output power supply OGND 34 G output ground OTR 35 O out of range SCLK/DFS 36 I SPI clock / data format select SDIO/ODS 37 I/O SPI data IO / output data standard CS 38 I SPI chip select SENSE 39 I reference programming pin VREF 40 I/O voltage reference input/output [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. ADC1115S125_1 Preliminary data sheet Pin description (CMOS digital outputs) Pin description (LVDS/DDR) digital outputs) Symbol Pin [1] Type [2] Description D9_D10_M 17 O differential output data D9 and D10 multiplexed, complement D9_D10_P 18 O differential output data D9 and D10 multiplexed, true D7_D8_M 19 O differential output data D7 and D8 multiplexed, complement D7_D8_P 20 O differential output data D7 and D8 multiplexed, true D5_D6_M 21 O differential output data D5 and D6 multiplexed, complement D5_D6_P 22 O differential output data D5 and D6 multiplexed, true D3_D4_M 23 O differential output data D3 and D4 multiplexed, complement D3_D4_P 24 O differential output data D3 and D4 multiplexed, true D1_D2_M 25 O differential output data D1 and D2 multiplexed, complement D1_D2_P 26 O differential output data D1 and D2 multiplexed, true LOW_D0_M 27 O differential output data D0 multiplexed, complement LOW_D0_P 28 O differential output data D0 multiplexed, true n.c. 29 - not connected All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 4 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 3. Pin description …continued (LVDS/DDR) digital outputs) Symbol Pin [1] Type [2] Description n.c. 30 - not connected DAVM 31 O data valid output clock, complement DAVP 32 O data valid output clock, true [1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2) [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VO output voltage pins D10 to D0 or pins D10P to D0P and pins D10M to D0M −0.4 +3.9 V VDDA(3V) analog supply voltage 3 V on pin VDDA3V −0.5 +4.6 V VDDA(5V) analog supply voltage 5 V on pin VDDA5V −0.5 +6.0 V VDDO output supply voltage −0.5 +4.6 V ΔVCC supply voltage difference <tbd> <tbd> V Tstg storage temperature −55 +125 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 125 °C VDDA(3V) − VDDO 8. Thermal characteristics Table 5. Thermal characteristics Symbol Rth(j-a) Rth(j-c) [1] Parameter Conditions Typ Unit thermal resistance from junction to ambient [1] 30.5 K/W thermal resistance from junction to case [1] 13.3 K/W Value for six layers board in still air with a minimum of 25 thermal vias. 9. Static characteristics Table 6. Symbol Static characteristics[1] Parameter Conditions Min Typ Max Unit 4.75 5.0 5.25 V Supplies VDDA(5V) analog supply voltage 5 V VDDA(3V) analog supply voltage 3 V VDDO output supply voltage IDDA(5V) analog supply current 5 V ADC1115S125_1 Preliminary data sheet 2.85 3.0 3.4 V CMOS mode 1.65 1.8 3.6 V LVDS DDR mode 2.85 3.0 3.6 V fclk = 125 Msps; fi =70 MHz - 46 - mA All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 5 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 6. Static characteristics[1] …continued Symbol Parameter Conditions Min Typ Max Unit IDDA(3V) analog supply current 3 V fclk = 125 Msps; fi =70 MHz - 205 - mA IDDO output supply current CMOS mode; fclk = 125 Msps; fi =70 MHz - 11 - mA LVDS DDR mode: fclk = 125 Msps; fi =70 MHz - 39 - mA analog supply only - 840 - mW Power-down mode - 2 - mW Standby mode - 40 - mW differential clock input voltage peak-to-peak - ±1.6 - V differential clock input voltage peak-to-peak - ±0.70 - V differential clock input voltage peak-to-peak ±0.8 ±3.0 - V P power dissipation Clock inputs: pins CLKP and CLKM LVPECL Vi(clk)dif LVDS Vi(clk)dif SINE wave Vi(clk)dif LVCMOS VIL LOW-level input voltage - - 0.3VDDA(3V) V VIH HIGH-level input voltage 0.7VDDA(3V) - - V 0 - 0.8 V Logic inputs: pins PWD and OE VIL LOW-level input voltage VIH HIGH-level input voltage 2 - VDDA(3V) V IIL LOW-level input current <tbd> - <tbd> μA IIH HIGH-level input current −10 - +10 μA Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS VIL LOW-level input voltage 0 - 0.3VDDA(3V) V VIH HIGH-level input voltage 0.7VDDA(3V) - VDDA(3V) V IIL LOW-level input current −10 - +10 μA IIH HIGH-level input current −50 - +50 μA CI input capacitance - 4 - pF OGND - 0.2VDDO V Digital outputs, CMOS mode: pins D10 to D0, OTR, DAV Output levels, VDDO = 3 V VOL LOW-level output voltage IOL = <tbd> VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO - VDDO V IOL LOW-level output current 3-state; output level = 0 V - <tbd> - μA IOH HIGH-level output current 3-state; output level = VDDA(3V) - <tbd> - μA CO output capacitance high impedance; OE = HIGH - 3 - pF Output levels, VDDO = 1.8 V ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 6 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 6. Static characteristics[1] …continued Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage IOL = <tbd> OGND - 0.2VDDO V VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO - VDDO V Digital outputs, LVDS mode: pins D10P to D0P, D10M to D0M, DAVP and DAVM Output levels, VDDO = 3 V only, Rload = 100 Ω VO(offset) output offset voltage output buffer current set to 3.5 mA - 1.2 - V VO(dif) differential output voltage output buffer current set to 3.5 mA - 350 - mV CO output capacitance - <tbd> - pF −5 - +5 μA Analog inputs: pins INP and INM II input current RI input resistance - 550 - Ω CI input capacitance - 1.3 - pF VI(cm) common-mode input voltage 0.9 1.5 2 V Bi input bandwidth - 600 - MHz VI(dif) differential input voltage 2 V VINP = VINM peak-to-peak 1 Common mode output voltage: pin VCM VO(cm) common-mode output voltage - 0.5VDDA(3V) - V IO(cm) common-mode output current - <tbd> - μA output - 0.5 to 1 - V input 0.5 - 1 V <tbd> <tbd> <tbd> LSB <tbd> <tbd> <tbd> LSB I/O reference voltage: pin VREF VVREF voltage on pin VREF Accuracy INL integral non-linearity DNL differential non-linearity Eoffset offset error - ±2 - mV EG gain error - ±0.5 - %FS - 35 - dBc guaranteed no missing codes Supply PSRR [1] power supply rejection ratio 100 mV (p-p) on VDDA(3V) Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 7 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Symbol Dynamic characteristics[1] Parameter Conditions ADC1115S125 Min Unit Typ Max Analog signal processing α2H second harmonic level α3H third harmonic level THD ENOB SNR SFDR IMD [1] total harmonic distortion effective number of bits signal-to-noise ratio spurious-free dynamic range Intermodulation distortion fi = 3 MHz - 88 - dBc fi = 30 MHz - 87 - dBc fi = 70 MHz - 85 - dBc fi = 170 MHz - 83 - dBc fi = 3 MHz - 87 - dBc fi = 30 MHz - 86 - dBc fi = 70 MHz - 84 - dBc fi = 170 MHz - 82 - dBc fi = 3 MHz - 86 - dBc fi = 30 MHz - 85 - dBc fi = 70 MHz - 83 - dBc fi = 170 MHz - 81 - dBc fi = 3 MHz - 10.7 - bits fi = 30 MHz - 10.7 - bits fi = 70 MHz - 10.7 - bits fi = 170 MHz - 10.6 - bits fi = 3 MHz - 66.2 - dBFS fi = 30 MHz - 66.2 - dBFS fi = 70 MHz - 66.0 - dBFS fi = 170 MHz - 65.8 - dBFS fi = 3 MHz - 87 - dBc fi = 30 MHz - 86 - dBc fi = 70 MHz - 84 - dBc fi = 170 MHz - 82 - dBc fi = 3 MHz - 89 - dBc fi = 30 MHz - 88 - dBc fi = 70 MHz - 86 - dBc fi = 170 MHz - 84 - dBc Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 8 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 10.2 Clock and digital output timing Table 8. Symbol Clock and digital output timing characteristics[1] Parameter Conditions ADC1115S125 Min Unit Typ Max Clock timing input: pins CLKP and CLKM fclk clock frequency 100 - 125 MHz tlat(data) data latency time - 14 - clock cycles δclk clock duty cycle 30 50 70 % 45 50 55 % td(s) sampling delay time - 0.8 - ns twake wake-up time - tbd - ns DATA - 3.9 - ns DAV - 4.2 - ns DCS_EN = 1 DCS_EN = 0 CMOS mode timing output: pins D10 to D0 and DAV propagation delay tPD tsu set-up time - 4.3 - ns th hold time - 3.5 - ns DATA 0.5 - 2.4 ns DAV 0.5 - 2.4 ns DATA 0.5 - 2.4 ns rise tr fall tf time[2] time[2] LVDS DDR mode timing output: pins D10P to D0P, D10M to D0M, DAVP and DAVM propagation delay tPD DATA - 3.9 - ns DAV - 4.2 - ns tsu set-up time - 1.4 - ns th hold time - 2.0 - ns rise tr time[3] fall time[3] tf DATA 50 100 200 ps DAV 50 100 200 ps DATA 50 100 200 ps DAV 50 100 200 ps [1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. [2] Measured between 20 % to 80 % of VDDO. [3] Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV. ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 9 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tsu tPD th DAV tclk 005aaa060 Fig 4. CMOS mode timing N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) Dx_Dx + 1_P Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx_Dx + 1_M tsu th tsu th tPD DAVP DAVM tclk Fig 5. ADC1115S125_1 Preliminary data sheet 005aaa061 LDVS DDR mode timing All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 10 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 10.3 SPI timings Table 9. Characteristics Symbol Parameter Conditions Min Typ Max Unit SPI timings tw(SCLK) SCLK pulse width 40 - - ns tw(SCLKH) SCLK pulse width HIGH 16 - - ns tw(SCLKL) SCLK pulse width LOW 16 - - ns tsu set-up time data to SCLKH 5 - - ns CS to SCLKH 5 - - ns data to SCLKH 2 - - ns CS to SCLKH 2 - - ns - - 25 MHz hold time th fclk(max) [1] maximum clock frequency Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified tsu tsu th CS tw(SCLKL) th tw(SCLKH) tw(SCLK) SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 6. SPI timing 11. Application information 11.1 Device control The ADC1115S125 can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device will remain in this mode. The transition from Pin control mode to SPI control mode is illustrated in Figure 7. ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 11 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs CS Pin control mode SCLK/DFS Data format two's complement SDIO/ODS SPI control mode Data format offset binary LVDS DDR CMOS R/W W1 W0 A12 005aaa039 Fig 7. Control mode selection When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO as soon as a transition is triggered by a falling edge on CS. 11.1.2 Operating mode selection The active ADC1115S125 operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 19) or using pins PWD and OE in Pin control mode, as described in Table 10. Table 10. Operating mode selection via pin PWD and OE Pin PWD Pin OE Operating mode Output high-Z 0 0 Power-up no 0 1 Power-up yes 1 0 Sleep yes 1 1 Power-down yes 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 23) or using pin DFS in Pin control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1115S125 supports differential or single-ended input drive. Optimal performance is achieved using differential inputs. The ADC inputs are internally biased and need to be decoupled. The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 21 further details). ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 12 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 8. package ESD parasitics switch INP Ron = 15 Ω 8 internal clock 4 pF sampling capacitor INPUT BUFFER switch INM Ron = 15 Ω 7 internal clock 4 pF sampling capacitor 005aaa107 Fig 8. Input sampling circuit and input buffer The integrated input buffer offers the following advantages: • The kickback effect is avoided - the charge injection and glitches generated by the S/H input stage are isolated from the input circuitry. So there’s no need for additional filtering. • The input capacitance is very low and constant over a wide frequency range, which makes the ADC1115S125 easy to drive. The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 13 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.2.2 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 9 would be suitable for a baseband application. ADT1-1WT 100 nF 100 nF Analog input INP 50 Ω 100 nF 100 nF INM VCM 100 nF 100 nF 005aaa108 Fig 9. Single transformer configuration suitable for baseband applications The configuration shown in Figure 10 is recommended for high frequency applications. In both cases, the choice of transformer will be a compromise between cost and performance. ADT1-1WT Analog input 100 nF ADT1-1WT 100 nF INP 50 Ω 100 Ω 50 Ω 100 nF INM VCM 100 nF 100 nF 100 nF 005aaa109 Fig 10. Dual transformer configuration suitable for high intermediate frequency application ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 14 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.3 System reference and power management 11.3.1 Internal/external references The ADC1115S125 has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and −6 dB via control bits INTREF[2:0] when bit INTREF_EN = 1; see Table 21). See Figure 12, Figure 13, Figure 14 and Figure 15. The equivalent reference circuit is shown in Figure 11. External reference is also possible by providing a voltage on pin VREF as described in Figure 14. REFT REFERENCE AMP REFB VREF EXT_ref EXT_ref BUFFER BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 005aaa164 Fig 11. Reference equivalent schematic If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or externally as detailed in Table 11. Table 11. Selection SPI bit INTREF_EN SENSE pin VREF pin full scale (p-p) internal (Figure 12) 0 AGND 330 pF capacitor to AGND 2V internal (Figure 13) 0 pin VREF connected to pin SENSE and via a 330 pF capacitor to AGND 1V external (Figure 14) 0 VDDA(3V) external voltage between 0.5 V and 1 V[1] 1 V to 2 V internal via SPI (Figure 15) 1 pin VREF connected to pin SENSE and via 330 pF capacitor to AGND 1 V to 2 V [1] ADC1115S125_1 Preliminary data sheet Reference selection The voltage on pin VREF is doubled internally to generate the internal reference voltage. All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 15 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Figure 12 to Figure 15 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. VREF VREF 330 pF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa117 005aaa116 Fig 12. Internal reference, 2 V (p-p) full scale Fig 13. Internal reference, 1 V (p-p) full scale VREF V 0.1 μF VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE VDDA SENSE 005aaa119 005aaa118 Fig 14. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 15. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale 11.3.2 Reference gain control The reference gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see Table 21). The corresponding full-scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 12: Table 12. Reference SPI gain control INTREF Gain full scale (p-p) 000 0 dB 2V 001 −1 dB 1.78 V 010 −2 dB 1.59 V 011 −3 dB 1.42 V 100 −4 dB 1.26 V 101 −5 dB 1.12 V 110 −6 dB 1V 111 reserved x 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 μF filter capacitor should be connected between pin VCM and ground. 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INP and INM is set internally. The input buffer bias current can be set to one of three levels (high, medium or low) via the SPI (see Table 22). ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 16 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.4 Clock input 11.4.1 Drive modes The ADC1115S125 can be driven differentially (SINE, LVPECL or LVDS) with little or no degradation on dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor). CLKP LVCMOS clock input CLKP CLKM CLKM LVCMOS clock input 005aaa174 a. Rising edge LVCMOS 005aaa053 b. Falling edge LVCMOS Fig 16. LVCMOS single-ended clock input CLKP Sine clock input CLKP Sine clock input CLKM CLKM 005aaa173 a. Sine clock input 005aaa054 b. Sine clock input (with transformer) CLKP CLKP LVPECL clock input LVDS clock input CLKM 005aaa172 005aaa055 c. LVDS clock input CLKM d. LVPECL clock input1 Fig 17. Differential clock input ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 17 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. PACKAGE ESD PARASITICS CLKP Vcm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ CLKM 005aaa056 Fig 18. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI interface (see Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performances of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45% and 55%. 11.4.4 Clock input divider The ADC1115S125 contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see Table 20). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 18 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see Table 23). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 19. The buffer is powered by a separate OGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO PARASITICS LOGIC DRIVER ESD PACKAGE 50 Ω Dx OGND 005aaa057 Fig 19. CMOS digital output buffer The output resistance is 50 Ω and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 30): ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 19 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table 23). VCCO 3.5 mA typ − + DnP/Dn + 1P 100 Ω RECEIVER DnM/Dn + 1M − + OGND 005aaa058 Fig 20. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver side (Figure 20) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 21 and Table 32). VCCO 3.5 mA typ − + DxP/Dx + 1P 100 Ω RECEIVER DxM/Dx + 1M + − OGND 005aaa059 Fig 21. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic voltage levels. Table 13. ADC1115S125_1 Preliminary data sheet LVDS DDR output register 2 LVDS_INT_TER[2:0] Resistor value (Ω) 000 no internal termination 001 300 010 180 011 110 100 150 All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 20 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 13. LVDS DDR output register 2 …continued LVDS_INT_TER[2:0] Resistor value (Ω) 101 100 110 81 111 60 11.5.3 Data valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1115S125. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 4 and Figure 5 respectively. 11.5.4 Out-of-Range (OTR) An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1; see Table 29). In this mode, the latency of OTR is reduced to only four clock cycles. The Fast OTR detection threshold (below full scale) can be programmed via bits FASTOTR_DET[2:0]. Table 14. Fast OTR register FASTOTR_DET[2:0] Detection level (dB) 000 −20.56 001 −16.12 010 −11.02 011 −7.82 100 −5.49 101 −3.66 110 −2.14 111 −0.86 11.5.5 Digital offset By default, the ADC1115S125 delivers output code that corresponds to the analog input. However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET[5:0]; see Table 25). 11.5.6 Test patterns For test purposes, the ADC1115S125 can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected when TESTPAT_SEL[2:0] = 101. The selected test pattern will be transmitted regardless of the analog input. ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 21 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.5.7 Output codes versus input voltage Table 15. Output codes VINP − VINM Offset binary Two’s complement OTR pin < −1 000 0000 0000 100 0000 0000 1 −1.0000000 000 0000 0000 100 0000 0000 0 −0.9990234 000 0000 0001 100 0000 0001 0 −0.9980469 000 0000 0010 100 0000 0010 0 −0.9970703 000 0000 0011 100 0000 0011 0 −0.996093 000 0000 0100 100 0000 0100 0 .... .... .... 0 −0.0019531 011 1111 1110 111 1111 1110 0 −0.0009766 011 1111 1111 111 1111 1111 0 0.0000000 100 0000 0000 000 0000 0000 0 +0.0009766 100 0000 0001 000 0000 0001 0 +0.0019531 100 0000 0010 000 0000 0010 0 .... .... .... 0 +0.9960938 111 1111 1011 011 1111 1011 0 +0.9970703 111 1111 1100 011 1111 1100 0 +0.9980469 111 1111 1101 011 1111 1101 0 +0.9990234 111 1111 1110 011 1111 1110 0 +1.0000000 111 1111 1111 011 1111 1111 0 > +1 111 1111 1111 011 1111 1111 1 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1115S125 serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will be transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 17). Table 16. Instruction bytes for the SPI MSB ADC1115S125_1 Preliminary data sheet LSB Bit 7 6 5 4 3 2 1 0 Description R/W[1] W1[2] W0[2] A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 [1] Bit R/W indicates whether it is a read (1) or a write (0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 17). All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 22 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 17. Number of data bytes to be transferred after the instruction bytes W1 W0 Number of bytes transmitted 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes or more Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end on data transmission. CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Instruction bytes A1 A0 D7 D6 D5 D4 D3 D2 Register N (data) D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register N + 1 (data) 005aaa062 Fig 22. SPI mode timing 11.6.2 Default modes at start-up During circuit initialization, it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on CS will trigger a transition to SPI control mode. When the ADC1115S125 enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 23). Once in SPI control mode, the output data standard can be changed via bit LVDS/CMOS in Table 23. When the ADC1115S125 enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] in Table 23. ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 23 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 23. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 24. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 24 of 35 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 18. NXP Semiconductors ADC1115S125_1 Preliminary data sheet 11.6.3 Register allocation map Register allocation map Register name R/W Bit definition 0005 Reset and operating mode R/W SW_RST 0006 Clock R/W - - - 0008 Internal reference R/W - - 0010 Input buffer R/W - 0011 Output data standard. R/W 0012 Output clock 0013 Bit 7 Default Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RESERVED[2:0] Bit 1 - SE_SEL DIFF_SE - - - INTREF_EN - - - - - - - - LVDS_ CMOS OUTBUF OUTBUS_SWAP R/W - - - - DAVINV Offset R/W - - 0014 Test pattern 1 R/W - - 0015 Test pattern 2 R/W 0016 Test pattern 3 R/W TESTPAT_USER[2:0] - - 0017 Fast OTR R/W - - - - FASTOTR 0020 CMOS output R/W - - - - 0021 LVDS DDR O/P 1 R/W - - DAVI_x2_EN 0022 LVDS DDR O/P 2 R/W - - - Bit 0 Bin OP_MODE[1:0] CLKDIV DCS_EN INTREF[2:0] IB_IBIAS[1:0 ] - - DATA_FORMAT[1:0] DAVPHASE[2:0] TESTPAT_SEL[2:0] 0000 0000 0000 0000 - - - FASTOTR_DET[2:0] DAV_DRV[1:0] BIT_BYTE_WISE 0000 0000 0000 1110 TESTPAT_USER[10:3] - 0000 0011 0000 0000 - DAVI[1:0] 0000 0001 0000 0000 DIG_OFFSET[5:0] - 0000 0000 DATAI_x2_EN 0000 0000 0000 0000 DATA_DRV[1:0] 0000 1110 DATAI[1:0] 0000 0000 LVDS_INT_TER[2:0] 0000 0000 ADC1115S125 25 of 35 © NXP B.V. 2010. All rights reserved. - 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Rev. 01 — 12 April 2010 All information provided in this document is subject to legal disclaimers. Addr. Hex ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 19. Reset and operating mode control register (address 0005h) bit description Bit Symbol Access 7 SW_RST R/W Value Description reset digital section 0 no reset 1 performs a reset on SPI registers 6 to 4 RESERVED[2:0] 000 reserved 3 to 2 - 00 not used 1 to 0 OP_MODE[1:0] Table 20. Symbol 7 to 5 - 4 SE_SEL DIFF_SE 2 - 1 CLKDIV 0 operating mode 00 normal (Power-up) 01 Power-down 10 Sleep 11 normal (Power-up) Clock control register (address 0006h) bit description Bit 3 R/W DCS_EN ADC1115S125_1 Preliminary data sheet Access Value Description 000 not used R/W single-ended clock input pin select 0 CLKM 1 CLKP R/W differential/single ended clock input select 0 fully differential 1 single-ended 0 R/W not used clock input divide by 2 0 disabled 1 enabled R/W duty cycle stabilizer 0 disabled 1 enabled All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 26 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 21. Internal reference control register (address 0008h) bit description Bit Symbol 7 to 4 - 3 INTREF_EN 2 to 0 INTREF[2:0] Table 22. Value Description 0000 not used R/W programmable internal reference enable 0 disable 1 active R/W programmable internal reference 000 0 dB (FS = 2 V) 001 −1 dB (FS = 1.78 V) 010 −2 dB (FS = 1.59 V) 011 −3 dB (FS = 1.42 V) 100 −4 dB (FS = 1.26 V) 101 −5 dB (FS = 1.12 V) 110 −6 dB (FS = 1 V) 111 reserved Input buffer control register (address 0010h) bit description Bit Symbol 7 to 2 - 1 to 0 IB_IBIAS[1:0] Table 23. Access Value Description 000000 not used R/W input buffer bias current 00 not used 01 medium 10 low 11 high Output data standard control register (address 0011h) bit description Bit Symbol 7 to 5 - 4 LVDS_CMOS 3 Access OUTBUF Access Value Description 000 not used R/W output data standard: LVDS DDR or CMOS 0 CMOS 1 LVDS DDR R/W output buffers enable 0 1 2 1 to 0 OUTBUS_SWAP DATA_FORMAT[1:0] ADC1115S125_1 Preliminary data sheet R/W output enabled output disabled (high Z) output bus swapping 0 no swapping 1 output bus is swapped (MSB becomes LSB and vice versa) R/W output data format 00 offset binary 01 two’s complement 10 gray code 11 offset binary All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 27 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 24. Output clock register (address 0012h) bit description Bit Symbol 7 to 4 - 3 DAVINV 2 to 0 DAVPHASE[2:0] Table 25. Access Value Description 0000 not used R/W output clock data valid (DAV) polarity 0 normal 1 inverted R/W DAV phase select 000 output clock shifted (ahead) by 3 ns 001 output clock shifted (ahead) by 2.5 ns 010 output clock shifted (ahead) by 2 ns 011 output clock shifted (ahead) by 1.5 ns 100 output clock shifted (ahead) by 1 ns 101 output clock shifted (ahead) by 0.5 ns 110 default value as defined in timing section 111 output clock shifted (delayed) by 0.5 ns Offset register (address 0013h) bit description Bit Symbol 7 to 6 - 5 to 0 DIG_OFFSET[5:0] Access Value Description 00 not used R/W digital offset adjustment 011111 ... 000000 0 ... ... 100000 Table 26. −32 LSB Test pattern register 1 (address 0014h) bit description Bit Symbol 7 to 3 - 2 to 0 TESTPAT_SEL[2:0] Table 27. +31 LSB ... Access Value Description 00000 not used R/W digital test pattern select 000 off 001 mid scale 010 −FS 011 +FS 100 toggle ‘1111..1111’/’0000..0000’ 101 custom test pattern 110 ‘1010..1010.’ 111 ‘010..1010’ Test pattern register 2 (address 0015h) bit description Bit Symbol Access Value Description 7 to 0 TESTPAT_USER[10:3] R/W 00000000 custom digital test pattern (bits 10 to 3) ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 28 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 28. Test pattern register 3 (address 0016h) bit description Bit Symbol Access Value Description 7 to 5 TESTPAT_USER[2:0] R/W 000 custom digital test pattern (bits 2 to 0) 4 to 0 - 00000 not used Table 29. Fast OTR register (address 0017h) bit description Bit Symbol 7 to 4 - 3 FASTOTR 2 to 0 Value Description 0000 not used R/W FASTOTR_DET[2:0] Table 30. fast Out-of-Range (OTR) detection 0 disabled 1 enabled R/W set fast OTR detect level 000 −20.56 dB 001 −16.12 dB 010 −11.02 dB 011 −7.82 dB 100 −5.49 dB 101 −3.66 dB 110 −2.14 dB 111 −0.86 dB CMOS output register (address 0020h) bit description Bit Symbol 7 to 4 - 3 to 2 DAV_DRV[1:0] 1 to 0 Access DATA_DRV[1:0] ADC1115S125_1 Preliminary data sheet Access Value Description 0000 not used R/W drive strength for DAV CMOS output buffer 00 low 01 medium 10 high 11 very high R/W drive strength for DATA CMOS output buffer 00 low 01 medium 10 high 11 very high All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 29 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 31. LVDS DDR output register 1 (address 0021h) bit description Bit Symbol 7 to 6 - 5 DAVI_x2_EN 4 to 3 2 1 to 0 DAVI[1:0] DATAI_x2_EN DATAI[1:0] Table 32. Value Description 00 not used R/W double LVDS current for DAV LVDS buffer 0 disabled 1 enabled R/W LVDS current for DAV LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA R/W double LVDS current for DATA LVDS buffer 0 disabled 1 enabled R/W LVDS current for DATA LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA LVDS DDR output register 2 (address 0022h) bit description Bit Symbol 7 to 4 - 3 BIT/BYTE_WISE 2 to 0 Access LVDS_INTTER[2:0] ADC1115S125_1 Preliminary data sheet Access Value Description 0000 not used R/W DDR mode for LVDS output 0 bit wise (even data bits output on DAV rising edge / odd data bits output on DAV falling edge) 1 byte wise (MSB data bits output on DAV rising edge / LSB data bits output on DAV falling edge) R/W internal termination for LVDS buffer (DAV and DATA) 000 no internal termination 001 300 Ω 010 180 Ω 011 110 Ω 100 150 Ω 101 100 Ω 110 81 Ω 111 60 Ω All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 30 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A B D SOT618-6 terminal 1 index area E A A1 c detail X e1 1/2 e e 11 20 C C A B C v w b y1 C y L 21 10 e e2 Eh 1/2 e 1 terminal 1 index area 30 40 31 X Dh 0 2.5 scale Dimensions Unit A(1) A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 mm 5 mm c D(1) Dh E(1) Eh 0.2 6.1 6.0 5.9 4.55 4.40 4.25 6.1 6.0 5.9 4.55 4.40 4.25 e e1 0.5 4.5 e2 L v 4.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT618-6 References IEC JEDEC JEITA MO-220 --- sot618-6_po European projection Issue date 09-02-23 09-03-04 Fig 25. Package outline SOT618-6 (HVQFN40) ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 31 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 13. Revision history Table 33. Revision history Document ID Release date Data sheet status ADC1115S125_1 20100412 Preliminary data sheet - ADC1115S125_1 Preliminary data sheet Change Supersedes notice All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 - © NXP B.V. 2010. All rights reserved. 32 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 33 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ADC1115S125_1 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 © NXP B.V. 2010. All rights reserved. 34 of 35 ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 11.6.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics . . . . . . . . . . . . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Clock and digital output timing . . . . . . . . . . . . . 9 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 11 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI and Pin control modes . . . . . . . . . . . . . . . 11 Operating mode selection. . . . . . . . . . . . . . . . 12 Selecting the output data standard . . . . . . . . . 12 Selecting the output data format. . . . . . . . . . . 12 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System reference and power management . . 15 Internal/external references . . . . . . . . . . . . . . 15 Reference gain control . . . . . . . . . . . . . . . . . . 16 Common-mode output voltage (VO(cm)) . . . . . 16 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 17 Equivalent input circuit . . . . . . . . . . . . . . . . . . 18 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 18 Clock input divider . . . . . . . . . . . . . . . . . . . . . 18 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 19 Digital output buffers: CMOS mode . . . . . . . . 19 Digital output buffers: LVDS DDR mode . . . . . 20 Data valid (DAV) output clock . . . . . . . . . . . . . 21 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 21 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output codes versus input voltage . . . . . . . . . 22 Serial Peripheral Interface (SPI) . . . . . . . . . . . 22 Register description . . . . . . . . . . . . . . . . . . . . 22 Default modes at start-up . . . . . . . . . . . . . . . . 23 Register allocation map . . . . . . . . . . . . . . . . . 25 12 13 14 14.1 14.2 14.3 14.4 15 16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 33 33 33 33 34 34 35 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 April 2010 Document identifier: ADC1115S125_1