TEA1742T GreenChip PFC controller Rev. 01 — 10 February 2009 Objective data sheet 1. General description The TEA1742T is a controller for Power Factor Correction (PFC). Its high level of integration allows the design of a cost-effective power supply with a very low number of external components. The special built-in green functions provide high efficiency at all power levels. This applies to quasi-resonant operation at high power levels and quasi-resonant operation with valley skipping. The TEA1742T enables highly efficient and reliable supplies with power requirements of up to 500 W, to be designed easily and with the minimum number of external components. 2. Features 2.1 Distinctive features n Universal mains supply operation (70 V (AC) to 276 V (AC)) n Dual boost PFC with accurate output voltage (NXP patented) n High level of integration, resulting in a very low external component count and a cost-effective design n Low start-up supply voltage 2.2 Green features n Valley/zero voltage switching for minimum switching losses (NXP patented) n Frequency limitation to reduce switching losses n High ohmic resistive dividers possible to minimize losses 2.3 Protection features n n n n n n Safe restart mode for system fault conditions Continuous mode protection by means of demagnetization detection (NXP patented) Accurate OverVoltage Protection (OVP) Open control loop protection IC OverTemperature Protection (OTP) Low and adjustable OverCurrent Protection (OCP) trip level TEA1742T NXP Semiconductors GreenChip PFC controller 3. Applications n The device can be used in all applications that require an efficient and cost-effective PFC solution up to 500 W. PC power supplies in particular can benefit from the high level of integration and high efficiency 4. Ordering information Table 1. Ordering information Type number TEA1742T Package Name Description Version SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 2 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 5. Block diagram PFCDRIVER 7 PFC DRIVER 1.12 V PFC GATE 3.5 V DRV LOW VIN VINSENSE 2 MAX BOOST PFCCOMP 3 R PFC PROT PROT ENABLE PFC Q S 1.25 V VOSENSE 5 PFC OSC 3.7 V 2.50 V 8 µA VSTART VUVLO BOOST VoOVP PFC PROT OTP VoSHORT Vcc<4V START STOP PFC SMPS CONTROL LOW VIN S LATCHED R PROTECTION PROT OCP 6 PFCSENSE 500 mV BLANK VoSHORT VUVLO PFC DRIVER ENABLE PFC S SAFE R RESTART PROTECTION 60 µA SOFT START START STOP PFC TEMP PFCAUX 4 VALLEY DETECT OTP TIMER 4 µs PFCGATE INTERNAL SUPPLY ZCS VSTART TIMER 50 µs VUVLO 100 mV 1 GND Fig 1. 8 VCC 014aaa734 Block diagram TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 3 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 6. Pinning information 6.1 Pinning GND 1 VINSENSE 2 8 VCC 7 PFCDRIVER TEA1742T PFCCOMP 3 6 PFCSENSE PFCAUX 4 5 VOSENSE 014aaa735 Fig 2. Pin configuration: TEA1742T (SOT96-1) 6.2 Pin description Table 2. Pin description Symbol Pin Description GND 1 ground VINSENSE 2 sense input for mains voltage PFCCOMP 3 frequency compensation pin for PFC PFCAUX 4 input from auxiliary winding for demagnetization timing for PFC VOSENSE 5 sense input for PFC output voltage PFCSENSE 6 programmable current sense input for PFC PFCDRIVER 7 gate driver output for PFC VCC 8 supply voltage TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 4 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 7. Functional description 7.1 General control The TEA1742T contains a controller for a power factor correction circuit. A typical configuration is shown in Figure 3. 7 4 3 6 5 8 VCC TEA1742T 2 1 014aaa736 Fig 3. Typical configuration 7.1.1 Start-up and UnderVoltage LockOut (UVLO) The control logic activates the internal circuitry when the voltage on pin VCC passes the Vstartup level. First, the soft start capacitor on the PFCSENSE pin is charged. When the soft start capacitor on the PFCSENSE pin is charged, the PFC circuit is activated. See Figure 4. When one of the protection functions is activated, the converter stops switching. For a restart protection the VCC has to be pulled below Vth(UVLO) to reset the protection. For a latched protection (OTP), the VCC has to drop below about 4 V (typ). TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 5 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller VSTART VUVLO VCC Vstart(VINSENSE) Vstop(VINSENSE) VINSENSE soft start PFCSENSE PFCDRIVER VOSENSE apply starting mains and VCC converter normal operation protection restart 014aaa737 Fig 4. Start-up sequence, normal operation and restart sequence 7.1.2 Supply management All internal reference voltages are derived from a temperature compensated and trimmed on-chip band gap circuit. Internal reference currents are derived from a temperature compensated and trimmed on-chip current reference circuit. 7.1.3 OverTemperature Protection (OTP) An accurate internal temperature protection is provided in the circuit. When the junction temperature exceeds the thermal shut-down temperature, the IC stops switching. OTP is a latched protection. It can be reset by removing the voltage on pin VCC. 7.2 Power factor correction circuit The power factor correction circuit operates in quasi-resonant or discontinuous conduction mode with valley switching. The next primary stroke is only started when the previous secondary stroke has ended and the voltage across the PFC MOSFET has reached a minimum value. The voltage on the PFCAUX pin is used to detect transformer demagnetization and the minimum voltage across the external PFC MOSFET switch. 7.2.1 ton control The power factor correction circuit is operated in ton control. The resulting mains harmonic reduction of a typical application is well within the class-D requirements. TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 6 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 7.2.2 Valley switching and demagnetization (PFCAUX pin) The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the voltage across the PFC MOSFET. The next stroke is started if the voltage across the PFC MOSFET is at its minimum in order to reduce switching losses and ElectroMagnetic Interference (EMI) (valley switching). If no demagnetization signal is detected on the PFCAUX pin, the controller generates a Zero Current Signal (ZCS), 50 ms (typ) after the last PFCGATE signal. If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal 4 ms (typ) after demagnetization was detected. To protect the internal circuitry, for example during lightning events, it is advisable to add a 5 kΩ series resistor to this pin. To prevent incorrect switching due to external disturbance, the resistor should be placed close to the IC on the printed circuit board. 7.2.3 Frequency limitation To optimize the transformer and minimize switching losses, the switching frequency is limited to fsw(PFC)max. If the frequency for quasi-resonant operation is above the fsw(PFC)max limit, the system switches over to discontinuous conduction mode. Also here, the PFC MOSFET is only switched on at a minimum voltage across the switch (valley switching). 7.2.4 Mains voltage compensation (VINSENSE pin) The mathematical equation for the transfer function of a power factor corrector contains the square of the mains input voltage. In a typical application this results in a low bandwidth for low mains input voltages, while at high mains input voltages the Mains Harmonic Reduction (MHR) requirements may be hard to meet. To compensate for the mains input voltage influence, the TEA1742T contains a correction circuit. Via the VINSENSE pin the average input voltage is measured and the information is fed to an internal compensation circuit. With this compensation it is possible to keep the regulation loop bandwidth constant over the full mains input range, yielding a fast transient response on load steps, while still complying with class-D MHR requirements. In a typical application, the bandwidth of the regulation loop is set by a resistor and two capacitors on the PFCCOMP pin. 7.2.5 Soft start-up (pin PFCSENSE) To prevent audible transformer noise at start-up or during hiccup, the transformer peak current, IDM, is increased slowly by the soft start function. This can be achieved by inserting RSS1 and CSS1 between pin PFCSENSE and current sense resistor RSENSE1. An internal current source charges the capacitor to VPFCSENSE = Istart(soft)PFC × RSS1. The voltage is limited to Vstart(soft)PFC. The start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of RSS1 and CSS1. τsoftstart = 3 × R SS1 × C SS1 TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 7 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller The charging current Istart(soft)PFC flows as long as the voltage on pin PFCSENSE is below 0.5 V (typ). If the voltage on pin PFCSENSE exceeds 0.5 V, the soft start current source starts limiting the current Istart(soft)PFC. As soon as the PFC starts switching, the Istart(soft)PFC current source is switched off; see Figure 5. Istartup(soft)PFC ≤ 60 µA S1 SOFT START CONTROL RSS1 11 PFCSENSE CSS1 RSENSE1 OCP 0.5 V 014aaa157 Fig 5. Soft start-up of PFC 7.2.6 Dual boost PFC The PFC output voltage is modulated by the mains input voltage. The mains input voltage is measured via the VINSENSE pin. The current is sourced from the VOSENSE pin if the voltage on the VINSENSE pin drops below 2.2 V (typ). To ensure the stability of the switch-over 200 mV is inserted around the 2.2 V, see Figure 6. For low VINSENSE input voltages, the output current is 8 mA (typ). This output current, in combination with the resistors on the VOSENSE pin, sets the lower PFC output voltage level at low mains voltages. At high mains input voltages the current is switched to zero. The PFC output voltage will then be at its maximum. As this current is zero in this situation, it does not effect the accuracy of the PFC output voltage. For proper switch-off behavior, the VOSENSE current is switched to its maximum value, 8 mA (typ), as soon as the voltage on pin VOSENSE drops below 2.1 V (typ). 2.2 V VVINSENSE −8 µA II(VOSENSE) 014aaa738 Fig 6. Voltage to current transfer function for dual boost PFC TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 8 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 7.2.7 Overcurrent protection (PFCSENSE pin) The maximum peak current is limited cycle-by-cycle by sensing the voltage across an external sense resistor, RSENSE1, on the source of the external MOSFET. The voltage is measured via the PFCSENSE pin. 7.2.8 Mains undervoltage lockout / brownout protection (VINSENSE pin) To prevent the PFC from operating at very low mains input voltages, the voltage on the VINSENSE pin is sensed continuously. As soon as the voltage on this pin drops below the Vstop(VINSENSE) level, switching of the PFC is stopped. The voltage on pin VINSENSE is clamped to a minimum value, Vstart(VINSENSE) + ∆Vpu(VINSENSE), for a fast restart as soon as the mains input voltage is restored after a mains dropout. 7.2.9 Overvoltage protection (VOSENSE pin) To prevent output overvoltage during load steps and mains transients, an overvoltage protection circuit is built in. As soon as the voltage on the VOSENSE pin exceeds the Vovp(VOSENSE) level, switching of the power factor correction circuit is inhibited. Switching of the PFC recommences as soon as the VOSENSE pin voltage drops below the VOVP(VOSENSE) level again. When the resistor between pin VOSENSE and ground is open, the overvoltage protection is also triggered. 7.2.10 PFC open-loop protection (VOSENSE pin) The power factor correction circuit does not start switching until the voltage on the VOSENSE pin is above the Vth(ol)(VOSENSE) level. This protects the circuit from open-loop and VOSENSE short situations. 7.2.11 Driver (pin PFCDRIVER) The driver circuit to the gate of the power MOSFET has a current sourcing capability of typically −500 (TBF) mA and a current sink capability of typically 1.2 (TBF) A. This permits fast turn-on and turn-off of the power MOSFET for efficient operation. 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Voltages VCC supply voltage −0.4 +38 V VPFCCOMP voltage on pin PFCCOMP −0.4 +5 V VVINSENSE voltage on pin VINSENSE −0.4 +5 V VVOSENSE voltage on pin VOSENSE −0.4 +5 V VPFCAUX voltage on pin PFCAUX −25 +25 V −0.4 +5 V VPFCSENSE voltage on pin PFCSENSE current limited TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 9 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller Table 3. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit −1 +10 mA duty cycle < 10 % −0.8 +2 A Tamb < 75 °C - 0.45 W Currents IPFCSENSE current on pin PFCSENSE IPFCDRIVER current on pin PFCDRIVER General Ptot total power dissipation Tstg storage temperature −55 +150 °C Tj junction temperature −20 +150 °C ESD VESD electrostatic discharge voltage class 1 human body model [1] - 2000 V machine model [2] - 200 V - 500 V charged device model [1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. [2] Equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω resistor. 9. Thermal characteristics Table 4. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air; JEDEC test board 150 K/W 10. Characteristics Table 5. Characteristics Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply voltage management (pin VCC) Vstartup start-up voltage 10.6 V Vth(UVLO) undervoltage lockout threshold voltage 10.3 V Vhys hysteresis voltage Vstartup − Vth(UVLO) 0.3 V ICC(oper) operating supply current no load on pin PFCDRIVER <tbd> - mA Vrst(latch) latched reset voltage 4 V - Input Voltage Sensing PFC (pin VINSENSE) Vstop(VINSENSE) stop voltage on pin VINSENSE 0.86 0.89 0.92 V Vstart(VINSENSE) start voltage on pin VINSENSE 1.11 1.15 1.19 V ∆Vpu(VINSENSE) pull-up voltage difference on pin VINSENSE - −100 - mV active after Vstop(VINSENSE) is detected TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 10 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller Table 5. Characteristics …continued Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Ipu(VINSENSE) pull-up current on pin VINSENSE active after Vstop(VINSENSE) is detected −55 −47 −40 µA Vmvc(VINSENSE)max maximum mains voltage compensation voltage on pin VINSENSE 4.0 - - V II(VINSENSE) input current on pin VINSENSE VINSENSE > Vstop(VINSENSE) after Vstart(VINSENSE) is detected 5 33 100 nA Vbst(dual) dual boost voltage current switch-over point - 2.2 - V switch-over region - 200 - mV Loop compensation PFC (pin PFCCOMP) gm transconductance VVOSENSE to IO(PFCCOMP) 60 80 100 µA/V IO(PFCCOMP) output current on pin PFCCOMP VVOSENSE = 2.0V 33 39 45 µA Vclamp(PFCCOMP) −45 −39 −33 µA Low power mode, PFC off, lower clamp voltage [1] 2.5 2.7 2.9 V Upper clamp voltage [1] - 3.9 - V VVOSENSE = 3.3V clamp voltage on pin PFCCOMP Vton(PFCCOMP)zero zero on-time voltage on pin PFCCOMP 3.4 3.5 3.6 V Vton(PFCCOMP)max maximum on-time voltage on pin PFCCOMP 1.20 1.25 1.30 V VVINSENSE = 3.3 V, VPFCCOMP = Vton(PFCCOMP)max 3.6 4.5 5.0 µs VVINSENSE = 0.9 V, VPFCCOMP = Vton(PFCCOMP)max 30 40 53 µs - 1.15 - V Pulse width modulator PFC ton(PFC) PFC on-time Output voltage sensing PFC (pin VOSENSE) Vth(ol)(VOSENSE) open-loop threshold voltage on pin VOSENSE Vreg(VOSENSE) regulation voltage on pin VOSENSE Vovp(VOSENSE) overvoltage protection voltage on pin VOSENSE Ibst(dual) dual boost current for IO(PFCCOMP) = 0 2.475 2.500 2.525 V 2.60 2.63 2.67 V VVINSENSE < Vbst(dual) or VVOSENSE < 2.1 V - -8 - µA VVINSENSE > Vbst(dual) - -30 - nA 0.49 0.52 0.55 V Overcurrent protection PFC (pin PFCSENSE) ∆V/∆t = 50 mV/µs Vsense(PFC)max maximum PFC sense voltage 0.51 0.54 0.57 V tleb(PFC) PFC leading edge blanking time 250 310 370 ns Iprot(PFCSENSE) protection current on pin PFCSENSE −50 - −5 nA ∆V/∆t = 200 mV/µs TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 11 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller Table 5. Characteristics …continued Tamb = 25 °C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit −75 −60 −45 µA 0.46 0.50 0.54 V Soft start PFC (pin PFCSENSE) Istart(soft)PFC PFC soft start current Vstart(soft)PFC PFC soft start voltage Rstart(soft)PFC PFC soft start resistance 12 - - kΩ fsw(PFC)max maximum PFC switching frequency 100 125 150 kHz toff(PFC)min minimum PFC off-time 1.1 1.4 1.7 µs - - 1.7 V/µs - - 50 ns 3 4 6 µs enabling voltage Oscillator PFC Valley switching PFC (pin PFCAUX) (∆V/∆t)vrec(PFC) PFC valley recognition voltage change with time tvrec(PFC) PFC valley recognition time tto(vrec)PFC PFC valley recognition time-out time VPFCAUX = 1 V peak-peak [2] Demagnetization management PFC (pin PFCAUX) Vth(comp)PFCAUX comparator threshold voltage on pin PFCAUX −150 −100 −50 mV tto(demag)PFC PFC demagnetization time-out time 40 50 60 µs Iprot(PFCAUX) protection current on pin PFCAUX VPFCAUX = 50 mV −75 - −5 nA Driver (pin PFCDRIVER) Isrc(PFCDRIVER) source current on pin PFCDRIVER VPFCDRIVER = 2 V - −0.5 TBF - A Isink(PFCDRIVER) sink current on pin PFCDRIVER VPFCDRIVER = 2 V - 0.7 TBF - A VPFCDRIVER = 10 V - 1.2 TBF - A - 11 12 V VO(PFCDRIVER)max maximum output voltage on pin PFCDRIVER Temperature protection Tpl(IC) IC protection level temperature 130 140 150 °C Tpl(IC)hys hysteresis of IC protection level temperature - 10 - °C [1] For a typical application with a compensation network on pin PFCCOMP, like the example in Figure 3. [2] Minimum required voltage change time for valley recognition on pin PFCAUX. TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 12 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 11. Application information Capacitor CVCC buffers the IC supply voltage, which has to be supplied by external means. Sense resistor RSENSE1 converts the current through the MOSFET S1 into a voltage at pin PFCSENSE. The value of RSENSE1 defines the maximum primary peak current in MOSFETS S1. RS1 is added to prevent the soft start capacitor from being charged during normal operation due to negative voltage spikes across the sense resistor. Resistor RAUX1 is added to protect the IC from damage during lightning events. D1 C BUS S1 CSS1 RSS1 RSENSE1 RAUX1 RS1 7 COMPENSATION 6 5 4 8 CVCC 3 TEA1742T 2 1 014aaa739 Fig 7. Typical application diagram TEA1742T TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 13 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 12. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Package outline SOT96-1 (SO8) TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 14 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 13. Revision history Table 6. Revision history Document ID Release date Data sheet status Change notice Supersedes TEA1742T_1 20090210 Objective data sheet - - TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 15 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP B.V. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TEA1742T_1 Objective data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 10 February 2009 16 of 17 TEA1742T NXP Semiconductors GreenChip PFC controller 16. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.2.1 7.2.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Distinctive features . . . . . . . . . . . . . . . . . . . . . . 1 Green features . . . . . . . . . . . . . . . . . . . . . . . . . 1 Protection features . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 General control . . . . . . . . . . . . . . . . . . . . . . . . . 5 Start-up and UnderVoltage LockOut (UVLO) . . 5 Supply management. . . . . . . . . . . . . . . . . . . . . 6 OverTemperature Protection (OTP) . . . . . . . . . 6 Power factor correction circuit. . . . . . . . . . . . . . 6 ton control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Valley switching and demagnetization (PFCAUX pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2.3 Frequency limitation . . . . . . . . . . . . . . . . . . . . . 7 7.2.4 Mains voltage compensation (VINSENSE pin). 7 7.2.5 Soft start-up (pin PFCSENSE) . . . . . . . . . . . . . 7 7.2.6 Dual boost PFC . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2.7 Overcurrent protection (PFCSENSE pin) . . . . . 9 7.2.8 Mains undervoltage lockout / brownout protection (VINSENSE pin). . . . . . . . . . . . . . . . 9 7.2.9 Overvoltage protection (VOSENSE pin) . . . . . . 9 7.2.10 PFC open-loop protection (VOSENSE pin) . . . 9 7.2.11 Driver (pin PFCDRIVER) . . . . . . . . . . . . . . . . . 9 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 Thermal characteristics. . . . . . . . . . . . . . . . . . 10 10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 Application information. . . . . . . . . . . . . . . . . . 13 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15 Contact information. . . . . . . . . . . . . . . . . . . . . 16 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 February 2009 Document identifier: TEA1742T_1