TFA9812 BTL stereo Class-D audio amplifier with I2S input Rev. 01 — 30 October 2008 Preliminary data sheet 1. General description The TFA9812 is a high-efficiency Bridge Tied Load (BTL) stereo Class-D audio amplifier with a digital I2S audio input. It is available in a HVQFN48 package with exposed die paddle. The exposed die paddle technology enhances the thermal and electrical performances of the device. The TFA9812 features digital sound processing and audio power amplification. It supports I2C control mode and Legacy mode. In Legacy mode I2C involvement is not needed because the key features are controlled by hardware pin connections. A continuous time output power of 2 × 12 W (RL = 8 Ω, VDDP = 15 V) is supported without an external heat sink. Due to the implementation of a programmable thermal foldback even for high supply voltages, higher ambient temperatures, and/or lower load impedances, the device operates without sound interrupting behavior. TFA9812 is designed in such a way that it starts up easily (no special power-up sequence required). It features various soft and hard impact protection mechanisms to ensure an application that is both user friendly and robust. A modulation technique is applied for the TFA9812, which supports common mode choke approach (1 common mode choke only per BTL amplifier stage). This minimizes the number of external components. 2. Features 2.1 General features n n n n n n n n n n n n n n 3.3 V and 8 V to 20 V external power supply High efficiency and low power dissipation Speaker outputs fully short circuit proof across load, to supply lines and ground Pop noise free at power-up/power-down and sample rate switching Low power sleep mode Overvoltage and undervoltage protection on the 8 V to 20 V power supply Undervoltage protection on the 3.3 V power supply Overcurrent protection (no audible interruptions) Overdissipation protection Thermally protected and programmable thermal foldback Clock error protection I2C mode control or Legacy mode (i.e. no I2C) control Four different I2C addresses supported Internal Phase-Locked Loop (PLL) without using external components TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input n n n n n No high system clock required (PLL is able to lock on BCK) No external heat sink required 5 V tolerant digital inputs Supports dual coil inductor application Easy application and limited external components required 2.2 DSP features n n n n n n n n n n n Digital parametric 10-band equalizer Digital volume control per channel Selectable +24 dB gain boost Analog interface to digital volume control in Legacy mode Digital clip level control Soft and hard mute Thermal foldback threshold temperature control De-emphasis Output power limiting control Polarity switch Four Pulse Width Modulation (PWM) switching frequency settings 2.3 Audio data input interface format support n n n n n Master or slave Master Clock (MCLK), Bit Clock (BCK) and Word Select (WS) signals Philips I2S, standard I2S Japanese I2S, Most Significant Bit (MSB) justified Sony I2S, Least Significant Bit (LSB) justified Sample rates from 8 kHz to 192 kHz 3. Applications n n n n n n Digital-in Class-D audio amplifier applications CRT and flat-panel television sets Flat-panel monitors Multimedia systems Wireless speakers Docking stations for MP3 players TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 2 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 4. Quick reference data Table 1. Quick reference table Unless specified otherwise, VDDA = VDDP = 12 V, VSSP1 = VSSP2 = 0 V, VDDA(3V3) = VDDD(3V3) = 3.3 V, VSS1 = VSS2 = REFD = REFA = 0 V, Tamb = 25 °C, RL = 8 Ω, fi = 1 kHz, fs = 44.1 kHz, fsw = 400 kHz, 24-bit I2S input data, MCLK clock mode, typical application diagram (Figure 13). Symbol Parameter Conditions Min Typ Max Unit General VDDA analog supply voltage 8 12 20 V VDDP power supply voltage 8 12 20 V VDDA(3V3) analog supply voltage (3.3 V) 3.0 3.3 3.6 V VDDD(3V3) digital supply voltage (3.3 V) 3.0 3.3 3.6 V IP supply current IDDA(3V3) analog supply current (3.3 V) soft mute mode, with load, filter and snubbers connected [1] - 38 45 mA sleep mode [1] - 160 270 µA I2S slave mode - 2 4 mA I2S - 4 6 mA VDDA = VDDP = 12 V - 120 - µA VDDA = VDDP = 1 V - 40 70 µA I2S slave mode - 15 25 mA I2S - 25 40 mA - 4 30 µA operating mode master mode sleep mode IDDD(3V3) digital supply current (3.3 V) operating mode master mode sleep mode; DATA = WS = BCK = MCLK = 0 V Po(RMS) RMS output power Continuous time output power per channel; THD = 10 %; RL = 8 Ω VDDA = VDDP = 12 V - 8.3 - W VDDA = VDDP = 13.5 V - 10 - W VDDA = VDDP = 15 V - 12 - W Short time (≤ 10 s) output power per channel; THD = 10 %; RL = 8 Ω VDDA = VDDP = 17 V ηpo [1] output power efficiency RL = 8 Ω; Po(RMS) = 8.3 W 15 - W - 88 - % IP is the current through the analog supply voltage (VDDA) pin added to the current through the power supply voltage (VDDP) pin. TFA9812_1 Preliminary data sheet - © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 3 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 5. Ordering information Table 2. Ordering information Type number TFA9812HN Package Name Description Version HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 × 7 × 0.85 mm SOT619-8 TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 4 of 66 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TEST1 TEST2 AVOL 43 32 7 VDDD(3V3) VDDA(3V3) 40 3 VDDA 6 15 18, 19 REGISTER ADDRESS HEX 01 PHASED LOCKED LOOP XTALIN 1 XTALOUT 2 CLOCK PROTECTION LP UFP OFP IBP OSCILLATOR MCLK 47 1 TFA9812 DRIVER LOW PWM CONTROLLER STAB1 DRIVER HIGH 23, 24 OUT1N INTERPOLATION FILTER AND DE-EMPHASIS GAIN 26, 27 VSSP1 28 STAB1 POWER LIMITER 22 BOOT2P VDDP DRIVER HIGH 20, 21 OUT2P CONTROL LOGIC DRIVER LOW PWM CONTROLLER POWERUP 31 STAB2 ENABLE 33 VSSP2 12 BOOT2N VDDP GAIN 34 CSEL 35 ADSEL2/PLIM2 36 ADSEL1/PLIM1 37 CONTROL INTERFACE SCL/SFOR 38 DRIVER HIGH 13, 14 OUT2N CONTROL LOGIC REFERENCES DRIVER LOW VSSP2 9 29 DIAG Fig 1. TFA9812 block diagram 41 42 CDELAY STABD REFD 30 4 STABA 5 REFA 8 EXPOSED DIE PADDLE VSS1 STAB2 48 VSS2 010aaa217 TFA9812 5 of 66 © NXP B.V. 2008. All rights reserved. SDA/MS 39 PROTECTION OVP UVP OCP OTP ODP WP BTL stereo Class-D audio amplifier with I2S input Rev. 01 — 30 October 2008 VOLUME CONTROL AND SOFT MUTE 10-BAND PARAMETRIC EQUALIZER 25 BOOT1N VDDP DRIVER LOW SERIAL AUDIO DATA 44 INTERFACE 10, 11 VSSP2 CSEL CONTROL LOGIC WS 45 VDDP 16, 17 OUT1P CONTROL LOGIC THERMAL FOLDBACK BCK 46 BOOT1P DRIVER HIGH ADC 0 NXP Semiconductors TFA9812_1 Preliminary data sheet 6. Block diagram TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Figure 1 shows the block diagram of the TFA9812. For a detailed description of the audio signal path see Section 8.1. 7. Pinning information 37 ADSEL1/PLIM1 38 SCL/SFOR 40 VDDD(3V3) 39 SDA/MS 41 STABD 42 REFD 43 TEST2 44 DATA 45 WS 46 BCK terminal 1 index area 47 MCLK 48 VSS2 7.1 Pinning XTALIN 1 36 ADSEL2PLIM2 XTALOUT 2 35 CSEL VDDA(3V3) 3 34 TEST3 STABA 4 33 ENABLE REFA 5 32 AVOL VDDA 6 TEST1 7 VSS1 8 29 DIAG STAB2 9 28 STAB1 31 POWERUP TFA9812HN 30 CDELAY VSSP2 10 27 VSSP1 VSSP2 11 26 VSSP1 OUT1N 24 OUT1N 23 BOOT1P 22 OUT1P 21 OUT1P 20 VDDP 19 VDDP 18 OUT2P 17 OUT2P 16 BOOT2P 15 OUT2N 14 25 BOOT1N OUT2N 13 BOOT2N 12 010aaa218 Transparent top view Fig 2. Table 3. Pin configuration, transparent top view Pinning description TFA9812 Pin Symbol Type Description 1 XTALIN I Crystal oscillator input 2 XTALOUT O Crystal oscillator output 3 VDDA(3V3) P Analog supply voltage (3.3 V) 4 STABA O 1.8 V analog stabilizer output 5 REFA P Analog reference voltage 6 VDDA P Analog supply voltage (8 V to 20 V) 7 TEST1 I Test signal input 1. For test purposes only (connect to VSS) 8 VSS1 P PCB ground reference 9 STAB2 O Decoupling of internal 11 V regulator for channel 2 drivers 10 VSSP2 P Negative power supply voltage for channel 1 and channel 2 11 VSSP2 P Negative power supply voltage for channel 1 and channel 2 12 BOOT2N O Bootstrap high-side driver negative PWM output channel 2 13 OUT2N O Negative PWM output channel 2 TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 6 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 3. Pinning description TFA9812 …continued Pin Symbol Type Description 14 OUT2N O Negative PWM output channel 2 15 BOOT1P O Bootstrap high-side driver positive PWM output channel 1 16 OUT1P O Positive PWM output channel 1 17 OUT1P O Positive PWM output channel 1 18 VDDP P Positive power supply voltage (8 V to 20 V) 19 VDDP P Positive power supply voltage (8 V to 20 V) 20 OUT2P O Positive PWM output channel 2 21 OUT2P O Positive PWM output channel 2 22 BOOT2P O Bootstrap high-side driver positive PWM output channel 2 23 OUT1N O Negative PWM output channel 1 24 OUT1N O Negative PWM output channel 1 25 BOOT1N O Bootstrap high-side driver negative PWM output channel 1 26 VSSP1 P Negative power supply voltage for channel 1 and channel 2 27 VSSP1 P Negative power supply voltage for channel 1 and channel 2 28 STAB1 O Decoupling of internal 11 V regulator for channel 1 drivers 29 DIAG O Fault mode indication output (open-drain pin) 30 CDELAY I Timing reference 31 POWERUP I Power-up pin to switch between Sleep and other operational modes 32 AVOL I Analog volume control (Legacy mode) 33 ENABLE I Enable input to switch between 3-state and other operational modes 34 GAIN I Gain selection input to select between 0 dB and +24 dB gain (Legacy mode) 35 CSEL I Control selection input to select between Legacy mode (no I2C bus control) and I2C bus control 36 ADSEL2/PLIM2 I Address selection in I2C mode input 2, power limiter selection input 2 in Legacy mode 37 ADSEL1/PLIM1 I Address selection in I2C mode input 1, power limiter selection input 1 in Legacy mode 38 SCL/SFOR I I2C bus clock input in I2C mode, I2S serial data format selection input in Legacy mode 39 SDA/MS I/O I2C bus data input and output in I2C mode, master/slave selection input in Legacy mode 40 VDDD(3V3) P Digital supply voltage (3.3 V) 41 STABD O 1.8 V digital stabilizer output 42 REFD P Digital reference voltage 43 TEST2 I Test signal input 2; for test purposes only (connect to VSS) 44 DATA I I2S bus data input 45 WS I/O I2S bus word select input (I2S slave mode) or output (I2S master mode) 46 BCK I/O I2S bus bit clock input (I2S slave mode) or output (I2S master mode) TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 7 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 3. Pinning description TFA9812 …continued Pin Symbol Type Description 47 MCLK I/O Master clock input (I2S slave mode) or output (I2S master mode) 48 VSS2 P PCB ground reference P PCB ground reference Exposed die-paddle 8. Functional description 8.1 General The TFA9812 is a high-efficiency stereo BTL Class-D amplifier with a digital I2S audio input. It supports all commonly used I2S formats. Figure 1 shows the functional block diagram, which includes the key function blocks of the TFA9812. In the digital domain the audio signal is processed and converted to a pulse width modulated signal using BD modulation. A BTL configured power comparator carries out power amplification. The audio signal processing path is as follows: 1. The Digital Audio Input (DAI) block translates the I2S (-like) input signal into a standard internal stereo audio stream. 2. The 10-band parametric equalizer can optionally equalize the stereo audio stream. Both channels have separate equalization streams. It can be used for speaker transfer curve compensation to optimize the audio performance of applied speakers. 3. Volume control in the TFA9812 is done by attenuation. The attenuation depends on the volume control settings and the thermal foldback value. Soft mute is also arranged at this part. In Legacy mode the volume control is done by an on-board Analog-to-Digital Converter (ADC) which measures the analog voltage on pin 32. 4. The interpolation filter interpolates from 1 fs to the PWM controller sample rate (2048 fs at 44.1 kHz) by cascading FIR filters. 5. The gain block can boost the signal with 0 dB or +24 dB. Four specific gain settings are also provided in this block. These specific gain settings are related to maximum clip levels of < 0.5 %, 10 %, 20 % or 30 % THD at the TFA9812 output. These maximum clip levels are only valid with the gain boost set to 0 dB and a 0 dBFS input signal. 6. The power limiter limits the maximum output signal of the TFA9812. The power limiter settings are 0 dB, −1.5 dB, −3 dB, and −4.5 dB. This function can be used to reduce the maximum output power delivered to the speakers at a fixed supply voltage and speaker impedance. 7. The PWM controller block transforms the audio signal into a BD-modulated PWM signal. The BD-modulation provides a high signal-to-noise performance and eliminates clock jitter noise. 8. Via four differential comparators the PWM signals are amplified by two BTL power output stages. By default the left audio signal is connected to channel 1 and the right audio signal to channel 2. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 8 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input The block control defines the operational control settings of the TFA9812 in line with the actual I2C settings and the pin-controlled settings. The PLL block creates the system clock and can take the I2S BCK, the MCLK or an external crystal as reference source. The following protections are built into the TFA9812: • • • • • • • • • • • • Thermal Foldback (TF) OverTemperature Protection (OTP) OverCurrent Protection (OCP) OverVoltage Protection (OVP) UnderVoltage Protection (UVP) Window Protection (WP) Lock Protection (LP) UnderFrequency Protection (UFP) OverFrequency Protection (OFP) Invalid BCK Protection (IBP) DC-blocking ElectroStatic Discharge (ESD) 8.2 Functional modes 8.2.1 Control modes The two control modes of the TFA9812 are I2C and legacy. • In I2C mode the I2C format control is enabled. • In Legacy mode a pin-based subset of the control options is available. The control settings for features which are not available in Legacy mode are set to the default I2C register settings. The control mode is selected via pin CSEL as shown in Table 4. Table 4. Control mode selection CSEL Pin value Control mode 0 Legacy (no I2C) 1 I2C In the functional descriptions below the control for the various functions will be described for each control mode. Section 9.6 summarizes the support given by each control mode for the various TFA9812 functions. 8.2.2 Key operating modes There are six key operating modes: • In Sleep mode the voltage supplies are present, but power consumption for the whole device is reduced to the minimum level. The output stages in Sleep mode are 3-state and I2C communication is disabled. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 9 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input • In Soft mute mode the I2S input signal is overruled with a soft mute. – In Legacy control mode the analog input pin AVOL controls Soft mute mode. – In I2C control mode I2C control can be used to enable an automatic soft mute function. See also Section 8.5.3. • In Hard mute mode the PWM controller is overruled with a 50 % duty cycle square pulse. The Hard mute mode is only available in I2C control mode. • In Operating mode the TFA9812 amplifies the I2S audio input signal in line with the actual control setting. • In 3-state mode the output stages are switched off. • Fault mode is entered when a fault condition is detected by one or more of the protection mechanisms implemented in the TFA9812. In Fault mode the actual device configuration depends on the fault detected: see Section 8.7 for more information. Fault mode is for a subset of the faults flagged on the DIAG output pin. When the DIAG pin is flagged the output stages will be forced to enter 3-state mode. In Sleep mode the DIAG pin will not flag fault modes. Table 5. Operational mode selection Pin: DIAG Output Operational mode selected: POWERUP ENABLE CSEL AVOL 0 - - - floating Sleep mode 1 - - - 0 / floating Fault mode (enabled by system)[1] 1 1 1 - floating Soft mute mode (in I2C control mode)[2] 1 1 0 < 0.8 V floating Soft mute (in Legacy control mode) 1 0 - - floating 3-state mode 1 1 - - floating Operational mode [1] Clocking faults do not trigger DIAG output. [2] Under these conditions soft mute still has to be enabled by the appropriate I2C setting. 8.2.3 I2S master/slave modes and MCLK/BCK clock modes The I2S interface can be set in master or in slave. • In I2S master mode the PLL locks to the output signal of the internal crystal oscillator circuit which uses an external crystal. The BCK, WS and MCLK signals are generated by the TFA9812. On the MCLK pin the TFA9812 delivers a master clock running at the crystal frequency. • In I2S slave mode the PLL can lock to: – The external MCLK signal on the MCLK pin called MCLK clock mode. – The I2S input BCK signal on the BCK pin called BCK clock mode. The I2S master or slave mode can be selected: • In I2C control mode by selecting the right I2C setting. • In legacy control mode by selecting the right setting on the SDA/MS pin. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 10 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 6. I2S master/slave mode selection Pin value Clock mode I2S mode CSEL SDA/MS 0 0 legacy slave 0 1 legacy master - I2 C slave or master[1] 1 [1] Under these conditions the mode is enabled by the appropriate I2C setting. In I2S slave mode selection between BCK and MCLK clock modes is automatic. MCLK clock mode is given higher priority than BCK. If the MCLK clock is judged valid by the protection circuit then MCLK clock mode is enabled. BCK clock mode is enabled when the MCLK clock is invalid (e.g. not available) and the BCK clock is judged valid by the protection circuit (see Section 8.7.11). Table 7 shows the supported crystal frequencies in I2S master mode. Table 8 shows the supported MCLK frequencies in MCLK mode (I2S slave mode). Table 9 shows the supported BCK frequencies in BCK mode (I2S slave mode). Table 7. Valid crystal frequencies in I2S master mode Control mode fs (kHz) Crystal frequency (MHz) I2C 8, 16, 32, 64, 128 8.192 11.025, 22.05, 44.1, 88.2, 176.4 11.2896 12, 24, 48, 96, 192 12.288 32 8.192 44.1 11.2896 48 12.288 Legacy Table 8. Valid MCLK frequencies in I2S slave mode Control mode fs (kHz) MLCK frequency (MHz) I2C 8, 16, 32, 64, 128 8.192 12.288 32 18.432 (576 fs) 11.025, 22.05, 44.1, 88.2, 176.4 11.2896 44.1 25.4016 (576 fs) 12, 24, 48, 96, 192 16.9344 12.288 18.432 48 TFA9812_1 Preliminary data sheet 27.648 (576 fs) © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 11 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 8. Valid MCLK frequencies in I2S slave mode Control mode fs (kHz) MLCK frequency (MHz) Legacy 32 8.192 12.288 18.432 (576 fs) 44.1 11.2896 16.9344 25.4016 (576 fs) 48 12.288 18.432 27.648 (576 fs) Table 9. Valid BCK frequencies in I2S slave mode Control mode I2C Legacy [1] fs (kHz) 8 to 32 fs 8 to 192[1] 48 fs 8 to 192[1] 64 fs 32, 44.1, 48 32 fs 32, 44.1, 48 48 fs 32, 44.1, 48 64 fs The valid sample frequencies are shown in Section 9.5.7. TFA9812_1 Preliminary data sheet BCK (x fs input) 192[1] © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 12 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 8.3 Power-up/power-down external voltage supplies POWERUP pin ENABLE pin I2C available soft mute setting in I2C mode AVOL pin in Legacy mode PWM outputs Operating mode active twake td(on) td(mute_off) td(soft_mute) 010aaa219 Fig 3. Power-up/power-down timing 8.3.1 Power-up Figure 3 and Table 10 describe the power-up timing while Table 11 shows the pin control for initiating a power-up reset. Table 10. Power-up/power-down timing Symbol Parameter Conditions Min Typ Max Unit twake wake-up time I2C control - 4 - ms td(on) turn-on delay time - 70 - 135 ms td(mute_off) mute off delay time - - - 128/fs s td(soft_mute) Soft mute delay time I2C control - - 128/fs s legacy control[1] - 15 - ms [1] Mute in Legacy mode is controlled by AVOL pin. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 13 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input In I2C control mode communication is enabled after 4 ms. The preferred I2C settings can be made within 66 ms before the PLL starts running. Finally, the output stages are enabled and the audio level is increased via a demute sequence if mute has previously been disabled. Remark: In I2C mode soft mute is enabled by default. It can be disabled at any time while I2C communication is valid. In order to prevent audio clicks volume control (default setting is 0 dB) should be set before soft mute is disabled. Remark: For a proper start-up in I2S master mode and I2C mode the following sequence should be followed: 1. The I2S master setting should be set and keep the default sample rate setting active. 2. Next, another sample rate setting than the default one should be selected. 3. Finally, when the default sample rate is used the default sample rate setting should be selected again. 8.3.2 Power-down Figure 3 includes the power-down timing while Table 11 shows the pin control for enabling power-down. Table 11. Power-up/power-down selection Power-up pin value Description 0 Power-down (Sleep mode) 1 Power-up Putting the TFA9812 into power-down is equivalent to enabling Sleep mode (see Section 8.2.2). This mode is entered immediately and no additional clock cycles are required. In order to prevent audible clicks, soft mute should be enabled at least Td(soft_mute) seconds before enabling Sleep mode. The specified low current and power conditions in Table 1 are valid within 10 µs after enabling Sleep mode. 8.4 Digital audio data input 8.4.1 Digital audio data format support The TFA9812 supports a commonly used range of I2S and I2S-like digital audio data input formats. These are listed in Table 12. Table 12. Supported digital audio data formats BCK frequency Interface format (MSB first) Supported in I2C control mode Supported in Legacy control mode 32 fs I2S up to 16-bit data yes yes 32 fs MSB-justified 16-bit data yes yes 32 fs LSB-justified 16-bit data yes yes 48 fs I2S yes yes 48 fs MSB-justified up to 24-bit data yes yes up to 24-bit data TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 14 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 12. Supported digital audio data formats BCK frequency Interface format (MSB first) Supported in I2C control mode Supported in Legacy control mode 48 fs LSB-justified 16-bit data yes no 48 fs LSB-justified 18-bit data yes no 48 fs LSB-justified 20-bit data yes no 48 fs LSB-justified 24-bit data yes yes 64 fs I2S yes yes 64 fs MSB-justified up to 24-bit data yes yes 64 fs LSB-justified 16-bit data yes no 64 fs LSB-justified 18-bit data yes no 64 fs LSB-justified 20-bit data yes no 64 fs LSB-justified 24-bit data yes no up to 24-bit data Remark: Only MSB-first formats are supported. RIGHT LEFT WS 1 2 3 1 2 3 MSB B2 BCK MSB DATA B2 MSB I2S-BUS FORMAT LEFT WS 1 2 RIGHT 3 1 2 3 BCK DATA MSB B2 LSB MSB B2 LSB MSB B2 MSB-JUSTIFIED FORMAT WS LEFT RIGHT 16 15 2 1 16 B15 LSB MSB 15 2 1 BCK DATA MSB B2 B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS WS LEFT RIGHT 18 17 16 15 2 1 18 B17 LSB MSB 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18 BITS WS LEFT 20 RIGHT 19 18 17 16 15 2 1 20 B19 LSB MSB 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS WS LEFT 24 23 22 21 20 RIGHT 19 18 17 16 15 2 1 24 B23 LSB MSB 23 22 21 20 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB 010aaa458 LSB-JUSTIFIED FORMAT 24 BITS Fig 4. Serial interface input and output formats TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 15 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input In I2C control mode the following sample frequency fs can be used: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz, 176.4 kHz or 192 kHz. The I2C control for fs selection can be found in Section 9.5.7. In Legacy control mode the following sample frequencies (fs) can be used: 32 kHz, 44.1 kHz or 48 kHz. 8.4.2 Digital audio data format control The BCK-to-WS and MCLK-to-WS frequency ratios are automatically detected, so no control settings need to be configured for these. In I2C control mode all the formats listed in Table 12 are supported. The appropriate I2C controls for selecting the supported formats can be found in Section 9. In the Legacy control mode only a subset of the supported formats can be used. These are shown in Table 12 and the required pin control is given in Table 13. See Section 8.2.1 for details of how to enable Legacy control mode. Table 13. Digital audio data format selection in Legacy control mode SCL/SFOR pin value Interface formats (MSB-first) 0 I2S 1 MSB-justified 8.5 Digital signal-processing features 8.5.1 Equalizer 8.5.1.1 Equalizer options The equalizer function can be bypassed and the equalizer can be configured to either a 5-band or 10-band function. These settings are for both audio channels simultaneously. There are 20 bands in the equalizer. These are distributed as follows: • Bands A1 to A5 are bands 1 to 5 of output 1 (used in 5-band and 10-band configuration). • Bands B1 to B5 are bands 1 to 5 of output 2 (used in 5-band and 10-band configuration). • Bands C1 to C5 are bands 6 to 10 of output 1 (used in 10-band configuration only). • Bands D1 to D5 are bands 6 to 10 of output 2 (used in 10-band configuration only). In I2C control mode each band can be configured separately using I2C register settings. In Legacy control mode the equalizer is bypassed. 8.5.1.2 Equalizer band function The shape of each parametric equalizer band is determined by the three filter parameters: • (Relative) center frequency ω = 2π ( f c ⁄ f s ). • Quality factor Q. • Gain factor G. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 16 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input In the above equation fc is the center frequency and fs is the sample frequency. The definition of the quality factor is the center frequency divided by the 3 dB bandwidth, see Equation 1. In parametric equalizers this is only valid when the gain is set very small (−30 dB). f 1: Af 10 20 log --------1 A f c = 3dB f c > f 1 f 2: Af 10 20 log --------2 A f c = 3dB , f 2 > f c fc Q = -----------------; f2 – f1 (1) Each band filter can be programmed to perform a band-suppression (G < 1) or a band-amplification (G > 1) function around the center frequency. Each band of the TFA9812 equalizer has a second-order Regalia-Mitra all-pass filter structure. The structure is shown in Figure 5. + ½ + Y(z) + X(z) s − K0/2 A(z) 010aaa406 Fig 5. Regalia filter flow-diagram The transfer function of this all-pass filter is shown in Equation 2: H (z) = 1 ⁄ 2 ⋅ (1 + A(z)) + K 0 ⁄ 2 ⋅ (1 – A(z)) (2) A(z) is the second-order filter structure. The transfer function of A(z) is shown in Equation 3: –1 –2 K 1 + K 2 ⋅ (1 + K 1) ⋅ Z + Z A ( z ) = -------------------------------------------------------------------------------–1 –2 1 + K 2 ⋅ (1 + K 1) ⋅ Z + K 1 ⋅ Z (3) The relationship between the programmable parameters K0, K1, and K2 and the filter parameters G, ω, Q is shown in Equation 4 and Equation 5. Use Equation 4 to calculate band suppression (G < 1) functions. K0 = G K 1 = – cos ω K 2 = ( 2Q ⋅ G – sin ω ) ⁄ ( 2Q ⋅ G + sin ω ) (4) G<1 Use Equation 5 to calculate band amplification (G ≥ 1) functions. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 17 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input K0 = G K 1 = – cos ω (5) K 2 = ( 2Q – sin ω ) ⁄ ( 2Q + sin ω ) G≥1 The ranges of the TFA9812 parametric equalizer settings for each band are: • The Gain, G is from −30 dB to +12 dB. • The center frequency, fc is from 0.0004 * fs to 0.49 * fs. • The quality factor Q is from 0.001 to 8. Using I2C control, filter coefficients need to be entered for each filter stage to configure it as desired. Figure 6, Figure 7 and Figure 8 show some of the possible transfer functions of the equalizer bands. The relations are symmetrical for the suppression and amplification functions. A skewing effect can be observed for the higher frequencies. Different configurations are available for the same filter transfer function, thus allowing optimum numerical noise performance. The binary filter configuration parameters t1 and t2 control the actual configuration and should be chosen according to Equation 6. 0 t 1 = 1 0 t 2 = 1 ω<=π ⁄ 2 ω>π ⁄ 2 k 2 >=0 k 2 <0 (6) A maximum of 12 dB amplification per equalizer stage can be achieved with respect to the input signal. Each band of the equalizer is provided with a −6 dB amplification, so in order to prevent numerical clipping for some filter settings with over 6 dB of amplification, band filters can be scaled by 0 dB or −6 dB. For optimum numerical noise performance steps of −6 dB amplification should be applied to the highest possible sections that are still within scale signal processing safeguards. Band filters can be scaled with the binary parameters listed in Table 14. Table 14. 8.5.1.3 Equalizer scale factor coding s scale factor (dB) 0 0 1 −6 Equalizer band control For compact representation with positive signed parameters, parameters k1’ and k2’ are introduced in Equation 7. The parameters k0, k1', k2', t1, t2 and s must be combined in two 16-bit control words, word1 and word2, and must fit within the representation given in Table 15. Parameters k1' and k2' are unsigned floating-point representations in Equation 8. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 18 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 1 – k1 k1′ = 1 + k1 t1 = 1 1 – k2 k2′ = 1 + k2 t2 = 0 kx = M ⋅ 2 t1 = 0 (7) t2 = 1 –E (8) M<1 In Equation 8, M is the unsigned mantissa and E the negative signed exponent. For example, in word2 bits [14:8] = [0111 010] represent k2' = (7/24) × 2−2 = 1.09375 10−1. Table 15. Equalizer control word construction Word Section Data word1 15 t1 word1 [14:4] 11 mantissa bits of k1’ word1 [3:0] Four exponent bits of k1’ word2 15 t2 word2 [14:11] Four mantissa bits of k2’ word2 [10:8] Three exponents bits of k2’ word2 [7:1] k0 word2 0 s Section 9.5.4 shows the I2C address locations of the controls for various bands of the equalizer. 010aaa222 12 Q1 = 0.27 Gain (dB) Q2 = 0.61 8 Q3 = 1.65 4 0 101 Fig 6. 102 103 Transfer functions for several quality factors Q TFA9812_1 Preliminary data sheet 104 105 Frequency (Hz) © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 19 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 010aaa223 12 Gain (dB) 8 4 0 101 102 103 104 105 Frequency (Hz) Fig 7. Transfer functions for several center frequencies fc 010aaa224 12 Gain (dB) 6 0 -6 -12 101 102 103 104 105 Frequency (Hz) Fig 8. Transfer functions for several gain factors G 8.5.2 Digital volume control In I2C control mode both audio channels have separate digital volume control. In Legacy control mode the volume control of both channels is common and the volume control setting depends on the supply voltage on the pin AVOL (32). 8-bit volume control is available per channel. This is dB-linear down to −124 dB in steps of 0.5 dB. The last step of the volume control is mute. Table 16 shows the various settings and their related channel suppression: TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 20 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 16. Volume control channel suppression table [7:0] control value (hexadecimal) Gain (dB) 00 0 01 −0.5 ... steps of 0.5 dB F7 −123.5 F8 −124 F9 mute Section 9 shows the I2C address locations for the digital gain control for both channels. In Legacy mode the pin AVOL (32) can be used to control the volume. Voltage levels of 0.8 V to 2.8 V correspond linearly to control values of 00h (0 dB) to F9h (mute). See Table 16. An external pull-up resistor connected to the VDDD(3V3) can be applied to provide a default volume of 0 dB. Pin AVOL has no function in I2C mode. 8.5.3 Soft mute and mute Soft mute is available in I2C and in Legacy control modes: hard mute can be enabled only in I2C control mode. In I2C control mode the soft mute function smoothly reduces the gain setting for both channels to mute level over a duration of 128/fs seconds. The smooth shape is implemented as a raised cosine function. Soft demute results in a similar gain increase. This implementation avoids audible plops. A different soft mute and soft demute function is implemented in Legacy mode. This works via the analog gain control under the control of pin AVOL. The analog volume control input signal is first-order low-pass filtered with a time constant of 10 ms in the digital domain. Suddenly switching on or switching off volume by setting the control voltage to > 2.8 V or < 0.8 V respectively will result in a fading which lasts approximately 15 ms (switching between 0 V and 3.3 V at AVOL). In Legacy mode the soft demute function that is part of the automatic power-up sequence is similar to the I2C mode soft demute function described above. The I2C control for the soft and hard mute functions can be found In Section 9. 8.5.4 Output signal and word-select polarity control In I2C control mode the TFA9812 can switch the polarity of the stereo output signal. The effect is a 180 degree phase shift of both output signals. The TFA9812 also has the option of switching the polarity of the WS signal. Without polarity inversion the left audio signal is connected to channel 1 and the right audio signal is connected to channel 2. The I2C control for the polarity switch can be found in Section 9.5.1. 8.5.5 Gain boost and clip level control An additional gain boost of +24 dB can be selected in the TFA9812. In Legacy mode this feature can be selected with the GAIN pin, see Table 17. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 21 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 17. GAIN pin functionality GAIN pin value Function 0 0 dB gain 1 +24 dB gain The I2C controls for selecting the +24 dB gain can be found in Section 9.5.6. The GAIN pin has no function In I2C mode. The TFA9812 features also specific gain settings which are related to < 0.5 %, 10 %, 20 % or 30 % clipping at the output of the TFA9812. These clipping values are only valid under the following conditions: • The volume control is set to 0 dB. • The gain boost is set to 0 dB. • A 0 dBFs I2S input signal is obtained. The I2C controls for selecting a specific clip level can be found in Section 9.5.6. In Legacy mode the clip level is set to 10 %. 8.5.6 Output power limiter Output power can be limited to three discrete levels with respect to the maximum power. The maximum power output value is determined by the value of the high voltage supply. Clipping levels (see Section 8.5.5) still apply to the maximum levels of reduced output voltage swings. In I2C control mode the same output power limiting levels can be selected, see Section 9.5.6. In Legacy control mode two pins can be used to select the output power limit level as shown in Table 18. Table 18. Legacy mode output power limiter control Pin value Function ADSEL2/PLIM2 ADSEL1/PLIM1 0 0 Maximum power 0 1 Maximum power − 1.5 dB 1 0 Maximum power − 3.0 dB 1 1 Maximum power − 4.5 dB 8.5.7 PWM control for performance improvement The PWM switching frequency of the TFA9812 is dependent on: • The sampling frequency, fs. • The sampling frequency setting, fs(selected) (see Section 9.5.7). • The PWM switching frequency setting, fsw (selected) (see Section 9.5.6). Equation 9 shows the relationship between these settings and the PWM carrier frequency: fs f sw = ---------------------------- ⋅ f sw ( selected ) f s ( selected ) ) TFA9812_1 Preliminary data sheet (9) © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 22 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input The selected PWM switching frequency is 400 kHz by default and can be set to 350 kHz, 700 kHz and 750 kHz in I2C control mode. In Legacy mode 400 kHz is the only option and this scales linearly if 32 kHz or 48 kHz is used as fs. Remark: The selected sample frequency, fs (selected) must be equal to the sample frequency (fs) in I2C control mode. Remark: The performance of AM radio reception can sometimes be improved by selecting non-interfering frequencies for the PWM signal. 8.6 Class-D amplification The Class-D power amplification of the PWM signal is carried out in two BTL power stages. The output signal voltage level is determined by the values on the VDDP pins. The power amplifiers can be explicitly put into 3-state mode by using the pin ENABLE as shown in Table 19. The ENABLE pin is functional in Legacy mode and in I2C mode. Table 19. ENABLE pin functionality ENABLE pin value Function 0 Output stages in 3-state mode. 1 Switching enabled [1]. [1] Can be overruled by a forced 3-state in Sleep or Fault mode. 8.7 Protection mechanisms The TFA9812 has a wide range of protection mechanisms to facilitate optimal and safe application. All of these are active in both I2C and Legacy control modes. The following protections are included in the TFA9812: • • • • • • • • • • • • Thermal Foldback (TF) OverTemperature Protection (OTP) OverCurrent Protection (OCP) OverVoltage Protection (OVP) UnderVoltage Protection (UVP) Window Protection (WP) Lock Protection (LP) UnderFrequency Protection (UFP) OverFrequency Protection (OFP) Invalid BCK Protection (IBP) DC-blocking ESD The reaction of the device to the different fault conditions differs per protection. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 23 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 8.7.1 Thermal foldback If the junction temperature of the TFA9812 exceeds the programmable Thermal foldback threshold temperature the gain of the amplifier is decreased gradually to a level where the combination of dissipation (P) and the thermal resistance from junction to ambient (Rth(j-a)) results in a junction temperature around the threshold temperature. This means that the device will not completely switch off, but remains operational at lower output power levels. Especially with music output signals this feature enables high peak output power while still operating without any external heat sink other than the printed-circuit board area. If the junction temperature still increases due to external causes, the OTP switches the amplifier to 3-state mode. Under I2C control the Thermal foldback threshold temperature value can be lowered (see Section 9.5.8): In Legacy control mode the default threshold value of 125 °C is fixed. 8.7.2 Overtemperature protection This is a ‘hard’ protection to prevent heat damage to the TFA9812. The overtemperature threshold level is the 160 °C junction temperature. When the threshold temperature is exceeded the output stages are set to 3-state mode. The temperature is then checked at 1 µs intervals and the output stages will operate normally again once the temperature has dropped below the threshold level. OTP is flagged by a low DIAG pin. The TFA9812 temperature is an I2C reading, see Section 9.5.9. Under normal conditions thermal foldback prevents the overtemperature protection from being triggered. 8.7.3 Overcurrent protection The output current of the power amplifiers is current-limited. When an output stage exceeds a current of 3 A typical, the output stages are set to 3-state mode and after 1 µs the stages will start operating normally again. These interruptions are not audible. OCP is flagged by a low DIAG pin and by a high DIAG I2C status bit, see Section 9.5.10. I2C settings remain valid. 8.7.4 Overvoltage protection The supply for the power stages (VDDA, VDDP) is protected against overvoltage. When a supply voltage exceeds 20 V the device will enter Sleep mode. When the supply voltage has fallen below 20 V again the power-up sequence is started. OVP is flagged by a low DIAG pin and by a high DIAG I2C status bit, see Section 9.5.10. I2C settings remain valid. 8.7.5 Undervoltage protections The supplies are protected against undervoltage. When this is detected the device will enter Sleep mode. When the supply voltage has risen to a sufficient level again the power-up sequence is started. Table 20 shows the UVP trigger levels for the VDDA and VDDA(3V3) supplies: TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 24 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 20. Undervoltage trigger levels Pin name UVP level DIAG pin (protection active) Min Max VDDA ≥7V <8V LOW VDDA(3V3) ≥ 1.6 V <3V - 8.7.6 Overdissipation protection When the output current of the power amplifiers exceeds a current value of 3 A and the temperature is above 140 °C, overdissipation protection is activated and the device enters Sleep mode. A restart will be initiated automatically when the two overdissipation conditions are both changed to ‘false’. Overdissipation is flagged by a low DIAG pin and by a high DIAG I2C status bit, see Section 9.5.10. Under normal conditions thermal foldback prevents overdissipation protection from being triggered. I2C settings remain valid. 8.7.7 Window protection Window protection is a feature for protecting the device against shorts from the outputs to the ground or supply lines. If during power-up one of the outputs is shorted to VSSPx or VDDP, power-up does not proceed any further. The trigger levels for these conditions are: • OUTxx > VDDA − 1 V, or • OUTxx < REFA + 1 V. The WP alarm is flagged by a low DIAG pin and by a high DIAG I2C status bit, see Section 9.5.10. 8.7.8 Lock protection When the selected clock input source (MCLK, BCK or crystal) stops running, the TFA9812 is able to detect this and set the output stages to 3-state mode. Without this protection peripheral devices in an application might be damaged. The PLL lock indication is an I2C reading and will be ‘false’ in the event of a clock interruption, see Section 9.5.10. 8.7.9 Underfrequency protection UFP sets the output stages to 3-state mode when the clock input source is too low. The PWM switching frequency can becomes critically low when the clock input source is lower than specified. Without UFP peripheral devices in an application might be damaged. The status of the UFP is shown in I2C reading register, see Section 9.5.10. 8.7.10 Overfrequency protection OFP sets the output stages to 3-state mode when the clock input source is too high. The PWM controller can become unstable when the clock input source is higher than specified. Without OFP peripheral devices in an application might be damaged. The status of the OFP is shown in I2C reading register, see Section 9.5.10. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 25 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 8.7.11 Invalid BCK protection The BCK clock signal is verified as being at one of the allowed relative frequencies: 32 fs, 48 fs or 64 fs. If it is not at one of these frequencies the TFA9812 will set the output stages to 3-state mode to prevent audible effects. The MCLK clock signal is also verified as being valid, see Section 8.2.3. Detection of violation results in an automatic internal overruling of the MCLK assignment to BCK. 8.7.12 DC blocking The TFA9812 features a high pass filter after the I2S input to block DC signals. DC values at the output can damage the peripheral devices. The high pass filter is always enabled. 8.7.13 Overview protections Table 21 shows the overview of the protections. Table 21. Overview protections Protections Symbol Conditions DIAG pin I2C Output flag[1] TF programmable max. Tj > 125 °C Floating - Switching Automatic, increasing volume control back to volume setting OTP Tj > 160 °C LOW DIAG Floating Automatic, after 1 µs and Tj < 160 °C OCP IO > IORM LOW DIAG Floating Automatic, after 1 µs and IO < IORM OVP VDDA > 20 V LOW DIAG Floating Restart (fault to operating when VDDA > 8 V and VDDA(3V3) > 3 V) UVP VDDA < 8 V or VDDA(3V3) < 3 V LOW DIAG Floating Restart (fault to operating when VDDA > 8 V and VDDA(3V3) > 3 V) ODP Tj > 140 °C and IO > IORM LOW DIAG Floating Restart (fault to operating when Tj < 140 °C or IO < IORM) WP[2] OUTX > VDDA − 1 V or OUTX < REFA + 1 V LOW DIAG Floating Restart (fault to operating when OUTX < VDDA − 1 V and OUTX > VSSA + 1 V) LP PLL out of lock Floating LP Floating Restart (fault to operating when PLL is in lock) UFP PLL frequency < 45 MHz Floating UFP Floating Restart (fault to operating when PLL frequency > 45 MHz) TFA9812_1 Preliminary data sheet Recovering © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 26 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 21. Overview protections …continued Protections Symbol Conditions DIAG pin I2C Output flag[1] Recovering OFP PLL frequency > 140 MHz Floating OFP Floating Restart (fault to operating when PLL frequency < 140 MHz) IBP BCK/WS is not 32 ± 2, 48 2 or 64 2 - Floating Restart (fault to operating when BCK/WS is 32 ± 2, 48 2 or 64 2) Floating [1] See, Section 9.5.10. [2] Window Protection is only checked at power-up. 9. I2C bus interface and register settings 9.1 I2C bus interface The TFA9812 supports the 400 kHz I2C bus microcontroller interface mode standard. This can be used to control the TFA9812 and to exchange data with it when in I2C control mode, see Section 8.2.1. The TFA9812 can operate in I2C slave mode only as slave receiver or a slave transmitter. The serial hardware interface involves the pins of the TFA9812 as described in Table 22. Table 22. I2C pins in I2C control mode Pin name Description SCL/MUTE I2C bus clock input SDA/MS I2C bus data input and output ADSEL2/PLIM2 I2C bus device address bit A2 ADSEL1/PLIM1 I2C bus device address bit A1 Voltage values applied to the I2C bus device address pins are interpreted as described in Table 23. Table 23. I2C pin voltages in I2C control mode Logic value Voltage A2/A1 0 < VIL 1 > VIH 9.2 I2C bus TFA9812 device addresses Table 24 shows the register address options for the TFA9812 as part of the 8-bit byte that contains the device address as well as the bit indicator read/write_not R/!W. The TFA9812 supports four different addresses, each of which can be configured using the pins ADSEL1/PLIM1 and ADSEL2/PLIM2, see Table 22. Table 24. I2C bus device address (MSB) Bit 1 1 (LSB) 0 1 TFA9812_1 Preliminary data sheet 0 A2 A1 R/!W © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 27 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 9.3 I2C write cycle description Table 25 shows the cycle required for writing data to the I2C registers of the TFA9812. The byte size is 8 bits. The I2C registers of the TFA9812 store two data bytes. Data is always written in pairs of two bytes. Data transfer is always MSB first. The cycle format for writing to the TFA9812 using SDA is as follows: 1. The microcontroller asserts a start condition (S). 2. The microcontroller sends the device address (7 bits) of the TFA9812 followed by the R/!W bit set to 0. 3. The TFA9812 asserts an acknowledge (A). 4. The microcontroller writes the 8-bit TFA9812 register address to which the first data byte will be written. 5. The TFA9812 asserts an acknowledge. 6. The microcontroller sends the first byte. This is the most significant byte of the register. 7. The TFA9812 asserts an acknowledge. 8. The microcontroller sends the second byte. 9. The TFA9812 asserts an acknowledgement. 10. The microcontroller can either assert the stop condition (P) or continue with a further pair of data bytes, repeating step 6. In the latter case the targeted register address will have been auto-increased by the TFA9812. Table 25. I2C write cycle Start TFA9812 Address R/!W S 11010A2A1 0 TFA9812 first register address A ADDR MS databyte A MS1 A LS databyte More Stop data... LS1 <....> P 9.4 I2C read cycle description Table 26 shows the cycle required for reading data from the I2C registers of the TFA9812. The byte size is 8 bits. The I2C registers of the TFA9812 store two data bytes. Data is always read in pairs of two bytes. Data transfer is always MSB-first. The read cycle format for writing to the TFA9812 using SDA is as follows: 1. The microcontroller asserts a start condition (S). 2. The microcontroller sends the device address (7 bits) of the TFA9812 followed by the R/!W bit set to 0. 3. The TFA9812 asserts an acknowledge (A). 4. The microcontroller writes the 8-bit TFA9812 register address from which the first data byte will be read. 5. The TFA9812 asserts an acknowledge. 6. The microcontroller asserts a repeated start (Sr). 7. The microcontroller resends the device address (7 bits) of the TFA9812 followed by the R/!W bit set to 1. 8. The TFA9812 asserts an acknowledge. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 28 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 9. The TFA9812 sends the first byte. This is the most significant byte of the register. 10. The microcontroller asserts an acknowledge. 11. The TFA9812 sends the second byte. 12. The microcontroller asserts either an acknowledge or a negative acknowledge (NA). – If the microcontroller has asserted an acknowledge, the targeted register address is auto-increased by the TFA9812 and steps 9 to 12 are repeated. – If the microcontroller has asserted a negative acknowledge, the TFA9812 frees the I2C bus and the microcontroller generates a stop condition (P). Table 26. I2C read cycle Start TFA9812 address S R/!W 11010A2A1 0 First register address A ADDR TFA9812 address A Sr R/!W 11010A2A1 1 MS data byte A MS1 LS More More data data... data... byte A LS1 <A> <....> Stop NA P 9.5 Top-level register map Table 27 describes the assignments of the various register addresses to the functional control or status areas at top level. There are 47 control registers and 2 status registers. The following subsections give the individual register interpretations and bit level details. Table 27. Top-level register map Register Default (hex) address (hex) Access See: Description 0x00 R/W Section 9.5.1 Interpolator settings and soft mute 0x0020; Legacy_mode 0x0021; I2C_mode 0x01 0x0000 R/W Section 9.5.2 Volume control 0x02 0x0006 R/W Section 9.5.3 Format digital in 0x03 0x0002 R/W Section 9.5.4 Equalizer configuration 0x04 0x0058 R/W Section 9.5.5 Equalizer_A1 word_1; word_1 for equalizer band A1, see Section 8.5.1.2 0x05 0x4F40 R/W Section 9.5.5 Equalizer_A1 word_2; see Section 8.5.1.2 0x06 0x0058 R/W Section 9.5.5 Equalizer_B1 word_1 0x07 0x4F40 R/W Section 9.5.5 Equalizer_B1 word_2 0x08 0x0A63 R/W Section 9.5.5 Equalizer_C1 word_1 0x09 0x4240 R/W Section 9.5.5 Equalizer_C1 word_2 0x0A 0x0A63 R/W Section 9.5.5 Equalizer_D1 word_1 0x0B 0x4240 R/W Section 9.5.5 Equalizer_D1 word_2 0x0C 0x00B7 R/W Section 9.5.5 Equalizer_A2 word_1 0x0D 0x4E40 R/W Section 9.5.5 Equalizer_A2 word_2 0x0E 0x00B7 R/W Section 9.5.5 Equalizer_B2 word_1 0x0F 0x4E40 R/W Section 9.5.5 Equalizer_B2 word_2 0x10 0x14A2 R/W Section 9.5.5 Equalizer_C2 word_1 TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 29 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 27. Top-level register map …continued Register Default (hex) address (hex) Access See: Description 0x11 0x7A40 R/W Section 9.5.5 Equalizer_C2 word_2 0x12 0x14A2 R/W Section 9.5.5 Equalizer_D2 word_1 0x13 0x7A40 R/W Section 9.5.5 Equalizer_D2 word_2 0x14 0x0156 R/W Section 9.5.5 Equalizer_A3 word_1 0x15 0x4D40 R/W Section 9.5.5 Equalizer_A3 word_2 0x16 0x0156 R/W Section 9.5.5 Equalizer_B3 word_1 0x17 0x4D40 R/W Section 9.5.5 Equalizer_B3 word_2 0x18 0x2871 R/W Section 9.5.5 Equalizer_C3 word_1 0x19 0x7140 R/W Section 9.5.5 Equalizer_C3 word_2 0x1A 0x2871 R/W Section 9.5.5 Equalizer_D3 word_1 0x1B 0x7140 R/W Section 9.5.5 Equalizer_D3 word_2 0x1C 0x02A5 R/W Section 9.5.5 Equalizer_A4 word_1 0x1D 0x4C40 R/W Section 9.5.5 Equalizer_A4 word_2 0x1E 0x02A5 R/W Section 9.5.5 Equalizer_B4 word_1 0x1F 0x4C40 R/W Section 9.5.5 Equalizer_B4 word_2 0x20 0x4A80 R/W Section 9.5.5 Equalizer_C4 word_1 0x21 0x5040 R/W Section 9.5.5 Equalizer_C4 word_2 0x22 0x4A80 R/W Section 9.5.5 Equalizer_D4 word_1 0x23 0x5040 R/W Section 9.5.5 Equalizer_D4 word_2 0x24 0x0534 R/W Section 9.5.5 Equalizer_A5 word_1 0x25 0x4B40 R/W Section 9.5.5 Equalizer_A5 word_2 0x26 0x0534 R/W Section 9.5.5 Equalizer_B5 word_1 0x27 0x4B40 R/W Section 9.5.5 Equalizer_B5 word_2 0x28 0xD961 R/W Section 9.5.5 Equalizer_C5 word_1 0x29 0x4840 R/W Section 9.5.5 Equalizer_C5 word_2 0x2A 0xD961 R/W Section 9.5.5 Equalizer_D5 word_1 0x2B 0x4840 R/W Section 9.5.5 Equalizer_D5 word_2 0x2C 0x0005 R/W Section 9.5.6 PWM signal control 0x2D 0x000E R/W Section 9.5.7 Digital-in clock configuration 0x2E 0x0000 R/W Section 9.5.8 Thermal foldback control 0x2F - R Section 9.5.9 TFA9812 temperature 0x30 - R Section 9.5.10 Miscellaneous status Reserved registers or bits will be indicated by RSD. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 30 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 9.5.1 Interpolator settings and soft mute Table 28. Bit Register address 00h: miscellaneous I2C interpolator settings 15 14 13 12 11 10 9 8 RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD INV_POL ROFF1 ROFF0 FDEMP2 FDEMP1 FDEMP0 S_MUTE Default 0 0 1 0 0 0 0 1/0 Symbol Table 29. Bit description of register 00h: miscellaneous I2C interpolator settings Bit Symbol Description 6 INV_POL Enable polarity inversion: 0 = No polarity inversion (left audio signal connected to channel 1; right signal to channel 2) 1 = Polarity inversion enabled 5 to 4 ROFF[1:0] Filter roll-off sharpness: 0 = Slow filter roll-off (2 to 8 fs) ≥ stop band > 0.7619 fs 1 = Slow filter roll-off (2 to 8 fs) ≥ stop band > 0.7619 fs 2 = Fast filter roll-off (2 to 8 fs) ≥ stop band > 0.6094 fs 3 = Fast filter roll-off (2 to 8 fs) ≥ stop band > 0.6094 fs 3 to 1 FDEMP[2:0] Digital de-emphasis setting: 0 = No digital de-emphasis 1 = Digital de-emphasis for fs = 32 kHz 2 = Digital de-emphasis for fs = 44.1 kHz 3 = Digital de-emphasis for fs = 48 kHz 4 = Digital de-emphasis for fs = 96 kHz 5 to 8 = No digital de-emphasis 0 S_MUTE Soft mute: 0 = Soft mute disabled using raised cosine (default in Legacy control mode) 1 = Soft mute enabled using raised cosine (default in I2C control mode) 9.5.2 Volume control Table 30. Bit Register address 01h: volume control 15 14 13 12 11 10 9 8 Symbol VOL_L7 VOL_L6 VOL_L5 VOL_L4 VOL_L3 VOL_L2 VOL_L1 VOL_L0 Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol VOL_R7 VOL_R6 VOL_R5 VOL_R4 VOL_R3 VOL_R2 VOL_R1 VOL_R0 Default 0 0 0 0 0 0 0 0 TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 31 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 31. Bit description of register 00h: miscellaneous I2C interpolator settings Bit Symbol Description 15 to 8 VOL_L[15:8] See Table 16 for suppression levels on left channel as function of data byte setting. 7 to 0 VOL_R[7:0] See Table 16 for suppression levels on right channel as function of data byte setting. 9.5.3 Digital input format Table 32. Bit Register address 02h: digital input format 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD RSD RSD RSD DI_FOR2 DI_FOR1 DI_FOR0 WS_POL Default 0 0 0 0 0 1 1 0 Table 33. Bit description of register 02h: digital input format Bit Symbol Description 3 to 1 DI_FOR[2:0] Digital audio input format: 0 = RSD 1 = RSD 2 = MSB-justified data up to 24 bits 3 = I2S data up to 24 bits 4 = LSB-justified 16-bit data 5 = LSB-justified 18-bit data 6 = LSB-justified 20-bit data 7 = LSB-justified 24-bit data 0 WS_POL Enable WS signal polarity inversion: 0 = No WS signal polarity inversion 1 = WS signal polarity inversion enabled 9.5.4 Equalizer configuration Table 34. Bit Register address 03h: equalizer configuration 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD RSD RSD RSD RSD RSD EQ_BP EQ_BND Default 0 0 0 0 0 0 1 0 TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 32 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 35. Bit description of register 03h: equalizer configuration Bit Symbol Description 1 EQ_BP Equalizer bypass enable: 0 = Equalizer not bypassed 1 = Equalizer bypassed 0 EQ_BND Equalizer 10-band or 5-band configuration selection: 0 = 10-band equalizer configuration enabled 1 = 5-band equalizer configuration enabled 9.5.5 Equalizer settings Table 36. Register addresses xxh = 04, 06...2A For word1 for equalizer 'yy' see Figure 9 Bit 15 14 13 12 11 10 9 8 Eyy_t1 Eyy_k1m10 Eyy_k1m9 Eyy_k1m8 Eyy_k1m7 Eyy_k1m6 Eyy_k1m5 Eyy_k1m4 Default[1] - - - - - - - - Bit 7 6 5 4 3 2 1 0 Symbol Eyy_k1m3 Eyy_k1m2 Eyy_k1m1 Eyy_k1m0 Eyy_k1e3 Eyy_k1e2 Eyy_k1e1 Eyy_k1e0 Default[1] - - - - - - - - Symbol [1] Default settings are shown in Table 27. The corresponding equalizer configuration is shown in Table 40. Table 37. Register addresses xxh = 05, 07...2B For word2 for equalizer 'yy' see Figure 9 Bit Symbol 15 14 13 12 11 10 9 8 Eyy_t2 Eyy_k2m3 Eyy_k2m2 Eyy_k2m1 Eyy_k2m0 Eyy_k2e2 Eyy_k2e1 Eyy_k2e0 Default - - - - - - - - Bit 7 6 5 4 3 2 1 0 Symbol Eyy_k06 Eyy_k05 Eyy_k04 Eyy_k03 Eyy_k02 Eyy_k01 Eyy_k00 Eyy_s Default - - - - - - - - [1] Default settings are shown in Table 27. The corresponding equalizer configuration is shown in Table 40. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 33 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input A1 Left in A2 A3 A4 A5 Left out C1 C2 C3 C4 C5 2 × 5 or 2 × 10 B1 Right in B2 B3 B4 B5 Right out D1 D2 D3 D4 D5 2 × 5 or 2 × 10 010aaa404 Fig 9. Equalizer configuration and register location mapping Table 38. Bit description of registers xxh = 04, 06...2A Bit Symbol Description 15 Eyy_t1 The filter configuration bit t1, see Section 8.5.1.2. 14 to 4 Eyy_k1m[10:0] The 11 mantissa bits of the filter parameter k1, see Section 8.5.1.2. 3 to 0 Eyy_k1e[3:0] The four exponent bits of the filter parameter k1, see Section 8.5.1.2. Table 39. Bit Bit description of registers xxh = 05, 07...2B Symbol Description 15 Eyy_t2 The filter configuration bit t2, see Section 8.5.1.2. 14 to 11 Eyy_k2m[3:0] The four mantissa bits of the filter parameter k2, see Section 8.5.1.2. 10 to 8 Eyy_k2e[2:0] The three exponent bits of the filter parameter k2, see Section 8.5.1.2. 7 to 1 Eyy_k0[6:0] The seven bits of the filter gain parameter k0, see Section 8.5.1.2. 0 Eyy_s The filter scale-factor bits, see Section 8.5.1.2: 0 = No scaling applied 1 = −6 dB amplification enabled TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 34 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 40. Default configuration equalizer for fs = 44.1 kHz Band A1/B1 A2/B2 A3/B3 A4/B4 A5/B5 C1/D1 C2/D2 C3/D3 C4/D4 C5/D5 Frequency (Hz) 31 63 125 250 500 1000 2000 4000 8000 16000 Q-factor 1 1 1 1 1 1 1 1 1 1 Gain (dB) 0 0 0 0 0 0 0 0 0 0 9.5.6 PWM signal control Table 41. Bit Register 2Ch: PWM signal control 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD PLIM1 PLIM0 PW_OFF PW_SF1 PW_SF0 PW_CL1 PW_CL0 Default 0 0 0 0 0 1 0 1 Table 42. Bit description address 2Ch Bit Symbol Description 7 GAIN +24 dB gain boost: 0 = Gain boost 0 dB 1 = Gain boost +24 dB 6 to 5 PLIM[1:0] Output power limitation: 0 = Maximum power 1 = Maximum power − 1.5 dB 2 = Maximum power − 3.0 dB 3 = Maximum power − 4.5 dB 4 PW_OFF Hard mute control: 0 = No hard mute 1 = Hard mute enabled, implemented by PWM signal with 50 % duty cycle 3 to 2 PW_SF[1:0] PWM switching frequency: 0 = 350 kHz 1 = 400 kHz 2 = 700 kHz 3 = 750 kHz 1 to 0 PW_CL[1:0] PWM clip level: 0 = < 0.5 % THD 1 = 10 % THD 2 = 20 % THD 3 = 30 % THD TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 35 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 9.5.7 Digital-in clock configuration Table 43. Bit Register 2Dh: digital-in clock configuration 15 14 13 12 11 10 9 8 RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD RSD RSD FSUB3 FSUB2 FSUB1 FSUB0 DI_MS Default 0 0 0 0 1 1 1 0 Symbol Table 44. Bit description of register 2Dh:digital-in clock configuration Bit Symbol Description 4 to 1 FSUB[3:0] Sample frequency fs of digital-in signal: 0 = 8 kHz 1 = 11.025 kHz 2 = 12 kHz 3 = 16 kHz 4 = 22.05 kHz 5 = 24 kHz 6 = 32 kHz 7 = 44.1 kHz 8 = 48 kHz 9 = 64 kHz 10 = 88.2 kHz 11 = 96 kHz 12 = 128 kHz 13 = 176.4 kHz 14 = 192 kHz 15 = RSD 0 DI_MS TFA9812 digital-in Master/Slave mode selection: 0 = Slave mode 1 = Master mode 9.5.8 Thermal foldback control Table 45. Bit Register 2Eh: thermal foldback control 15 14 13 12 11 10 9 8 RSD RSD RSD RSD RSD RSD TP_THR9 TP_THR8 Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol TP_THR7 TP_THR6 TP_THR5 TP_THR4 TP_THR3 TP_THR2 TP_THR1 TP_THR0 Default 0 0 0 0 0 0 0 0 Symbol TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 36 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 46. Bit description of register 2Dh: digital-in clock configuration Bit Symbol Description 9 to 0 TP_THR[9:0] Reduction on the maximum temperature of 125 °C. The reduction can be calculated by: (TP_THR[9:0] reduction = INTEGER -----------------------------------in °C 2.4552 9.5.9 TFA9812 temperature Table 47. Bit Register 2Fh: TFA9812 temperature 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD TEMP9 TEMP8 Default - - - - - - - - Bit 7 6 5 4 3 2 1 0 Symbol TEMP7 TEMP6 TEMP5 TEMP4 TEMP3 TEMP2 TEMP1 TEMP0 Default - - - - - - - - Table 48. Bit description of register 2Dh: digital-in clock configuration Bit Symbol Description 9 to 0 TEMP[9:0] Temperature of the TFA9812, which can be calculated in °C using: Temp TFA9812 = (1023 − TEMP[9:0]) / 2.4552 9.5.10 Miscellaneous status Table 49. Bit Register 30h: miscellaneous status 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default - - - - - - - - Bit 7 6 5 4 3 2 1 0 Symbol RSD OFP UFP UVP1V8 UVP3V3 DIAG LP MUTE Default - - - - - - - - Table 50. Bit description of register 30h: miscellaneous status Bit Symbol Description 6 OFP PLL frequency-over-range indicator: 0 = PLL frequency in supported range 1 = PLL frequency exceeds highest supported frequency value 5 UFP PLL frequency underrange indicator: 0 = PLL frequency in supported range 1 = PLL frequency below lowest supported frequency value 4 UVP1V8 Undervoltage detector for pins 4 and 41: 0 = No UVP has been detected 1 = A UVP has been detected since the last read-out of the register TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 37 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 50. Bit description of register 30h: miscellaneous status …continued Bit Symbol Description 3 UVP3V3 Undervoltage detector for pins 3 and 40: 0 = No UVP has been detected 1 = A UVP has been detected since the last read-out of the register 2 DIAG Diagnostic pin flagging status[1]: 0 = Diagnostic pin has not been flagged low 1 = Diagnostic pin has been flagged low since the last read-out of the register 1 LP PLL lock protection indicator: 0 = PLL is in locked status 1 = PLL is not in locked status 0 MUTE Soft mute status: 0 = No soft-mute or soft mute/demute in progress 1 = Audio signal muted as result of a soft mute [1] The diagnostic pin 30 DIAG is flagged when several protection mechanisms have been active, see Section 8.7. 9.6 Overview of functional control in each control mode Table 51 shows the control level supported by either I2C or Legacy control mode for all functions described in Section 9. It summarizes the information provided in the detailed description of each function. Table 51. Functional control support in I2C and Legacy control modes D = fixed control setting, determined by default I2C register setting; N = not supported; Y = fully supported (i.e. all options implemented in the TFA9812). Control function Reference I2C mode Legacy mode I2C Section 9 Y N/D Sleep mode enable register content Section 8.2.2 Y Y Operating mode enable Section 8.2.2 Y Y 3-state mode enable Section 8.2.2 Y Y I2 S Section 8.2.3 Y Y MCLK/BCK master input clock selection Section 8.2.3 Auto Auto Digital audio input format selection Section 8.4 Y Subset Selection fs = 8 kHz to 192 kHz Section 8.4.1 Y D[1] Equalizer enable and configuration Section 8.5.1 Y D[2] Detailed equalizer settings Section 8.5.1 Y N Digital volume control per channel Section 8.5.2 Y N Analog volume control (shared for two channels) Section 8.5.3 N Y De-emphasis for subset of allowed fs Section 8.5.3 Y N Soft mute Section 8.5.3 Y Y[3] Hard mute Section 8.5.3 Y N Polarity switch enable Section 8.5.4 Y N +24 dB gain boost Section 8.5.6 Y Y Master/Slave TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 38 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 51. Functional control support in I2C and Legacy control modes …continued D = fixed control setting, determined by default I2C register setting; N = not supported; Y = fully supported (i.e. all options implemented in the TFA9812). Control function Reference I2C mode Legacy mode Clip level control Section 8.5.5 Y D[4] Output power limit level control Section 8.5.6 Y Y PWM signal frequency selection Section 8.5.7 Y D[5] Thermal foldback threshold temperature control Section 8.7.1 Y N [1] 32 kHz, 44.1 kHz and 48 kHz supported [2] Bypass. [3] Special Legacy mode implementation. [4] 10 % clip level. [5] 400 kHz. 10. Internal circuitry Table 52. Internal circuitry Pin Symbol 1 XTALIN 32 AVOL Equivalent circuitry 1, 32 ESD VSS1, VSS2, REFA, REFD Exposed die paddle 010aaa459 2 XTALOUT STABA 2 ESD VSS1, VSS2, REFA, REFD, Exposed die-paddle 010aaa460 3 VDDA(3V3) 40 VDDD(3V3) 3, 40 ESD VSS1, VSS2, REFA, REFD, Exposed die-paddle 010aaa461 TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 39 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 52. Internal circuitry …continued Pin Symbol 4 STABA 41 STABD Equivalent circuitry VDDA(3V3), VDDD(3V3) 4, 41 ESD VSS1, VSS2, REFA, REFD, Exposed die-paddle 010aaa462 5 REFA 6 VDDA 6 24 V VSS1, REFD, VSS2, Exposed die-paddle 5 010aaa463 7 TEST1 VDDA 7 13 kΩ VSS1 010aaa464 9 STAB2 28 STAB1 VDDA 9, 28 12 V VSS1 010aaa465 10/11 VSSP2 18/19 VDDP 26/27 VSSP1 18/19 24 V 10/11, 26/27 010aaa466 12 BOOT2N 15 BOOT1P 22 BOOT2P 25 BOOT1N 12, 15, 22, 25 12 V OUT2N, OUT1P, OUT2P, OUT1N 010aaa467 TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 40 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 52. Internal circuitry …continued Pin Symbol 13/14 OUT2N 16/17 OUT1P 20/21 OUT2P 23/24 OUT1N Equivalent circuitry VDDP 13/14, 16/17, 20/21, 23/24 VSSP1, VSSP2 010aaa468 29 DIAG VDDA 29 VSS1 VSS1 010aaa469 30 CDELAY VDDA 2 µA 30 200 nA 5 kΩ DISCHARGE VSS1 010aaa470 31 POWERUP VDDA 3 kΩ 31 250 nA VSS1 010aaa471 33 ENABLE 34 GAIN 35 CSEL 36 ADSEL2/PLIM2 37 ADSEL1/PLIM1 43 TEST2 33, 34, 35, 36, 37, 43 TFA9812_1 Preliminary data sheet Pull-down 50 µA ESD VSS1, VSS2, REFA, REFD, Exposed die-paddle 010aaa472 © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 41 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 52. Internal circuitry …continued Pin Symbol 38 SCL/SFOR Equivalent circuitry 38, 44 ESD VSS1, VSS2, REFA, REFD, Exposed die-paddle 010aaa473 39 SDA/MS 39 ESD VSS1, VSS2, REFA, REFD, Exposed die-paddle 010aaa474 45 WS 46 BCK 47 MCLK VDDD(3V3) 45, 46, 47 ESD VSS1, VSS2, REFA, REFD, Exposed die-paddle 010aaa475 11. Limiting values Table 53. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit [1] VDDA analog supply voltage −VSS −0.3 +24 V VDDP power supply voltage −VSSPx; x = 1.2 VDDA(3V3) analog supply voltage (3.3 V) −0.3 +24 V −VSS [1] −0.3 +4.6 V VDDD(3V3) digital supply voltage (3.3 V) −VSS [1] −0.3 +4.6 V Tj junction temperature - 150 °C Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C P power dissipation 5 W TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 42 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 53. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Vx Parameter Conditions voltage on pin x Vesd electrostatic discharge voltage Min Max Unit DIAG [1] VSS − 0.3 VSS + 12 V POWERUP [1] VSS − 0.3 VDDA + 0.3 V ENABLE, GAIN, CSEL, ADSEL2/PLIM2, ADSEL2/PLIM1, SCL/SFOR, SDA/MS, DATA, WS, BCK, MCLK [1] VSS − 0.5 VSS + 5.5 V AVOL [1] VSS − 0.5 VSS + 4.6 V according to the human body model STAB1 and STAB2 with respect to other pins −1750 +1750 V all other pins −2 +2 kV −500 +500 V according to the charge device model [1] Vss = VSS1 = VSS2 = REFA = REFD 12. Thermal characteristics Table 54. Thermal Characteristics Symbol Parameter Rth(j-a) Condition thermal resistance from junction to ambient Rth(j-c) thermal resistance from junction to case Rth(j-lead) thermal resistance from junction to lead Min Typ Max Unit [1][2] - - 42 K/W No air flow; typical 4L board in the NXP 4L reference application [2] - - 36 K/W No air flow; typical 2L board in the NXP 2L reference application [2] - - 42 K/W 5 - - K/W 5 - - K/W No air flow, JEDEC board [3] Worst-case pin [1] Measured in a JEDEC high K-factor test board (standard EIA/JESD 51-7). [2] Measured in free air with natural convection. [3] Strongly depends on where measurement is made on the case: worst-case value stated. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 43 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 13. Characteristics 13.1 DC Characteristics Table 55. DC characteristics Unless specified otherwise, VDDA = VDDP = 12 V, VSSP1 = VSSP2 = 0 V, VDDA(3V3) = VDDD(3V3) = 3.3 V, VSS1 = VSS2 = REFD = REFA = 0 V, Tamb = 25 °C, RL = 8 Ω, fi = 1 kHz, fs = 44.1 kHz, fsw = 400 kHz, 24-bit I2S input data, MCLK clock mode, typical application diagram (Figure 13). Symbol Parameter Condition Min Typ Max Unit Supply voltage VDDA analog supply voltage 8 12 20 V VDDP power supply voltage 8 12 20 V VDDA(3V3) analog supply voltage (3.3 V) 3.0 3.3 3.6 V VDDD(3V3) digital supply voltage (3.3 V) 3.0 3.3 3.6 V IP supply current IDDA(3V3) analog supply current (3.3 V) soft mute mode, with load, filter and snubbers connected [1] - 38 45 mA sleep mode [1] - 160 270 µA I2S slave mode - 2 4 mA I2S - 4 6 mA VDDA = VDDP = 12 V - 120 - µA VDDA = VDDP = 1 V - 40 70 µA - 15 25 mA - 25 40 mA - 4 30 µA operating mode master mode sleep mode IDDD(3V3) digital supply current operating mode (3.3 V) I2S slave mode I2S master mode sleep mode; DATA = WS = BCK = MLCK = 0 V Amplifier output pins; pins OUT1P, OUT1N, OUT2P and OUT2N |VO(offset)| output offset voltage soft mute mode - - 5 mV Power-up pin VIH HIGH-level input voltage With respect to VSS1 2.1 - VDDA V VIL LOW-level input voltage With respect to VSS1 −0.3 - +0.8 V II input current - 0.1 20 µA MCLK, BCK, WS, DATA pin VIH HIGH-level input voltage With respect to VSS2 0.7 × VDDD(3V3) - - V VIL LOW-level input voltage With respect to VSS2 - - 0.3 × VDDD(3V3) V Ci input capacitance - - 3 pF TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 44 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 55. DC characteristics …continued Unless specified otherwise, VDDA = VDDP = 12 V, VSSP1 = VSSP2 = 0 V, VDDA(3V3) = VDDD(3V3) = 3.3 V, VSS1 = VSS2 = REFD = REFA = 0 V, Tamb = 25 °C, RL = 8 Ω, fi = 1 kHz, fs = 44.1 kHz, fsw = 400 kHz, 24-bit I2S input data, MCLK clock mode, typical application diagram (Figure 13). Symbol Parameter Condition Min VOH HIGH-level output voltage At IOH = −0.4 mA VOL LOW-level output voltage At IOL = 4 mA CL load capacitance Typ Max Unit VDDD(3V3) − 0.4 V - - V - - 400 mV - - 50 pF SDA/MS, SCL/SFOR pin VIH HIGH-level input voltage With respect to VSS2 0.7 × VDDD(3V3) - 5.5 V VIL LOW-level input voltage With respect to VSS2 −0.3 - 0.3 × VDDD(3V3) V Vhys(i) input hysteresis voltage With respect to VSS2 0.1 × VDDD(3V3) - - V Ci input capacitance - - 2.5 pF VOL LOW-level output voltage - - 400 mV 0.7 × VDDD(3V3) - - V - 0.3 × VDDD(3V3) V 0.1 × VDDD(3V3) - - V - 50 93 µA STAB1 − VSS1 10 11 12 V STAB2 − VSS1 10 11 12 V STABA − REFA 1.65 1.8 1.95 V STABD − REFD 1.65 1.8 1.95 V voltage on pin CDELAY Relative to positive analog power supply - VDDA −1 - V peak-to-peak crystal oscillator output voltage With respect to VSS2 - 1.8 - V input voltage Mute level, with respect to VSS2 0.77 0.8 0.83 V 0 dB level with respect to VSS2 2.74 2.8 2.86 V - - 1 µA At IOL = 3 mA ENABLE, GAIN, CSEL, ADSEL2/PLIM2, ASEL1/PLIM1 pin VIH HIGH-level input voltage With respect to VSS2 VIL LOW-level input voltage With respect to VSS2 Vhys(i) input hysteresis voltage With respect to VSS2 II input current Regulators Vo output voltage CDELAY pin VCDELAY Crystal pins Vo(xtal)(p-p) AVOL pin Vi II input current TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 45 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 55. DC characteristics …continued Unless specified otherwise, VDDA = VDDP = 12 V, VSSP1 = VSSP2 = 0 V, VDDA(3V3) = VDDD(3V3) = 3.3 V, VSS1 = VSS2 = REFD = REFA = 0 V, Tamb = 25 °C, RL = 8 Ω, fi = 1 kHz, fs = 44.1 kHz, fsw = 400 kHz, 24-bit I2S input data, MCLK clock mode, typical application diagram (Figure 13). Symbol Parameter Condition Min Typ Max Unit 118 125 132 °C - - 160 °C 20 22.3 24 V UVP on VDDA 7 7.5 8 V UVP on VDDA(3V3) 1.6 2.2 3.0 V 3.0 3.3 3.6 A high level - VDDA − 1 - V low level - REFA + 1 - V Thermal Foldback (TF) Tact(th_fold) [2] thermal foldback activation temperature OverTemperature Protection (OTP) Tact(th_prot) thermal protection activation temperature OverVoltage Protection (OVP) VP(ovp) overvoltage protection supply voltage UnderVoltage Protections (UVP) VP(uvp) undervoltage protection supply voltage OverCurrent Protection (OCP) IO(ocp) [3] overcurrent protection output current Window Protection (WP) output voltage Vo OverFrequency Protection (OFP) fOFP Overfrequency protection frequency At PLL output frequency [4] 100 140 185 MHz At PLL output frequency [4] 30 45 60 MHz UnderFrequency Protection (OFP) Underfrequency protection frequency fUFP [1] IP is the current through the analog supply voltage (VDDA) pin added to the current through the power supply voltage (VDDP) pin. [2] Thermal foldback temperature sensor is not located at hottest spot. Hottest spot is 12 °C higher. [3] Current limiting concept: in overcurrent condition no interruption of the audio signal in case of impedance drop. [4] PLL output frequency not external available. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 46 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 13.2 AC characteristics Table 56. AC characteristics Unless specified otherwise, VDDA = VDDP = 12 V, VDDA(3V3) = VDDD(3V3) = 3.3 V, Tamb = 25 °C, Rs < 0.1 Ω[1], RL = 8 Ω, fi = 1 kHz, fs = 44.1 kHz, fsw = 400 kHz, 24-bit I2S input data, MCLK clock mode, typical application diagram (Figure 13). Symbo Parameter l Condition Min. Typ. Max. Unit Output power per channel Po(RMS) RMS output power Continuous time output power per channel; THD = 1 %, RL = 6 Ω VDDA = VDDP = 12 V - 7.9 - W VDDA = VDDP = 15 V - 12 - W Continuous time output power per channel; THD = 10 %, RL = 6 Ω VDDA = VDDP = 12 V - 9.7 - W Short time (≤ 10 s) output power per channel; THD = 10 %, RL = 6 Ω VDDA = VDDP = 15 V - 15 - W Continuous time output power per channel; THD = 1 %, RL = 8 Ω VDDA = VDDP = 12 V - 6.6 - W VDDA = VDDP = 15 V - 10 - W Continuous time output power per channel; THD = 10 %, RL = 8 Ω VDDA = VDDP = 12 V - 8.3 - W VDDA = VDDP = 13.5 V - 10 - W VDDA = VDDP = 15 V - 12 - W Short time (≤ 10 s) output power per channel; THD = 10 %, RL = 8 Ω VDDA = VDDP = 17 V - 15 - W PO = 1 W; AES17 brick wall filter - 0.07 0.1 % - 103 - dB Performance THD+N total harmonic distortion-plus-noise S/N signal-to-noise ratio VO = 10 V; A-weighted Vn(o) output noise voltage MCLK clock jitter < 200 ps; AES17 brick-wall filter operating mode - 70 - µV soft mute mode - 70 - µV hard mute mode - 30 - µV 50 54 - dB αcs channel separation Po(RMS) = 1 W; aggressor channel: fi = 1 kHz SVRR supply voltage ripple rejection Vripple = 2 Vpp; fripple = 100 Hz output power efficiency ηpo 55 60 - dB RL = 8 Ω; Po(RMS) = 8.3 W [2] - 88 - % RL = 6 Ω; Po(RMS) = 9.7 W [2] - 83 - % - - 155 ms Power-up times and delay times td(on) turn-on delay time TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 47 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 56. AC characteristics …continued Unless specified otherwise, VDDA = VDDP = 12 V, VDDA(3V3) = VDDD(3V3) = 3.3 V, Tamb = 25 °C, Rs < 0.1 Ω[1], RL = 8 Ω, fi = 1 kHz, fs = 44.1 kHz, fsw = 400 kHz, 24-bit I2S input data, MCLK clock mode, typical application diagram (Figure 13). Symbo Parameter l Condition tPD fs = propagation delay Min. Typ. Max. Unit 8 kHz - 3.6 - ms 11.025 kHz - 2.58 - ms 12 kHz - 2.39 - ms 16 kHz - 1.78 - ms 22.05 kHz - 1.3 - ms 24 kHz - 1.18 - ms 32 kHz - 892 - µs 44.1 kHz - 664 - µs 48 kHz - 600 - µs 64 kHz - 458 - µs 88.2 kHz - 320 - µs 96 kHz - 306 - µs 128 kHz - 67.2 - µs 176.4 kHz - 48 - µs 192 kHz - 40.8 - µs PWM output tr rise time IO = 0 A - 10 - ns tf fall time IO = 0 A - 10 - ns tw(min) minimum pulse width IO = 0 A - 40 - ns RDSon drain-source on-state resistance per output MOSFET, for low and high side - 0.28 0.35 Ω δmax maximum duty factor - - 0.96 - [1] Rs is the series resistance of inductor of low-pass LC filter in the application. [2] Output power measured across the loudspeaker load. This is based on indirect measurement of RDSon. 13.3 Timing Table 57. Characteristics I2C bus interface; see Figure 10 VDDD(3V3) = VDDA(3V3) = 2.7 V to 3.6 V; VDDA = VDDP = 8 V to 20 V;Tamb = −20 °C to +85 °C; all voltages referenced to ground; unless otherwise specified. Symbol Parameter fSCL Min Typ Max Unit SCL clock frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - µs tHIGH HIGH period of the SCL clock 0.6 - - µs SDA and SCL signals [1] 20 + 0.1 Cb - - ns SDA and SCL signals [1] 20 + 0.1 Cb - - ns [2] 0.6 - - µs tr tf tHD;STA rise time fall time Conditions hold time (repeated) START condition TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 48 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Table 57. Characteristics I2C bus interface; see Figure 10 …continued VDDD(3V3) = VDDA(3V3) = 2.7 V to 3.6 V; VDDA = VDDP = 8 V to 20 V;Tamb = −20 °C to +85 °C; all voltages referenced to ground; unless otherwise specified. Symbol Parameter tSU;STA Conditions Min Typ Max Unit set-up time for a repeated START condition 0.6 - - µs tSU;STO set-up time for STOP condition 0.6 - - µs tBUF bus free time between a STOP and START condition 1.3 - - µs tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - µs tSP pulse width of spikes that must be suppressed by the input filter 0 - 50 ns Cb capacitive load for each bus line - - 400 pF [3] [1] Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF. [2] After this period, the first clock pulse is generated. [3] To be suppressed by the input filter. SDA tLOW tBUF tr tf tHD;STA tSP SCL tHD;STA P tHD;DAT tHIGH tSU;DAT S tSU;STA Sr tSU;STO P 010aaa225 Fig 10. Timing 14. Application information 14.1 Output power estimation The output power just before clipping can be estimated using Equation 10: 2 RL --------------------------------------------------- ⋅δ ⋅V R L + 2 ⋅ ( R DSon + R S ) max P P O (0.5%) = ---------------------------------------------------------------------------------------------2 ⋅ RL (10) Where: VP = supply voltage (V) (VDDP-VSSP). RL = load impedance (Ω). RDSon = ‘On’ resistance power switch (Ω). TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 49 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input RS = Series resistance output inductor (Ω). δmax = Maximum duty factor (0.96). The output power at 10 % THD can be estimated using Equation 11: P O (10%) = 1.25 ⋅ P O (0.5%) (11) Figure 11 and Figure 12 show the estimated output power at THD = 0.5 % and THD = 10 % as a function of BTL supply voltage for different load impedances. 010aaa347 30 010aaa348 45 PO (10 %) W/channel PO (0.5 %) (W/channel) (1) (1) 20 30 (2) (2) 10 15 (3) (3) 0 0 8 12 16 20 8 24 12 16 20 24 VP (V) VP (V) (1) 6 Ω (1) 6 Ω (2) 8 Ω (2) 8 Ω (3) 16 Ω (3) 16 Ω Fig 11. BTL PO (0.5 %) as a function of VP Fig 12. BTL PO (10 %) as a function of VP 14.2 Output current limiting The peak output current is internally limited above a level of 3 A minimum. During normal operation the output current should not exceed this threshold level of 3 A otherwise the output signal will be distorted. The peak output current in BTL can be estimated using Equation 12: VP I O ( max ) ≤ ----------------------------------------------------R L + 2 ⋅ 〈 R DSon + R S〉 (12) Where: VP= supply voltage (V) (VDDP-VSSP) RL= load impedance (Ω) RDSon= 'On' resistance power switch (Ω) RS= series resistance output inductor (Ω) TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 50 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input Remark: A 4.8 Ω speaker (6 Ω speaker with 20 % spread) in BTL configuration can be used up to a supply voltage of 17 V without running into current limiting. Current limiting (clipping) will avoid audio holes, but it causes a distortion comparable to voltage clipping. 14.3 Speaker configuration and impedance For a flat-frequency response (second-order Butterworth filter) it is necessary to change the low pass filter components LLC and CLC according to the speaker configuration and impedance. Table 58. Filter component values Impedance (Ω) LLC (µH) CLC (nF) 6 15 680 8 18 560 16 47 330 14.4 Typical application schematics TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 51 of 66 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DIAGNOSTIC NXP Semiconductors TFA9812_1 Preliminary data sheet 14.4.1 I2S slave mode and Legacy control mode RVDDA VPA 10 Ω POWERUP DC-VOLUME CONTROL VP = 8 V to 20 V POWER IN VP ENABLE CVDDP 220 µF / 25 V GND CDELAY 1 nF 25 BOOT1N STAB1 26 VSSP1 27 VSSP1 28 DIAG 30 29 CDELAY 31 POWERUP 32 AVOL 33 ENABLE 34 24 dB GAIN ADSEL2/PLIM2 37 CSEL 35 36 CSTAB 100 nF CBOOT 15 nF 38 39 OUT1N SCL/SFOR OUT1N SDA/MS BOOT2P 40 VDDD 41 Cvddd 100 nF CSTABD 1 µF 42 43 I2S DATA I2S WS 44 45 I2S BCK 46 I2S MLCK (optional) 47 VDDD(3V3) OUT2P STABD OUT2P VDDP REFD TFA9812 TEST2 VDDP DATA OUT1P WS OUT1P BCK BOOT1P MCLK OUT2N VSS2 OUT2N 48 CSN 470 pF 22 21 20 CBOOT 15 nF CSN 470 pF F2 Lic S2 S1 F1 15 µH OUT1 CLC 680 nF − CLC 680 nF + 6 Ω to 8 Ω RSN 10 Ω VP 19 18 CVDDP 100 nF CVDDP 100 nF 17 16 15 14 CBOOT 15 nF RSN 10 Ω F2 CSN 470 pF CSN 470 pF Lic S2 S1 F1 15 µH CLC 680 nF + CLC 680 nF − OUT2 RSN 10 Ω 13 3 4 3.3 V CVDDA 100 nF 5 6 7 8 9 10 11 BOOT2N VSSP2 VSSP2 STAB2 VSS1 TEST1 VDDA REFA STABA VDDA(3V3) XTALOUT 2 12 VPA RSTABA 1 kΩ CSTAB 100 nF CVPA 100 nF CSTAB 100 nF 010aaa476 Fig 13. Simplified application diagram for I2S slave mode and Legacy control mode 6 Ω to 8 Ω TFA9812 52 of 66 © NXP B.V. 2008. All rights reserved. 1 RSN 10 Ω 23 CBOOT 15 nF DPAD XTALIN 49 24 BTL stereo Class-D audio amplifier with I2S input Rev. 01 — 30 October 2008 ADSEL1/PLIM1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DIAGNOSTIC NXP Semiconductors TFA9812_1 Preliminary data sheet 14.4.2 I2S slave mode and I2C control mode RVDDA VPA 10 Ω POWERUP POWER IN VP = 8 V to 20 V ENABLE VP CVDDP 220 µF / 25 V GND 26 VSSP1 27 25 BOOT1N 28 VSSP1 30 29 STAB1 31 AVOL ENABLE 32 CDELAY 33 POWERUP 34 GAIN ADSEL2/PLIM2 CSEL 35 36 37 CSTAB 100 nF CDELAY 1 nF DIAG 3.3 V CBOOT 15 nF OUT1N I2C SCL 38 I2C SDA 39 40 VDDD 41 CVDDD 100 nF CSTABD 1 µF 42 43 I2S DATA 44 I2S WS 45 I2S BCK 46 I2S MLCK 47 OUT1N SCL/SFOR BOOT2P SDA/MS VDDD(3V3) OUT2P STABD OUT2P VDDP REFD TFA9812 VDDP TEST2 DATA OUT1P WS OUT1P BOOT1P BCK MCLK OUT2N VSS2 OUT2N 48 CSN 470 pF 22 21 20 CBOOT 15 nF CSN 470 pF F2 Lic S2 S1 F1 15 µH OUT1 CLC 680 nF − CLC 680 nF + 6 Ω to 8 Ω RSN 10 Ω VP 19 CVDDP 18 100 nF CVDDP 100 nF 17 16 15 14 CBOOT 15 nF RSN 10 Ω F2 CSN 470 pF CSN 470 pF Lic S2 S1 F1 15 µH CLC 680 nF CLC 680 nF OUT2 + − RSN 10 Ω 13 3 4 5 3.3 V CVDDA 100 nF 6 7 8 9 10 11 BOOT2N VSSP2 VSSP2 STAB2 VSS1 TEST1 VDDA REFA STABA VDDA(3V3) XTALOUT 2 12 VPA RSTABA 1 kΩ CSTAB 100 nF CVPA 100 nF CSTAB 100 nF 010aaa477 Fig 14. Simplified application diagram for I2S slave mode and I2C control mode 6 Ω to 8 Ω TFA9812 53 of 66 © NXP B.V. 2008. All rights reserved. 1 RSN 10 Ω 23 CBOOT 15 nF DPAD XTALIN 49 24 BTL stereo Class-D audio amplifier with I2S input Rev. 01 — 30 October 2008 ADSEL1/PLIM1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2S master mode and Legacy control mode DIAGNOSTIC NXP Semiconductors TFA9812_1 Preliminary data sheet 14.4.3 RVDDA VPA 10 Ω POWERUP DC-VOLUME CONTROL VP = 8 V to 20 V POWER IN VP ENABLE CVDDP 220 µF / 25 V GND CDELAY 1 nF 25 BOOT1N 26 VSSP1 27 VSSP1 CDELAY 28 DIAG 30 29 STAB1 31 POWERUP 32 AVOL 33 ENABLE CSEL ADSEL2/PLIM2 37 34 24 dB GAIN 35 36 CSTAB 100 nF CBOOT 15 nF 38 39 3.3 V OUT1N SCL/SFOR OUT1N SDA/MS BOOT2P 40 VDDD 41 Cvddd 100 nF CSTABD 1 µF 42 43 I2S DATA I2S WS 44 45 I2S BCK 46 I2S MLCK (optional) 47 VDDD(3V3) OUT2P STABD OUT2P VDDP REFD TFA9812 TEST2 VDDP DATA OUT1P WS OUT1P BCK BOOT1P MCLK OUT2N VSS2 OUT2N 48 XTALL 3 4 CXTALL 18 pF CVDDA 100 nF 5 6 7 8 9 21 20 CSN 470 pF CBOOT 15 nF RSN 10 Ω F2 Lic S2 S1 F1 15 µH OUT1 CLC 680 nF − CLC 680 nF + 10 11 18 CVDDP 100 nF CVDDP 100 nF 17 16 15 14 CBOOT 15 nF RSN 10 Ω F2 CSN 470 pF CSN 470 pF Lic S2 S1 F1 15 µH CLC 680 nF + CLC 680 nF − OUT2 RSN 10 Ω 13 12 VPA RSTABA 1 kΩ CSTAB 100 nF CVPA 100 nF CSTAB 100 nF 010aaa478 Fig 15. Simplified application diagram for I2S master mode and Legacy control mode 6 Ω to 8 Ω VP 19 BOOT2N VSSP2 VSSP2 TEST1 VSS1 STAB2 VDDA REFA STABA VDDA(3V3) XTALOUT 2 3.3 V CXTALL 18 pF CSN 470 pF 22 6 Ω to 8 Ω TFA9812 54 of 66 © NXP B.V. 2008. All rights reserved. 1 RSN 10 Ω 23 CBOOT 15 nF DPAD XTALIN 49 24 BTL stereo Class-D audio amplifier with I2S input Rev. 01 — 30 October 2008 ADSEL1/PLIM1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DIAGNOSTIC NXP Semiconductors TFA9812_1 Preliminary data sheet 14.4.4 I2S master mode and I2C control mode RVDDA VPA 10 Ω POWERUP POWER IN VP = 8 V to 20 V ENABLE VP CVDDP 220 µF / 25 V GND CDELAY 1 nF 26 VSSP1 27 STAB1 AVOL 28 25 BOOT1N 30 29 DIAG 31 CDELAY 32 POWERUP 33 ENABLE CSEL ADSEL2/PLIM2 37 34 GAIN 35 36 CSTAB 100 nF VSSP1 3.3 V CBOOT 15 nF OUT1N I2C SCL 38 I2C SDA 39 40 VDDD 41 CVDDD 100 nF CSTABD 1 µF 42 43 I2S DATA 44 I2S WS 45 I2S BCK 46 I2S MLCK 47 OUT1N SCL/SFOR BOOT2P SDA/MS VDDD(3V3) OUT2P STABD OUT2P VDDP REFD TFA9812 VDDP TEST2 DATA OUT1P WS OUT1P BOOT1P BCK MCLK OUT2N VSS2 OUT2N 48 CSN 470 pF 22 21 20 CBOOT 15nF CSN 470 pF F2 Lic S2 S1 F1 15 µH OUT1 CLC 680 nF − CLC 680 nF + 6 Ω to 8 Ω RSN 10 Ω VP 19 CVDDP 18 100 nF CVDDP 100 nF 17 16 15 14 CBOOT 105 nF RSN 10 Ω F2 CSN 470 pF CSN 470 pF Lic S2 S1 F1 15 µH CLC 680 nF CLC 680 nF OUT2 + − RSN 10 Ω 13 4 CVDDA 100 nF 7 8 9 10 11 BOOT2N VSSP2 VSSP2 STAB2 VSS1 TEST1 5 6 3.3 V CXTALL 18 pF VDDA REFA STABA VDDA(3V3) XTALOUT 3 12 VPA RSTABA 1 kΩ CSTAB 100 nF CVPA 100 nF CSTAB 100 nF 010aaa479 Fig 16. Simplified application diagram for I2S master mode and I2C control mode 6 Ω to 8 Ω TFA9812 55 of 66 © NXP B.V. 2008. All rights reserved. 1 XTALL 2 CXTALL 18 pF RSN 10 Ω 23 CBOOT 15 nF DPAD XTALIN 49 24 BTL stereo Class-D audio amplifier with I2S input Rev. 01 — 30 October 2008 ADSEL1/PLIM1 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 14.5 Curves measured in typical application 010aaa480 10 010aaa481 10 THD+N (%) THD+N (%) 1 1 (2) (1) (1) 10−1 10−1 (3) (2) (3) 10−2 10−2 10−1 10 102 Po (W/channel) 1 10−2 10−2 10−1 (1) fi = 6 kHz (1) fi = 6 kHz (2) fi = 1 kHz (2) fi = 1 kHz (3) fi = 100 Hz (3) fi = 100 Hz a. VP = 12 V; RL = 2 × 6 Ω b. VP = 12 V; RL = 2 × 8 Ω 010aaa482 10 010aaa483 10 THD+N (%) THD+N (%) 1 1 (1) 10 102 Po (W/channel) 1 (2) (2) (1) 10−1 10−1 (3) (3) 10−2 10−2 10−1 1 10 102 Po (W/channel) 10−2 10−2 10−1 (1) fi = 6 kHz (1) fi = 6 kHz (2) fi = 1 kHz (2) fi = 1 kHz (3) fi = 100 Hz (3) fi = 100 Hz c. VP = 15 V; RL = 2 × 6 Ω 1 10 102 Po (W/channel) d. VP = 15 V; RL = 2 × 8 Ω Fig 17. Total harmonic distortion-plus-noise as a function of output power TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 56 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 010aaa484 10 THD+N (%) THD+N (%) 1 1 10−1 10−1 10−2 10 102 103 104 105 010aaa485 10 10−2 102 10 103 104 f (Hz) 105 f (Hz) a. VP = 12 V; RL = 2 × 6 Ω; Po = 1 W b. VP = 12 V; RL = 2 × 8 Ω; Po = 1 W Fig 18. Total harmonic distortion-plus-noise as a function of frequency 010aaa486 3 010aaa487 0 G (dB) −20 G (dB) −40 1 (1) −60 (2) (1) (2) −1 −80 −100 −3 10 102 103 104 105 −120 0 0.5 1 1.5 2 f (Hz) VP = 12 V; PO = 1 W (1) 0 dB (2) RL = 8 Ω 15 µH / 680 µF (2) 24 dB gain boost Fig 20. Gain as a function of AVOL TFA9812_1 Preliminary data sheet 3 VP = 12 V; RL = 8 Ω; fi = 1 kHz (1) RL = 6 Ω 15 µH / 680 µF Fig 19. Gain as a function of frequency 2.5 AVOL (V) © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 57 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 010aaa488 0 SVRR (dB) 010aaa489 100 S/N (dB) −20 (1) 90 (2) −40 (1) 80 −60 (2) 70 −80 60 −100 102 10 103 104 105 fi (Hz) VP = 12 V; Vripple = 500 mV (RMS) reference to ground; No input signal (1) RL = 8 Ω 50 10−2 10−1 10 102 Po (W/channel) 1 VP = 15 V; 20 kHz AES17 filter (1) RL = 2 × 8 Ω (2) RL = 2 × 6 Ω (2) RL = 6 Ω Fig 21. SVRR as a function of frequency Fig 22. S/N ratio as a function of output power 010aaa490 25 010aaa491 25 Po (W/chan.) Po (W/chan.) 20 20 (1) (1) 15 15 (2) (2) 10 10 (3) (3) 5 5 0 0 0 120 240 360 480 600 time (s) a. VP = 15 V; RL = 2 × 6 Ω BTL; fi = 1 kHz 0 120 240 360 480 600 time (s) b. VP = 20 V; RL = 2 × 8 Ω BTL; fi = 1 kHz (1) Tact(th_fold) = 125 °C (2) Tact(th_fold) = 105 °C (3) Tact(th_fold) = 90 °C Fig 23. Output power as a function of time TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 58 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 010aaa492 25 Po (W/chan.) 010aaa493 25 Po (W/chan.) 20 (1) 15 (2) (1) 15 (2) (3) (3) 10 20 10 (4) (4) 5 5 0 0 8 10 12 14 16 18 VP (V) 20 (1) Power limiter = 0 dB 8 10 12 14 16 18 20 VP (V) (1) Power limiter = 0 dB (2) Power limiter = −1.5 dB (2) Power limiter = −1.5 dB (3) Power limiter = −3 dB (3) Power limiter = −3 dB (4) Power limiter = −4.5 dB (4) Power limiter = −4.5 dB a. VP = 12 V; RL = 2 × 6 Ω; fi = 1 kHz; THD = 1 % 010aaa494 25 b. VP = 12 V; RL = 2 × 6 Ω; fi = 1 kHz; THD = 10 % 010aaa495 25 Po (W/chan.) Po (W/chan.) 20 20 (1) 15 (2) (1) 15 (2) (3) 10 10 (3) 5 (4) 5 (4) 0 0 8 10 12 14 16 18 20 VP (V) 8 10 12 14 (1) Power limiter = 0 dB (1) Power limiter = 0 dB (2) Power limiter = −1.5 dB (2) Power limiter = −1.5 dB (3) Power limiter = −3 dB (3) Power limiter = −3 dB (4) Power limiter = −4.5 dB (4) Power limiter = −4.5 dB c. VP = 15 V; RL = 2 × 8 Ω; fi = 1 kHz; THD = 1 % 16 18 20 VP (V) d. VP = 15 V; RL = 2 × 8 Ω; fi = 1 kHz; THD = 10 % Fig 24. Output power as a function of supply voltage TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 59 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 010aaa496 3 010aaa497 100 ηPO (%) P (W) (2) 80 (1) 2 (1) 60 (2) 40 1 20 0 10−2 10−1 1 0 10 102 Po (W/channel) 0 2 4 6 8 10 Po (W/channel) VP = 12 V; fi = 1 kHz; ηpo = (2 × Po) / (2 × Po + Pd) VP = 12 V; fi = 1 kHz; Power dissipation in junction only (1) RL = 2 × 6 Ω (1) RL = 2 × 6 Ω (2) RL = 2 × 8 Ω (2) RL = 2 × 8 Ω Fig 25. Power dissipation as a function of output power Fig 26. Efficiency as a function of output power 010aaa498 0 αcs (dB) −20 −40 (1) −60 (2) −80 −100 10 102 103 104 105 f (Hz) VP = 12 V; PO = 1 W (1) RL = 2 × 6 Ω (2) RL = 2 × 8 Ω Fig 27. Channel separation as a function of frequency TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 60 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 15. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm B D SOT619-8 A terminal 1 index area E A A1 c detail X e1 e 1/2 e v w b 13 24 L M M C C A B C y1 C y 25 12 e e2 Eh 1/2 e 1 36 terminal 1 index area 48 37 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 b c D(1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 7.1 6.9 5.75 5.45 7.1 6.9 5.75 5.45 0.5 5.5 5.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT619-8 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 07-01-10 07-01-30 Fig 28. Package outline SOT619-8 (HVQFN48) TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 61 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 16. Handling information It is advisable to abide by the normal precautions appropriate to handling MOS devices. TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 62 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 17. Revision history Table 59. Revision history Document ID Release date Data sheet status Change notice Supersedes TFA9812_1 20081030 Preliminary data sheet - - TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 63 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 64 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 20. Contents 1 2 2.1 2.2 2.3 3 4 5 6 7 7.1 8 8.1 8.2 8.2.1 8.2.2 8.2.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 DSP features . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Audio data input interface format support. . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 8 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional modes . . . . . . . . . . . . . . . . . . . . . . . 9 Control modes . . . . . . . . . . . . . . . . . . . . . . . . . 9 Key operating modes . . . . . . . . . . . . . . . . . . . . 9 I2S master/slave modes and MCLK/BCK clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.3 Power-up/power-down . . . . . . . . . . . . . . . . . . 12 8.3.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.3.2 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.4 Digital audio data input . . . . . . . . . . . . . . . . . . 14 8.4.1 Digital audio data format support . . . . . . . . . . 14 8.4.2 Digital audio data format control . . . . . . . . . . . 16 8.5 Digital signal-processing features . . . . . . . . . . 16 8.5.1 Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.5.1.1 Equalizer options . . . . . . . . . . . . . . . . . . . . . . 16 8.5.1.2 Equalizer band function . . . . . . . . . . . . . . . . . 16 8.5.1.3 Equalizer band control . . . . . . . . . . . . . . . . . . 18 8.5.2 Digital volume control . . . . . . . . . . . . . . . . . . . 20 8.5.3 Soft mute and mute . . . . . . . . . . . . . . . . . . . . 21 8.5.4 Output signal and word-select polarity control 21 8.5.5 Gain boost and clip level control . . . . . . . . . . . 21 8.5.6 Output power limiter . . . . . . . . . . . . . . . . . . . . 22 8.5.7 PWM control for performance improvement . . 22 8.6 Class-D amplification . . . . . . . . . . . . . . . . . . . 23 8.7 Protection mechanisms . . . . . . . . . . . . . . . . . 23 8.7.1 Thermal foldback . . . . . . . . . . . . . . . . . . . . . . 24 8.7.2 Overtemperature protection . . . . . . . . . . . . . . 24 8.7.3 Overcurrent protection . . . . . . . . . . . . . . . . . . 24 8.7.4 Overvoltage protection . . . . . . . . . . . . . . . . . . 24 8.7.5 Undervoltage protections . . . . . . . . . . . . . . . . 24 8.7.6 Overdissipation protection . . . . . . . . . . . . . . . 25 8.7.7 Window protection . . . . . . . . . . . . . . . . . . . . . 25 8.7.8 Lock protection . . . . . . . . . . . . . . . . . . . . . . . . 25 8.7.9 Underfrequency protection . . . . . . . . . . . . . . . 25 8.7.10 Overfrequency protection . . . . . . . . . . . . . . . . 8.7.11 Invalid BCK protection . . . . . . . . . . . . . . . . . . 8.7.12 DC blocking . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.13 Overview protections . . . . . . . . . . . . . . . . . . . 2 9 I C bus interface and register settings . . . . . 9.1 I2C bus interface. . . . . . . . . . . . . . . . . . . . . . . 9.2 I2C bus TFA9812 device addresses . . . . . . . . 9.3 I2C write cycle description . . . . . . . . . . . . . . . 9.4 I2C read cycle description . . . . . . . . . . . . . . . 9.5 Top-level register map . . . . . . . . . . . . . . . . . . 9.5.1 Interpolator settings and soft mute. . . . . . . . . 9.5.2 Volume control . . . . . . . . . . . . . . . . . . . . . . . . 9.5.3 Digital input format . . . . . . . . . . . . . . . . . . . . . 9.5.4 Equalizer configuration. . . . . . . . . . . . . . . . . . 9.5.5 Equalizer settings . . . . . . . . . . . . . . . . . . . . . . 9.5.6 PWM signal control . . . . . . . . . . . . . . . . . . . . 9.5.7 Digital-in clock configuration. . . . . . . . . . . . . . 9.5.8 Thermal foldback control . . . . . . . . . . . . . . . . 9.5.9 TFA9812 temperature . . . . . . . . . . . . . . . . . . 9.5.10 Miscellaneous status . . . . . . . . . . . . . . . . . . . 9.6 Overview of functional control in each control mode . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . 13.2 AC characteristics . . . . . . . . . . . . . . . . . . . . . 13.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information . . . . . . . . . . . . . . . . . 14.1 Output power estimation . . . . . . . . . . . . . . . . 14.2 Output current limiting . . . . . . . . . . . . . . . . . . 14.3 Speaker configuration and impedance. . . . . . 14.4 Typical application schematics . . . . . . . . . . . . 14.4.1 I2S slave mode and Legacy control mode . . . 14.4.2 I2S slave mode and I2C control mode . . . . . . 14.4.3 I2S master mode and Legacy control mode . 2 14.4.4 I S master mode and I2C control mode . . . . . 14.5 Curves measured in typical application . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Handling information . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 26 26 26 27 27 27 28 28 29 31 31 32 32 33 35 36 36 37 37 38 39 42 43 44 44 47 48 49 49 50 51 51 52 53 54 55 56 61 62 63 64 64 64 64 continued >> TFA9812_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 30 October 2008 65 of 66 TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I2S input 18.4 19 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Contact information. . . . . . . . . . . . . . . . . . . . . 64 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 October 2008 Document identifier: TFA9812_1