NX5DV713 Dual supply 1-of-2 VGA switch Rev. 1 — 24 November 2011 Product data sheet 1. General description The NX5DV713 is a dual supply 1-to-2 VGA switch. It integrates high-bandwidth SPDT switches with level-translating buffers and level translating switches to provide switching of input RGB, H-sync, V-sync and DDC signals to either of two output channels. The NX5DV713 is characterized for operation from 40 C to +85 C. 2. Features and benefits RGB switches: Low ON resistance (4 typical) Low ON capacitance (12 pF typical) Low output skew (50 ps) Low power consumption (< 2 A) Level translation of sync and DDC signals Over-voltage tolerant inputs ESD protection: HBM JESD22-A114F Class 3A exceeds 4 kV MM JESD22-A115-A exceeds 200 V CDM JESD22-C101D exceeds 1000 V IEC61000-4-2 contact discharge exceeds 4 kV for I/Os Specified from 40 C to +85 C 3. Applications Notebook Computers Docking stations Digital projectors Computer monitors Servers Storage NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 4. Ordering information Table 1. Ordering information Type number NX5DV713HF Package Temperature range Name Description Version 40 C to +85 C HWQFN32 plastic thermal enhanced very very thin quad flat package; no leads; 32 terminals; body 3 6 0.75 mm SOT1180-1 5. Functional diagram VCC(B) R0 R1 R2 G0 G1 G2 B0 B1 B2 VCC(A) SEL CONTROL LOGIC H1 H0 H2 LEVEL TRANSLATING MUX V0 V1 V2 RPU RPU SDA1 RPU RPU LEVEL TRANSLATING SWITCH SCL1 RPU RPU SDA0 SDA2 SCL0 SCL2 aaa-001597 Fig 1. Logic symbol NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 6. Pinning information 28 GND 29 TEST 30 SEL 32 VCC(A) terminal 1 index area 31 GND 6.1 Pinning R0 1 27 R1 G0 2 26 R2 GND 3 25 G1 VCC(A) 4 24 G2 B0 5 23 n.c.(2) H0 6 V0 7 21 B2 n.c. 8 20 H1 SDA0 9 19 H2 SCL0 10 18 V1 NX5DV713 GND 11 22 B1 17 V2 VCC(B) 16 SCL2 15 SCL1 14 SDA2 13 SDA1 12 GND(1) aaa-001608 Transparent top view (1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to GND. (2) Pin can be connected to VCC(A). Fig 2. Pin configuration SOT1180-1 (HWQFN32) 6.2 Pin description Table 2. Pin description Symbol Pin Description R0, G0, B0 1, 2, 5 RGB input or output GND 3, 11, 28, 31 ground (0 V) VCC(A) 4, 32 supply voltage A H0 6 horizontal sync input V0 7 n.c. 8, vertical sync input 23[2] not connected SDA0 9 SDA0 input or output SCL0 10 SCL0 input or output SDA1, SDA2 12, 13 SDAn input or output SCL1, SCL2 14, 15 SCLn input or output VCC(B) 16 supply voltage B V1, V2 18, 17 vertical sync output NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch Table 2. Pin description …continued Symbol Pin Description H1, H2 20, 19 horizontal sync output R1, G1, B1, R2, G2, B2 27, 25, 22, 26, 24, 21 RGB input or output TEST[1] 29 test pin (active LOW) SEL 30 select input [1] Test pin used to enable test mode. For normal usage, this pin must be connected to VCC(A). [2] Pin can be connected to VCC(A). 7. Functional description The NX5DV713 integrates high-bandwidth SPDT switches, level-translating buffers and level translating SPDT switches to provide a complete solution for 1-to-2 switching of VGA signals. A select input (SEL) is used to determine which output is selected. 7.1 RGB switches The NX5DV713 provides three identical single pole double throw high-bandwidth switches to route standard VGA RGB signals (see Table 3). Table 3. Function table RGB H = HIGH voltage level; L = LOW voltage level; X = Don’t care. Input Switch SEL L R0 to R1; G0 to G1; B0 to B1 H R0 to R2; G0 to G2; B0 to B2 7.2 H-Sync/V-Sync level translator The horizontal and vertical synchronization buffers have inputs (H0, V0) referenced to VCC(A) and outputs (H1, V1 and H2,V2) that are referenced to VCC(B). This allows level translation of synchronization signals from as low as 2.0 V up to 5.5 V and supports low-voltage CMOS or TTL-compatible graphics controllers meeting the VESA specification for output drive of 8 mA. Table 4. Function table HV H = HIGH voltage level; L = LOW voltage level; X = Don’t care. Input Switch SEL NX5DV713 Product data sheet L H1 = H0; V1 = V0; H2, V2 = L H H2 = H0; V2 = V0; H1, V1 = L All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 7.3 Display-Data Channel Multiplexer The NX5DV713 provides two identical SPDT active-level translating switches to route DDC signals (See Table 5). The switch outputs are limited to a diode drop less than the voltage applied on VCC(A). To provide VESA I2C-compatible signals 3.3 V should be applied to VCC(A). If voltage translation is not required VCC(A) should be connected to VCC(B). Switch terminals include integrated pull-up resistors; inputs (SDA0, SCL0) are pulled up to VCC(A), outputs (SDA1, SCL1 and SDA2, SCL2) are pulled up to VCC(B). Table 5. Function table DDC H = HIGH voltage level; L = LOW voltage level; X = Don’t care. Input Switch SEL L SDA0 to SDA1, SCL0 to SCL1 H SDA0 to SDA2, SCL0 to SCL2 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) VCC(B) Min Max Unit supply voltage A 0.5 +6 V supply voltage B 0.5 +6 V input voltage [1] 0.5 +6 V VSW switch voltage [1] 0.5 +6 V IIK input clamping current VI < 0.5 V 50 - mA ISK switch clamping current VI < 0.5 V 50 - mA IOK output clamping current VO < 0 V 50 - mA IO output current VO = 0 V to VCC(B) - 50 mA ICC supply current ICC(A) or ICC(B) - 100 mA IGND ground current 100 - mA ISW switch current VSW > 0.5 V or VSW < 6 V; source or sink current - 30 mA VSW > 0.5 V or VSW < 6 V; pulsed at 1 ms duration, < 10 % duty cycle; peak current - 90 mA 65 +150 C - 250 mW VI Tstg Conditions storage temperature total power dissipation Ptot Tamb = 40 C to +85 C [1] The minimum input voltage rating may be exceeded if the input current rating is observed. [2] For HWQFN32 package: above 137 C the value of Ptot derates linearly with 20.5 mW/K. NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 [2] © NXP B.V. 2011. All rights reserved. 5 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter VCC(A) VCC(B) Conditions Min Typ Max Unit supply voltage A 2 3.3 5.5 V supply voltage B 4.5 5.0 5.5 V Tamb ambient temperature operating in free-air 40 +25 +85 C t/V input transition rise and fall rate VCC(A) = 2.3 V to 2.7 V [1] - 20 - ns/V VCC(A) = 3 V to 3.6 V [1] - 10 - ns/V VCC(A) = 4.5 V to 5.5 V [1] - 5 - ns/V [1] Applies to control signal levels. 10. Static characteristics Table 8. Static characteristics VCC(B) = 4.5 V to 5.5 V; VCC(A) = 2 V to 5.5 V, unless otherwise specified; Voltages are referenced to GND (ground = 0 V) Symbol Parameter Tamb = 40 C to +85 C Conditions Min Typ[1] Max Unit General ICC(A) supply current A VCC(A) = 3.3 V; for H1, H2, V1, V2: IO = 0 A; SCLn, SDAn unconnected - - 2.0 A ICC(B) supply current B VCC(B) = 5.0 V; for H1, H2, V1, V2: IO = 0 A; SCLn, SDAn unconnected - - 2.0 A VIH HIGH-level input voltage VCC(A) = 3 V to 3.6 V 2 - - V VIL LOW-level input voltage VCC(A) = 3 V to 3.6 V - - 0.8 V VH hysteresis voltage - 50 - mV II input leakage current - - 1 A VOH HIGH-level output voltage IO = 8 mA VCC(B) 0.5 - - V VOL LOW-level output voltage IO = 8 mA - - 0.5 V IOFF power-off leakage current VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 0 V to 5.5 V - - 1 A HV buffer VCC(B) = VCC(A) = 5.5 V; VI = GND to VCC(A) RGB switches IS(OFF) OFF-state leakage current VCC(B) = 5.5 V; VI = 0.3 V or 5.5 V; VO = 0 V to VCC(B); See Figure 3 - - 1 A IS(ON) ON-state leakage current VCC(B) = 5.5 V; VI = 0.3 V or 5.5 V; VO = 0 V to VCC(B); See Figure 4 - - 1 A RON ON resistance VI = 0.7 V; ISW = 10 mA; See Figure 5 and Figure 6 [4] - 4 - RON ON resistance mismatch between channels VI = GND to 0.7 V; ISW = 10 mA [2] - 0.5 - RON(flat) ON resistance (flatness) VI = GND to 0.7 V; ISW = 10 mA [3] - 0.5 - CS(OFF) OFF-state capacitance - 4.5 - pF NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch Table 8. Static characteristics …continued VCC(B) = 4.5 V to 5.5 V; VCC(A) = 2 V to 5.5 V, unless otherwise specified; Voltages are referenced to GND (ground = 0 V) Symbol CS(ON) Parameter Tamb = 40 C to +85 C Conditions Unit Min Typ[1] Max - 12 - pF - - 1 A - 9 - ON-state capacitance SDAn, SCLn [5] IS(OFF) OFF-state leakage current VCC(B) = 5.5 V; VCC(A) = 3.6 V; SCL0, SDA0, SCL1, SCL2, SDA1, SDA2 = VCC(A) or GND; VO = 0 V to VCC(B); See Figure 3 RON ON resistance VCC(A) = 2 V; VI = 0.4 V; ISW = ±2 mA; See Figure 5 and Figure 7 CS(ON) ON-state capacitance - 15 - pF RPU pull-up resistance - 4.7 - k VCC(A) = 2.3 V to 2.7 V 1.7 - V VCC(A) = 3.0 V to 3.6 V 2.0 - V Control Logic (SEL) HIGH-level input voltage VIH LOW-level input voltage VIL VH hysteresis voltage II input leakage current VCC(A) = 4.5 V to 5.5 V 0.7VCC(A) - VCC(A) = 2.3 V to 2.7 V - - 0.7 V VCC(A) = 3.0 V to 3.6 V - - 0.8 V VCC(A) = 4.5 V to 5.5 V - - 0.3VCC(A) V - 50 - mV - - 1 A VCC(A) = 5.5 V; VI = GND to VCC(A) [1] All typical values are measured at VCC(B) = 5 V, VCC(A) = 3.3 V and Tamb = 25 C unless otherwise specified. V [2] Measured at identical VCC, temperature and input voltage. [3] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. [4] Guarantees the LOW level. [5] Guarantees the HIGH level. 10.1 Test circuits and waveforms VCC(A) VIH or VIL VCC(B) SEL x1 1 x0 x2 2 switch switch SEL 1 VIH 2 VIL IS GND VI VO aaa-001599 x0 refers to R0, G0, B0, SCL0 or SDA0 x1 refers to R1, G1, B1, SCL1 or SDA1 x2 refers to R2, G2, B2, SCL2 or SDA2 Fig 3. Test circuit for measuring OFF-state leakage current NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch VCC(A) VIH or VIL IS VCC(B) SEL x1 1 x0 x2 2 switch SEL 1 VIH 2 VIL switch GND VI VO aaa-001600 x0 refers to R0, G0, B0, SCL0 or SDA0 x1 refers to R1, G1, B1, SCL1 or SDA1 x2 refers to R2, G2, B2, SCL2 or SDA2 Fig 4. Test circuit for measuring ON-state leakage current VCC(A) VIL or VIH V VCC(B) VSW SEL x1 1 x0 x2 2 switch SEL 1 VIL 2 VIH switch GND VI ISW aaa-001601 x0 refers to R0, G0, B0, SCL0 or SDA0 x1 refers to R1, G1, B1, SCL1 or SDA1 x2 refers to R2, G2, B2, SCL2 or SDA2 RON = VSW / ISW. Fig 5. Test circuit for measuring ON resistance NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 001aan178 10 RON (Ω) 8 6 (1) (2) 4 (3) 2 0 0 0.2 0.4 0.6 0.8 1.0 VI (V) (1) Tamb = 85 C (2) Tamb = 25 C (3) Tamb = 40 C Fig 6. ON resistance as a function of input voltage (RGB switches) 001aan179 60 VCC(A) = 3.3 V RON (Ω) VCC(A) = 5.0 V 45 30 (1) (2) (3) (1) (2) (3) 15 0 0 1 2 3 4 VI (V) (1) Tamb = 85 C (2) Tamb = 25 C (3) Tamb = 40 C Fig 7. ON resistance as a function of input voltage (DDC switches) NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; Voltages are referenced to GND (ground = 0 V; VCC(B) = 4.5 V to 5.5 V; VCC(A) = 2 V to 5.5 V. Symbol Parameter Tamb = 40 C to +85 C Conditions Unit Min Typ[1] Max - 3 - ns [2] tpd propagation delay H0 to H1, H2 and V0 to V1, V2; See Figure 8 and Figure 9 ten enable time SEL to all other outputs; See Figure 10 and Figure 11 - 15 - ns tdis disable time SEL to all other outputs; See Figure 10 and Figure 11 - 5 - ns tb-m break-before-make time See Figure 12 - 10 - ns tsk(o) output skew time Skew between any Rn, Gn and Bn ports; see Figure 8 - 50 - ps [1] [3] All typical values are measured at VCC(B) = 5 V; VCC(A) = 3.3 V; Tamb = 25 C. [2] tpd is the same as tPLH and tPHL. [3] Guaranteed by design. 11.1 Test circuits and waveforms VI input VM VM GND tPLH tPHL VOH output 1 VM VM VM VM VOL VOH output 2 VOL 001aan180 Measurement points are given in Table 10. tsk(o) = tPLH1 tPLH2 Fig 8. Table 10. Propagation delay and output skew times Measurement points Input Output VM VI VX VM 0.5VCC(A) GND to VCC(A) 0.9VOH 0.5VCC(B) NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch VCC VI VO G DUT RT CL RL 001aan183 Test data is given in Table 11. Definitions: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including test jig and probe. RL = Load resistance. Fig 9. Table 11. Test circuit for measuring propagation delay times (SEL to H1, H2, V1, V2) Test data Input Load tr, tf CL RL 2.5 ns 10 pF 1 k VI SEL input VM VM GND ten VOH output OFF to HIGH HIGH to OFF tdis VX VX GND tdis VOH output HIGH to OFF OFF to HIGH ten VX VX GND aaa-001602 Measurement points are given in Table 10. Logic level: VOH is typical output voltage level that occurs with the output load. Fig 10. Enable and disable times NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch VI G V VO RL VCC(A) VCC(B) SEL x1 1 x0 x2 2 switch CL VEXT = 1 V GND aaa-001603 Test data is given in Table 12. x0 refers to R0, G0, B0, SCL0 or SDA0 x1 refers to R1, G1, B1, SCL1 or SDA1 x2 refers to R2, G2, B2, SCL2 or SDA2 Fig 11. Test circuit for measuring enable and disable times Table 12. Test data Input Load tr, tf VI CL RL 2.5 ns GND to VCC(A) 10 pF 100 NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch VI G V VO RL VCC(A) VCC(B) SEL x1 x0 x2 CL VEXT = 1 V GND aaa-001604 a. Test circuit VI 0.5VI 0.9VO 0.9VO VO tb-m 001aag572 b. Input and output measurement points Test data is given in Table 12. x0 refers to R0, G0, B0, SCL0 or SDA0 x1 refers to R1, G1, B1, SCL1 or SDA1 x2 refers to R2, G2, B2, SCL2 or SDA2 Fig 12. Test circuit for measuring break-before-make times NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 12. Additional dynamic characteristics Table 13. Additional dynamic characteristics VCC(B) = 5.0 V 10 %, VCC(A) = 2 V to 5.5 V, unless otherwise specified; Voltages are referenced to GND (ground = 0 V) Symbol Parameter Tamb = 40 C to +85 C Conditions f(3dB) 3 dB frequency response RL = 50 ; see Figure 13 ins Insertion loss fi = 1 MHz; RL = RS =50 ; see Figure 13 Xtalk crosstalk between switches; fi = 50 MHz; RL = 50 ; see Figure 13 [1] Unit Min Typ Max - 600 - MHz - 0.6 - dB - 50 - dB [1] [1] fi is biased at 0.5VCC. 12.1 Test circuits 5V 10 nF VCC(A) VCC(B) NETWORK ANALYZER VI 50 Ω 50 Ω R0, G0, B0 fi NX5DV713 GND or VCC SEL R1, G1, B1 R2, G2, B2 VO measurement reference 50 Ω 50 Ω 50 Ω GND aaa-001609 Insertion loss is measured between R0 and R1 or R2 on each switch; crosstalk is measured from one channel to the other channel. Fig 13. Test circuit for measuring crosstalk and insertion loss NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 13. Application information The NX5DV713 provides the level shifting necessary to drive two standard VGA ports from a graphic controller as low as 2.2 V. Internal buffers drive the HSYNC and VSYNC signals to VGA standard TTL levels. The DDC multiplexer provides level shifting by clamping signals to a diode drop less than VCC(A) (See Figure 14). Connect VCC(A) to 3.3 V for normal operation, or to VCC(B) to disable voltage clamping for DDC signals +3.3 V +5.0 V 0.1 μF 0.1 μF VCC(A) 3 GRAPHICS CONTROLLER 2 2 VCC(B) R0, B0, G0 R1, B1, G1 H0, V0 SDA0, SCL0 SDA1, SCL1 H1, V1 R2, B2, G2 SDA2, SCL2 GND or VCC SEL H2, V2 3 2 2 VGA PORT 3 2 2 VGA PORT2 GND aaa-001606 Fig 14. Typical operating circuit NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 14. Package outline HWQFN32: plastic thermal enhanced very very thin quad flat package; no leads; 32 terminals; 3 x 6 x 0.75 mm A B D SOT1180-1 terminal 1 index area E A A1 c detail X e1 e 12 16 C C A B C v w b y y1 C L 17 11 e e2 Eh 27 1 terminal 1 index area 32 28 X Dh 0 2.5 scale Dimensions Unit mm 5 mm A(1) A1 b max 0.80 0.05 0.25 nom 0.75 0.02 0.20 min 0.70 0.00 0.15 c D(1) Dh E(1) Eh 0.2 3.1 3.0 2.9 1.9 1.8 1.7 6.1 6.0 5.9 4.9 4.8 4.7 e e1 0.4 1.6 e2 L 4 0.4 0.3 0.2 v w y 0.07 0.05 0.08 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT1180-1 --- --- --- sot1180-1_po European projection Issue date 10-07-02 10-08-05 Fig 15. Package outline SOT1180-1 (HWQFN32) NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 16 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 15. Abbreviations Table 14. Abbreviations Acronym Description CDM Charged Device Model DDC Display Data Channel ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model RGB Red Green Blue SPDT Single-Pole Double-Throw TTL Transistor-Transistor Logic VESA Video Electronics Standards Association 16. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes NX5DV713 v.1 20111124 Product data sheet - - NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 17 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. 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Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 18 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] NX5DV713 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 November 2011 © NXP B.V. 2011. All rights reserved. 19 of 20 NX5DV713 NXP Semiconductors Dual supply 1-of-2 VGA switch 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 8 9 10 10.1 11 11.1 12 12.1 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 RGB switches . . . . . . . . . . . . . . . . . . . . . . . . . . 4 H-Sync/V-Sync level translator . . . . . . . . . . . . . 4 Display-Data Channel Multiplexer . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Test circuits and waveforms . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Test circuits and waveforms . . . . . . . . . . . . . . 10 Additional dynamic characteristics . . . . . . . . 14 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 24 November 2011 Document identifier: NX5DV713