PHILIPS PCF2103EU/2/F2

INTEGRATED CIRCUITS
DATA SHEET
PCF2103 family
LCD controllers/drivers
Product specification
File under Integrated Circuits, IC12
1998 May 11
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
CONTENTS
8.7
8.8
8.9
8.10
8.11
8.12
8.12.1
8.12.2
8.12.3
8.12.4
8.12.5
8.12.6
8.12.7
Set CGRAM address
Set DDRAM address
Read busy flag and address counter
Write data to CGRAM or DDRAM
Read data from CGRAM or DDRAM
Extended function set instructions and features
New instructions
Icon control
IM
IB
Screen configuration
Display configuration
Reducing current consumption
9
INTERFACE TO MICROCONTROLLER
9.1
9.2
9.2.1
9.2.2
9.2.3
Parallel interface
I2C-bus interface
Characteristics of the I2C-bus
I2C-bus protocol
Definitions
10
LIMITING VALUES
11
HANDLING
12
DC CHARACTERISTICS
13
AC CHARACTERISTICS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
LCD bias voltage generator
Oscillator
External clock
Power-on reset
Power-down mode
Registers
Busy flag
Address Counter (AC)
Display Data RAM (DDRAM)
Character Generator ROM (CGROM)
Character Generator RAM (CGRAM)
Cursor control circuit
Timing generator
LCD row and column drivers
Reset function
14
TIMING CHARACTERISTICS
8
INSTRUCTIONS
15
APPLICATION INFORMATION
8.1
8.2
8.3
8.3.1
8.3.2
8.4
8.4.1
8.4.2
8.4.3
8.5
8.6
8.6.1
8.6.2
8.6.3
Clear display
Return home
Entry mode set
I/D
S
Display control (and partial power-down mode)
D
C
B
Cursor or display shift
Function set
DL (parallel mode only)
M
H
15.1
15.3
15.4
8-bit operation, 1-line display using internal
reset
4-bit operation, 1-line display using internal
reset
8-bit operation, 2-line display
I2C-bus operation, 1-line display
16
BONDING PAD LOCATIONS
17
DEFINITIONS
18
LIFE SUPPORT APPLICATIONS
19
PURCHASE OF PHILIPS I2C COMPONENTS
1998 May 11
15.2
2
Philips Semiconductors
Product specification
LCD controllers/drivers
1
PCF2103 family
FEATURES
• Single-chip LCD controller/driver
• 2-line display of up to 12 characters + 120 icons,
or 1-line display of up to 24 characters + 120 icons
• 5 × 7 character format plus cursor; 5 × 8 for kana
(Japanese syllabary) and user defined symbols
2
• Icon mode: reduced current consumption while
displaying icons only(1)
APPLICATIONS
• Telecom equipment
• Portable instruments
• Icon blink function
• Point-of-sale terminals.
• On-chip:
– Generation of intermediate LCD bias voltages
3
– Oscillator requires no external components
(external clock also possible)
GENERAL DESCRIPTION
The PCF2103 family is a low power CMOS LCD controller
and driver, designed to drive a dot matrix LCD display of
2 line by 12 or 1 line by 24 characters with 5 × 8 dot
format. All necessary functions for the display are provided
in a single chip, including on-chip generation of LCD bias
voltages, resulting in a minimum of external components
and lower system current consumption. The PCF2103
interfaces to most microcontrollers via a 4 or 8-bit bus or
via the 2-wire I2C-bus. The chip contains a character
generator and displays alphanumeric and kana
(Japanese) characters. The letter ‘X’ in PCF2103X
characterizes the built-in character set. Various character
sets can be manufactured on request.
• Display data RAM: 80 characters
• Character generator ROM: 240, 5 × 8 characters
• Character generator RAM: 16, 5 × 8 characters;
3 characters used to drive 120 icons, 6 characters used
if icon blink feature is used in application
• 4 or 8-bit parallel bus and 2-wire I2C-bus interface
• CMOS compatible
• 18 row, 60 column outputs
• Mux rates 1 : 18 (for normal operation) and 1 : 2
(for icon-only mode)
• Uses common 11 code instruction set (extended)
• Logic supply voltage range, VDD − VSS = 1.8 to 5.5 V;
chip may be driven with two battery cells
• Display supply voltage range, VLCD − VSS = 2.2 to 6.5 V
• Very low current consumption (20 to 120 µA):
– Icon mode: <25 µA
– Power-down mode: <2.5 µA.
(1) Icon mode is used to save current. When only icons
are displayed, a much lower operating voltage VLCD
can be used and the switching frequency of the LCD
outputs is reduced. In most applications it is possible
to use VDD as VLCD.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF2103EU/2/F2
1998 May 11
−
DESCRIPTION
VERSION
−
chip with bumps in tray
3
Philips Semiconductors
Product specification
LCD controllers/drivers
5
PCF2103 family
BLOCK DIAGRAM
C1 to C60
handbook, full pagewidth
R1 to R18
60
COLUMN DRIVERS
BIAS
VOLTAGE
GENERATOR
VLCD
18
ROW DRIVERS
60
18
DATA LATCHES
SHIFT REGISTER 18-BIT
60
SHIFT REGISTER 5 × 12-BIT
5
OSC
OSCILLATOR
CURSOR AND DATA CONTROL
5
CHARACTER
GENERATOR
RAM (128 × 5)
(CGRAM)
16 CHARACTERS
VDD
CHARACTER
GENERATOR
ROM
(CGROM)
240 CHARACTERS
TIMING
GENERATOR
VSS
8
T1
DISPLAY DATA RAM
(DDRAM)
80 CHARACTERS/BYTES
8
PD
7
7
DISPLAY
ADDRESS
COUNTER
ADDRESS COUNTER
(AC)
7
7
INSTRUCTION
DECODER
PCF2103
DATA
REGISTER
(DR)
8
INSTRUCTION
REGISTER
BUSY
FLAG
8
POWER-ON
RESET
8
I/O BUFFER
MGL259
DB0 to DB3/SA0
DB4 to DB7
E
R/W
RS
SCL
SDA
Fig.1 Block diagram.
1998 May 11
4
Philips Semiconductors
Product specification
LCD controllers/drivers
6
PCF2103 family
PINNING
SYMBOL
DIE PAD
DESCRIPTION
VDD
1
supply voltage
OSC
2
oscillator/external clock input
PD
3
power-down pad input
T1
4
test pad (connected to VSS)
VSS
5
ground
VLCD
6
VLCD input; note 1
R9 to R16
R18
C60 to C1
R8 to R1
7 to 14
15
LCD row driver outputs 9 to 16
LCD row driver output 18
16 to 23, 26 to 50, LCD column driver outputs 60 to 1
53 to 77, 80, 81
82 to 89
LCD row driver outputs 8 to 1
R17
90
LCD row driver output 17
SCL
91
I2C-bus serial clock input
SDA
92
I2C-bus serial data input/output
E
93
data bus clock input
RS
94
register select input
R/W
95
read/write input
DB7
96
bit of bi-directional data bus
DB6
97
bit of bi-directional data bus
DB5
98
bit of bi-directional data bus
DB4
99
bit of bi-directional data bus
DB3/SA0
100
bit of bi-directional data bus/I2C-bus address pin
DB2
101
bit of bi-directional data bus
DB1
102
bit of bi-directional data bus
DB0
103
bit of bi-directional data bus
Note
1. This is the voltage used for the generation of LCD bias levels.
1998 May 11
5
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 1
PCF2103 family
Pin functions; note 1
NAME
RS
FUNCTION
register select
DESCRIPTION
RS selects the register to be accessed for read and write; there is an internal pull-up
on this pin
RS = 0 selects the instruction register for write and the busy flag and address
counter for read
RS = 1 selects the data register for both read and write
R/W
read/write
R/W selects either the read (R/W = 1) or write (R/W = 0) operation; there is an
internal pull-up on this pin
E
data bus clock
pin E is set HIGH to signal the start of a read or write operation; data is clocked in or
out of the chip on the negative edge of the clock
DB7 to DB0 data bus
the bi-directional, 3-state data bus transfers data between the system controller and
the PCF2103; DB7 may be used as the busy flag, signalling that internal operations
are not yet completed; in 4-bit operations the 4 higher order lines DB7 to DB4 are
used; DB3 to DB0 must be left open-circuit; there is an internal pull-up on each of the
data lines
C1 to C60
column driver
outputs
these pins output the data for columns
R1 to R18
row driver
outputs
these pins output the row select waveforms to the display; R17 and R18 drive the
icons
VLCD
LCD power
supply
positive power supply for the liquid crystal display
OSC
oscillator
when the on-chip oscillator is used this pin must be connected to VDD; an external
clock signal, if used, is input at this pin
SCL
serial clock line
input for the I2C-bus clock signal
SDA
serial data line
I/O for the I2C-bus data line
SA0
address pin
the hardware sub-address line is used to program the device sub-address for two
different PCF2103s on the same I2C-bus
T1
test pad
must be connected to VSS; not user accessible
PD
power-down pad PD selects chip power-down mode; for normal operation PD = 0
Note
1. When the I2C-bus is used, the parallel interface pin E must be defined as E = 0. In I2C-bus read mode DB7 to DB0
should be connected to VDD or left open-circuit.
a) When the parallel bus is used, pins SCL and SDA must be connected to VSS or VDD; they may not be left
unconnected.
b) If the 4-bit interface is used without reading out from the PCF2103 (i.e. R/W is set permanently to logic 0), the
unused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.
1998 May 11
6
Philips Semiconductors
Product specification
LCD controllers/drivers
7
PCF2103 family
FUNCTIONAL DESCRIPTION
7.1
LCD bias voltage generator
The intermediate bias voltages for the LCD display are generated on-chip. This removes the need for an external
resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on
the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships given
in Tables 2 and 3. Using a 5-level bias scheme for 1 : 18 maximum rate allows VLCD <5 V for most LCD liquids.
Table 2
Optimum/maximum values for VOP (off pixels start darkening; Voff = Vth)
MUX RATE
NUMBER OF LEVELS
Von/Vth
1 : 18
5
1.272
3.7
5.2 V
1:2
3
2.236
2.283
3.9 V
VOP/Vth
VOP (typical; for Vth = 1.4 V)
Table 3
VOP/Vth
VOP (typical; for Vth = 1.4 V)
Minimum values for VOP (on pixels clearly visible; Von > Vth)
MUX RATE
NUMBER OF LEVELS
Von/Vth
1 : 18
5
1.12
3.2
4.6 V
1:2
3
1.2
1.5
2.1 V
7.2
During power-down, the whole chip is being reset and will
restart with a clear display after power-down. Therefore,
the whole chip has to be initialized after a power-down as
after an initial power-up.
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
pin OSC must be connected to VDD.
7.3
7.6
External clock
The PCF2103 has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed. The instruction register stores instruction codes
such as ‘display clear’ and ‘cursor shift’, and address
information for the Display Data RAM (DDRAM) and
Character Generator RAM (CGRAM). The instruction
register can be written from but not read by the system
controller. The data register temporarily stores data to be
read from the DDRAM and CGRAM. When reading, data
from the DDRAM or CGRAM corresponding to the address
in the instruction register is written to the data register prior
to being read by the ‘read data’ instruction.
If an external clock is to be used, it is input at the OSC pin.
The resulting display frame frequency is given by
f osc
f frame = -----------3072
Only in the power-down state is the clock allowed to be
stopped (OSC connected to VSS), otherwise the LCD is
frozen in a DC state.
7.4
Power-on reset
The on-chip power-on reset block initializes the chip after
power-on or power failure. This is a synchronous reset and
requires 3 oscillator cycles to be executed. Afterwards, a
clear display is initiated.
7.5
7.7
Busy flag
The busy flag indicates the internal status of the PCF2103.
Logic 1 indicates that the chip is busy and further
instructions will not be accepted. The busy flag is output at
pin DB7 when RS = 0 and R/W = 1. Instructions should
only be written after checking that the busy flag is logic 0
or waiting for the required number of cycles.
Power-down mode
The chip can be put into power-down mode where all static
currents are switched off (no internal oscillator, no bias
level generation, all LCD outputs are internally connected
to VSS) when PD = 1.
1998 May 11
Registers
7
Philips Semiconductors
Product specification
LCD controllers/drivers
7.8
PCF2103 family
Address Counter (AC)
7.11
The address counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
commands ‘set CGRAM address’ and ‘set DDRAM
address’. After a read/write operation the address counter
is automatically incremented or decremented by 1.
The address counter contents are output to the bus
(DB6 to DB0) when RS = 0 and R/W = 1.
7.9
Up to 16 user defined characters may be stored in the
CGRAM. Some CGRAM characters (see Fig.14) are also
used to drive icons (6 if icons blink and both icon rows are
used in application; 3 if no blink but both icon rows are
used in application; 0 if no icons are driven by the icon
rows). The CGROM and CGRAM use a common address
space, of which the first column is reserved for the
CGRAM (see Fig.6). Figure 7 shows the addressing
principle for the CGRAM.
Display Data RAM (DDRAM)
The DDRAM stores up to 80 characters of display data
represented by 8-bit character codes. RAM locations
which are not used for storing display data can be used as
general purpose RAM. The basic RAM-to-display
addressing scheme is shown in Fig.2. With no display shift
the characters represented by the codes in the first
24 RAM locations starting at address 00 in line 1 are
displayed. Figures 3 and 4 show the display mapping for
right and left shift respectively.
7.12
7.13
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
7.14
LCD row and column drivers
The PCF2103 contains 18 row and 60 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. R17 and R18 drive the icon rows.
Character Generator ROM (CGROM)
The Character Generator ROM (CGROM) generates
240 character patterns in 5 × 8 dot format from 8-bit
character codes. Figure 6 shows the character set that is
currently implemented.
Table 4
Cursor control circuit
The cursor control circuit generates the cursor (underline
and/or cursor blink as shown in Fig.5) at the DDRAM
address contained in the address counter. When the
address counter contains the CGRAM address the cursor
will be inhibited.
When data is written to or read from the DDRAM
wrap-around occurs from the end of one line to the start of
the next line. When the display is shifted each line wraps
around within itself, independently of the others. Thus all
lines are shifted and wrapped around together.
The address ranges and wrap-around operations for the
various modes are shown in Table 4.
7.10
Character Generator RAM (CGRAM)
The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 8, 9 and 10 show typical waveforms.
Unused outputs should be left unconnected.
Address space and wrap-around operation
MODE
ADDRESS SPACE
READ/WRITE
WRAP-AROUND(1)
DISPLAY SHIFT
WRAP-AROUND(2)
1 × 24
00H to 4FH
4FH to 00H
4FH to 00H
2 × 12
00H to 27H; 40H to 67H
27H to 40H; 67H to 00H
27H to 00H; 67H to 40H
Notes
1. Moves to next line.
2. Stays within line.
1998 May 11
8
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth
display
position
DDRAM
address
PCF2103 family
non-displayed DDRAM addresses
1 2 3 4 5
22 23 24
00 01 02 03 04
15 16 17 18 19
4C 4D 4E 4F
1-line display
non-displayed DDRAM address
DDRAM
address
1 2 3 4 5
10 11 12
00 01 02 03 04
09 0A 0B 0C 0D
1 2 3 4 5
10 11 12
40 41 42 43 44
49 4A 4B 4C 4D
24 25 26 27
line 1
64 65 66 67
line 2
MGE991
2-line display
Fig.2 DDRAM-to-display mapping: no shift.
handbook,display
halfpage
position
1
5
22 23 24
DDRAM
address
4F 00 01 02 03
2 3
4
14 15 16
1-line display
1
DDRAM
address
5
10 11 12
27 00 01 02 03
2 3
08 09 0A
1
5
10 11 12
67 40 41 42 43
48 49 4A
2 3
4
4
line 1
line 2
MGE992
2-line display
Fig.3 DDRAM-to-display mapping: right shift.
1998 May 11
9
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
handbook,display
halfpage
5
22 23 24
01 02 03 04 05
1
16 17 18
position
DDRAM
address
2 3
4
1-line display
5
10 11 12
01 02 03 04 05
1
0A 0B 0C
1
5
10 11 12
41 42 43 44 45
4A 4B 4C
DDRAM
address
2 3
2 3
4
4
line 1
line 2
MGE993
2-line display
Fig.4 DDRAM-to-display mapping: left shift.
cursor
MGA801
5 x 7 dot character font
alternating display
cursor display example
blink display example
Fig.5 Cursor and blink display examples.
1998 May 11
10
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MGD689
Fig.6 Character set ‘E’ in CGROM.
1998 May 11
11
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
character codes
handbook, full pagewidth
CGRAM
address
(DDRAM data)
7
6
5
4
3
2
higher
order
bits
0
0
0
0
0
0
1
0
6
lower
order
bits
0
0
0
0
0
0
0
0
5
4
3
2
higher
order
bits
0
1
0
0
0
0
0
0
character patterns
(CGRAM data)
1
0
4
lower
order
bits
0
1
3
higher
order
bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2
1
character code
(CGRAM data)
0
4
3
2
1
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
1
0
0
0
lower
order
bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
cursor
position
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
character
pattern
example 1
character
pattern
example 2
MGE995
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with
the cursor. Data in the 8th position will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.6.
As shown in Figs 6 and 7, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds
to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in
the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address
counter’ command; see Table 7.
Fig.7 Relationship between CGRAM addresses and data and display patterns.
1998 May 11
12
Philips Semiconductors
Product specification
LCD controllers/drivers
frame n
handbook, full pagewidth
ROW 1
PCF2103 family
frame n + 1
state 1 (ON)
state 2 (OFF)
VLCD
V2
V3/V4
V5
VSS
R1
R2
R3
R4
R5
ROW 9
R6
VLCD
V2
V3/V4
V5
VSS
ROW 2
VLCD
V2
V3/V4
V5
VSS
COL1
VLCD
V2
V3/V4
V5
VSS
COL2
VLCD
V2
V3/V4
V5
VSS
R7
R8
R9
VOP
0.5VOP
0.25VOP
state 1 0 V
−0.25VOP
−0.5VOP
−VOP
VOP
0.5VOP
0.25VOP
state 2 0 V
−0.25VOP
−0.5VOP
−VOP
MGE996
1 2 3
18 1 2 3
18
Fig.8 Typical LCD waveforms; character mode.
1998 May 11
13
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
frame n + 1
frame n
handbook, full pagewidth
only icons are
driven (MUX 1 : 2)
VLCD
ROW 17
2/3
1/3
VSS
VLCD
ROW 18
2/3
1/3
VSS
VLCD
ROW 1 to 16
2/3
1/3
VSS
VLCD
COL 1 ON/OFF
2/3
1/3
VSS
VLCD
COL 2 OFF/ON
2/3
1/3
VSS
VLCD
COL 3 ON/ON
2/3
1/3
VSS
VLCD
COL 4 OFF/OFF
2/3
1/3
VSS
MGE997
Fig.9 Mux 1 : 2 LCD waveforms; icon mode.
1998 May 11
14
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth V
PIXEL
PCF2103 family
frame n + 1
frame n
state 1 (ON)
state 1
COL 1 ROW 17
state 2
COL 2 ROW 17
VOP
2/3 VOP
1/3 VOP
state 2 (OFF)
R17
R18
0
R1-16
−1/3 VOP
−2/3 VOP
−VOP
state 3 (OFF)
VOP
2/3 VOP
1/3 VOP
0
−1/3 VOP
−2/3 VOP
−VOP
VOP
2/3 VOP
1/3 VOP
state 3
COL 1 0
ROW 1 to 16 −1/3 VOP
−2/3 VOP
−VOP
MGE998
VON(rms) = 0.745 VOP.
VOFF(rms) = 0.333 VOP.
V ON
= 2.23
D = ------------V OFF
Fig.10 Mux 1 : 2 LCD waveforms; icon mode.
1998 May 11
15
Philips Semiconductors
Product specification
LCD controllers/drivers
7.15
PCF2103 family
Reset function
The PCF2103 automatically initializes (resets) when power is turned on. The reset executes a ‘clear display’ instruction,
requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 5.
Table 5
State after reset
STEP
INSTRUCTION
1
clear display
2
entry mode set
3
4
display control
function set
RESET STATE (BIT/REGISTER)
RESET STATE (DESCRIPTION)
I/D = 1
+1 (increment)
S=0
no shift
D=0
display off
C=0
cursor off
B=0
cursor character blink off
DL = 1
8-bit interface
M=0
1-line display
H=0
normal instruction set
5
default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until initialization
ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 16 and 17
6
icon control
IM, IB = 00
icons/icon blink disabled
7
display/screen configuration
L, P, Q = 000
default configurations
8
I2C-bus
1998 May 11
interface reset
16
Philips Semiconductors
Product specification
LCD controllers/drivers
8
PCF2103 family
In normal use, instructions that perform data transfer with
internal RAM are used most frequently. However,
automatic incrementing by 1 (or decrementing by 1) of
internal RAM addresses after each data write lessens the
microcontroller program load. The display shift in particular
can be performed concurrently with display data write,
enabling the designer to develop systems in minimum time
with maximum programming efficiency.
INSTRUCTIONS
Only two PCF2103 registers, the Instruction Register (IR)
and the Data Register (DR) can be directly controlled by
the microcontroller. Before internal operation, control
information is stored temporarily in these registers to allow
interface to various types of microcontrollers which
operate at different speeds or to allow interface to
peripheral control ICs. The format for instructions when
I2C-bus control is used is shown in Table 6. The PCF2103
operation is controlled by the instructions given in Table 7
together with their execution time. Details are explained in
subsequent sections.
During internal operation, no instruction other than the
‘read busy flag and address counter’ instruction will be
executed. Because the busy flag is set to logic 1 while an
instruction is being executed, the user should verify that
the busy flag is at logic 0 before sending the next
instruction or wait for the maximum instruction execution
time, as given in Table 7. An instruction sent while the
busy flag is logic 1 will not be executed.
Instructions are of 4 types, those that:
1. Designate PCF2103 functions such as display format,
data length, etc.
2. Set internal RAM addresses
3. Perform data transfer with internal RAM
4. Others.
Table 6
Instruction set for I2C-bus commands
CONTROL BYTE
Co RS
0
0
0
0
COMMAND BYTE
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1
Note
1. R/W is set together with the slave address.
1998 May 11
I2C-BUS COMMANDS
17
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INSTRUCTION
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED
CLOCK
CYCLES
H = 0 or 1
NOP
0
0
0
0
0
0
0
0
0
0
no operation
3
Function set
0
0
0
0
1
DL
0
M
0
H
sets interface Data Length (DL) and number of
display lines (M); extended instruction set control
(H)
3
Read busy flag
and address
counter
0
1
BF
reads the Busy Flag (BF) indicating internal
operating is being performed and reads address
counter contents
0
Read data
1
1
read data
reads data from CGRAM or DDRAM
3
Write data
1
0
write data
writes data from CGRAM or DDRAM
3
Clear display
0
0
0
0
0
0
0
0
0
1
clears entire display and sets DDRAM address 0
in address counter
165
Return home
0
0
0
0
0
0
0
0
1
0
sets DDRAM address 0 in address counter; also
returns shifted display to original position; DDRAM
contents remain unchanged
3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
sets cursor move direction and specifies shift of
display; these operations are performed during
data write and read
3
Display control
0
0
0
0
0
0
1
D
C
B
sets entire display on/off (D), cursor on/off (C) and
blink of cursor position character (B); D = 0
(display off) puts chip into power-down mode
3
Cursor/display
shift
0
0
0
0
0
1
S/C
R/L
0
0
moves cursor and shifts display without changing
DDRAM contents
3
Set CGRAM
address
0
0
0
1
sets CGRAM address; bit 6 is to be set by the
command ‘set DDRAM address’; look at the
description of the commands
3
Set DDRAM
address
0
0
1
sets DDRAM address
3
AC
Philips Semiconductors
Instruction set with parallel bus commands; note 1
LCD controllers/drivers
1998 May 11
Table 7
H=0
18
Product specification
ADD
PCF2103 family
ACG
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R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED
CLOCK
CYCLES
H=1
Reserved
0
0
0
0
0
0
0
0
0
1
do not use
−
Screen
configuration
0
0
0
0
0
0
0
0
1
L
set screen configuration
3
Display
configuration
0
0
0
0
0
0
0
1
P
Q
set display configuration
3
Icon control
0
0
0
0
0
0
1
IM
IB
0
set icon mode (IM), icon blink (IB)
3
Reserved
0
0
0
0
0
1
X
X
X
X
do not use
−
Reserved
0
0
0
1
X
X
X
X
X
X
do not use
−
Reserved
0
0
1
X
X
X
X
X
X
X
do not use
−
Philips Semiconductors
RS
LCD controllers/drivers
1998 May 11
INSTRUCTION
Note
1. X = don’t care.
19
Product specification
PCF2103 family
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 8
PCF2103 family
Specification of mnemonics used in Table 7
BIT
LOGIC 0
LOGIC 1
I/D
decrement
increment
S
display freeze
display shift
D
display off
display on
C
cursor off
cursor on
B
cursor character blink off: character at cursor
position does not blink
cursor character blink on: character at cursor
position blinks
S/C
cursor move
display shift
R/L
left shift
right shift
DL
4 bits
8 bits
H
use basic instruction set
use extended instruction set
L (ignored,
if M = 1)
left/right screen: standard connection
(as in PCF2114);
1st 12 characters of 24: columns are from 1 to 60;
2nd 12 characters of 24: columns are from 1 to 60
left/right screen: mirrored connection
(as in PCF2116);
1st 12 characters of 24: columns are from 1 to 60;
2nd 12 characters of 24: columns are from 60 to 1
P
column data: left to right (as in PCF2116);
column data is displayed from 1 to 60
column data: right to left;
column data is displayed from 60 to 1
Q
row data: top to bottom (as in PCF2116);
row data is displayed from 1 to 16 and icon row
data is in 17 and 18
row data: bottom to top;
row data is displayed from 16 to 1 and icon
row data is in 18 and 17
IM
character mode; full display
icon mode; only icons displayed
IB
icon blink disabled
icon blink enabled
M
1-line by 24 display
2-line by 12 display
C0
last control byte; see Table 6
another control byte follows after data/command
1998 May 11
20
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4
IR0
AC4
AC0
DR4
DR0
busy flag and
address counter read
instruction
write
data register
read
MGA804
Fig.11 4-bit transfer example.
RS
R/W
E
internal
DB7
internal operation
IR7
IR3
instruction
write
busy
AC3
busy flag
check
not
busy
AC3
busy flag
check
D7
instruction
write
IR7 and IR3: instruction 7th and 3rd bit.
AC3: address counter 3rd bit.
D7 and D3: data 7th and 3rd bit.
Fig.12 An example of 4-bit data transfer timing sequence.
1998 May 11
21
D3
MGA805
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
RS
R/W
E
internal
DB7
internal operation
data
instruction
write
busy
busy flag
check
not
busy
busy
busy flag
check
busy flag
check
data
instruction
write
MGA806
Fig.13 Example of busy flag checking timing sequence.
8.1
Clear display
8.3
‘Clear display’ writes character code 20H into all DDRAM
addresses (the character pattern for character code 20H
must be a blank pattern), sets the DDRAM address
counter to logic 0 and returns display to its original position
if it was shifted. Thus, the display disappears and the
cursor or blink position goes to the left edge of the display.
Sets entry mode I/D = 1 (increment mode). S of entry
mode does not change.
8.3.1
8.3.2
S
When S = 1, the entire display shifts either to the right
(I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus
it looks as if the cursor stands still and the display moves.
The display does not shift when reading from the DDRAM,
or when writing into or reading out of the CGRAM. When
S = 0 the display does not shift.
Return home
‘Return home’ sets the DDRAM address counter to logic 0
and returns display to its original position if it was shifted.
DDRAM contents do not change. The cursor or blink
position goes to the left of the first display line. I/D and S of
entry mode do not change.
1998 May 11
I/D
When I/D = 1 (0) the DDRAM or CGRAM address
increments (decrements) by 1 when data is written into or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor underline and cursor
character blink are inhibited when the CGRAM is
accessed.
The instruction ‘clear display’ requires extra execution
time. This may be allowed by checking the Busy Flag (BF)
or by waiting until the 165 clock cycles have elapsed.
The latter must be applied where no read-back options are
foreseen, as in some Chip-On-Glass (COG) applications.
8.2
Entry mode set
22
Philips Semiconductors
Product specification
LCD controllers/drivers
8.4
8.4.1
PCF2103 family
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the ‘cursor shift’.
Display control (and partial power-down mode)
D
The display is on when D = 1 and off when D = 0. Display
data in the DDRAM are not affected and can be displayed
immediately by setting D to logic 1.
8.6
8.6.1
When the display is off (D = 0) the chip is in partial
power-down mode:
• Bias generator is turned off.
3 oscillator cycles are required after sending the
‘display off’ instruction to ensure all outputs are at VSS,
afterwards OSC can be stopped. If the oscillator is running
during partial power-down mode (‘display off’) the chip can
still execute instructions. Even lower current consumption
is obtained by inhibiting the oscillator (OSC = VSS).
‘Function set’ from the I2C-bus interface sets the DL bit to
logic 1.
To ensure IDD < 2 µA the parallel bus pins DB7 to DB0
should be connected to VDD; RS and R/W to VDD or left
open-circuit and PD to VDD. Recovery from power-down
mode: put PD back to logic 0, if necessary put OSC back
to VDD and send a ‘display control’ instruction with D = 1 to
enable the display again.
8.6.2
C
When H = 1 the extended range of instructions will be
used. These are mainly for controlling the display
configuration and the icons.
B
8.7
The character indicated by the cursor blinks when B = 1.
The cursor character blink is displayed by switching
between display characters and all dots on with a period of
f osc
approximately 1 s, with f BLINK = --------------52224
The cursor underline and the cursor character blink can be
set to display simultaneously.
Set CGRAM address
‘Set CGRAM address’ sets bits 5 to 0 of the CGRAM
address ACG into the address counter (binary A[5] to A[0]).
Data can then be written to or read from the CGRAM.
Attention: the CGRAM address uses the same address
register as the DDRAM address and consists of 7 bits
(binary A[6] to A[0]). With the ‘set CGRAM address’
command, only bits 5 down to 0 are set. Bit 6 can be set
using the ‘set DDRAM address’ command first, or by using
the auto-increment feature during CGRAM write.
All bits 6 to 0 can be read using the
‘read busy flag and address counter’ command.
Cursor or display shift
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2-line displays, the
cursor moves to the next line when it passes the last
position (40) of the line. When the displayed data is shifted
repeatedly all lines shift at the same time; displayed
characters do not shift into the next line.
1998 May 11
H
When H = 0 the chip can be programmed via the standard
11 instruction codes used in the PCF2116 and other LCD
controllers.
The cursor is displayed when C = 1 and inhibited when
C = 0. Even if the cursor disappears, the display functions
I/D, etc. remain in operation during display data write.
The cursor is displayed using 5 dots in the 8th line (see
Fig.5).
8.5
M
Chooses either 1-line by 24 display (M = 0) or 2-line by
12 display (M = 1).
8.6.3
8.4.3
DL (PARALLEL MODE ONLY)
Sets interface data width. Data is sent or received in bytes
(DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4)
when DL = 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus. In a 4-bit
application DB3 to DB0 should be left open-circuit (internal
pull-ups). Hence in the first ‘function set’ instruction after
power-on N and H are set to logic 1. A second
‘function set’ must then be sent (2 nibbles) to set N and H
to their required values.
• The LCD outputs are connected to VSS
8.4.2
Function set
When writing to the lower part of the CGRAM, ensure that
bit 6 of the address is not set (e.g. by an earlier DDRAM
write or read action).
23
Philips Semiconductors
Product specification
LCD controllers/drivers
8.8
PCF2103 family
8.12
Set DDRAM address
‘Set DDRAM address’ sets the DDRAM address ADD into
the address counter (binary A[6] to A[0]). Data can then be
written to or read from the DDRAM.
8.9
8.12.1
Extended function set instructions and
features
NEW INSTRUCTIONS
H = 1 sets the chip into alternate instruction set mode.
Read busy flag and address counter
8.12.2
‘Read busy flag and address counter’ reads the Busy Flag
(BF) and Address Counter (AC). BF = 1 indicates that an
internal operation is in progress. The next instruction will
not be executed until BF = 0, so BF should be checked
before sending another instruction.
ICON CONTROL
The PCF2103 can drive up to 120 icons. See Fig.14 for
CGRAM to icon mapping.
8.12.3
IM
At the same time, the value of the address counter
expressed in binary A[6] to A[0] is read out. The address
counter is used by both CGRAM and DDRAM, and its
value is determined by the previous instruction.
When IM = 0 the chip is in character mode. In character
mode characters and icons are driven (mux 1 : 18).
8.10
8.12.4
When IM = 1 the chip is in icon mode. In icon mode only
the icons are driven (mux 1 : 2).
Write data to CGRAM or DDRAM
IB
‘Write data’ writes binary 8-bit data D[7] to D[0] to the
CGRAM or the DDRAM.
Icon blink control is independent of the cursor/character
blink function.
Whether the CGRAM or DDRAM is to be written into is
determined by the previous ‘set CGRAM address’ or ‘set
DDRAM address’ command. After writing, the address
automatically increments or decrements by 1, in
accordance with the entry mode. Only bits D[4] to D[0] of
CGRAM data are valid, bits D[7] to D[5] are ‘don’t care’.
When IB = 0 icon blink is disabled. Icon data is stored in
CGRAM character 0 to 2 (3 × 8 × 5 = 120 bits for
120 icons).
8.11
When IB = 1 icon blink is enabled. In this case each icon is
controlled by two bits. Blink consists of two half phases
(corresponding to the cursor on and off phases called even
and odd phases hereafter).
Read data from CGRAM or DDRAM
Icon states for the even phase are stored in CGRAM
characters 0 to 2 (3 × 8 × 5 = 120 bits for 120 icons).
These bits also define the icon state when the icon blink is
not used.
‘Read data’ reads binary 8-bit data D[7] to D[0] from the
CGRAM or DDRAM.
The most recent ‘set address’ command determines
whether the CGRAM or DDRAM is to be read.
Icon states for the odd phase are stored in CGRAM
character 4 to 6 (another 120 bits for the 120 icons). When
icon blink is disabled CGRAM characters 4 to 6 may be
used as normal CGRAM characters.
The ‘read data’ instruction gates the content of the Data
Register (DR) to the bus while pin E is HIGH. After pin E
goes LOW again, internal operation increments (or
decrements) the AC and stores RAM data corresponding
to the new AC into the DR.
It should be noted that there are only three instructions that
update the Data Register (DR). These are:
• ‘set CGRAM address’
• ‘set DDRAM address’
• ‘read data’ from CGRAM or DDRAM.
Other instructions (e.g. ‘write data’, ‘cursor/display shift’,
‘clear display’, ‘return home’) do not modify the data
register content.
1998 May 11
24
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 9
PCF2103 family
Blink effect for icons and cursor character blink
PARAMETER
EVEN PHASE
ODD PHASE
Cursor underline
on
off
Cursor character blink
block (all on)
normal (display character)
Icons
state 1: CGRAM characters 0 to 2
state 2: CGRAM characters 4 to 6
handbook, full pagewidth
display:
COL 1 to 5
COL 6 to 10
COL 56 to 60
ROW 17 –
1
2
3
4
5
6
7
8
9
10
ROW 18 –
61
62
63
64
65
66
67
68
69
70
56
57
58
59
60
116 117 118 119 120
MGE999
block of 5 columns
icon
no.
handbook, full
pagewidth
phase
ROW/COL
character codes
7
6
5
4
3
2
CGRAM address
1
MSB
0
6
LSB
MSB
5
4
3
2
1
CGRAM data
0
4
3
2
1
LSB MSB
icon view
0
LSB
1-5
even
17/1-5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
6-10
even
17/6-10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
11-15
even
17/11-15
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
56-60
even
17/56-60
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
61-65
even
18/1-5
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
116-120
even
18/56-60
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
0
1
1-5
odd (blink)
17/1-5
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
116-120
odd (blink)
18/56-60
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
MGG001
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off.
Data in character codes 0 to 2 define the icon states when icon blink is disabled or during the even phase when icon blink is enabled.
Data in character codes 4 to 6 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).
Fig.14 CGRAM-to-icon mapping.
1998 May 11
25
Philips Semiconductors
Product specification
LCD controllers/drivers
8.12.5
PCF2103 family
SCREEN CONFIGURATION
9
The default value for L is logic 0. In the event of L = 0 the
two halves of a split screen are connected in a standard
way i.e. column 1/61, 2/62 to 60/120. In the event of L = 1
the two halves of a split screen are connected in a mirrored
way i.e. column 1/120, 2/119 to 60/61. This allows single
layer PCB or glass layout.
8.12.6
9.1
In 8-bit mode data is transferred as 8-bit bytes using the
8 data lines DB7 to DB0. Three further control lines E, RS
and R/W are required; see Table 1.
DISPLAY CONFIGURATION
In 4-bit mode data is transferred in two cycles of 4 bits
each using pins DB7 to DB4 for transaction. The higher
order bits (corresponding to DB7 to DB4 in 8-bit mode) are
sent in the first cycle and the lower order bits (DB3 to DB0
in 8-bit mode) in the second. Data transfer is complete
after two 4-bit data transfers. Note that two cycles are also
required for the busy flag check. 4-bit operation is selected
by instruction. See Figs 11 to 14 for examples of bus
protocol.
REDUCING CURRENT CONSUMPTION
Reducing current consumption can be achieved by one of
the options mentioned in Table 10.
Table 10 Reducing current consumption
ORIGINAL MODE
ALTERNATIVE MODE
Character mode
icon mode (control bit IM)
Display on
display off (control bit D)
1998 May 11
Parallel interface
The PCF2103 can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
The default value for P and Q is logic 0. P = 1 mirrors the
column data whereas Q = 1 mirrors the row data.
8.12.7
INTERFACE TO MICROCONTROLLER
In 4-bit mode pins DB3 to DB0 must be left open-circuit.
They are pulled up to VDD internally.
26
Philips Semiconductors
Product specification
LCD controllers/drivers
9.2
9.2.1
PCF2103 family
I2C-bus interface
9.2.2
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I2C-bus configuration for the different
PCF2103 read and write cycles is shown in Figs 20 to 21.
The slow down feature of the I2C-bus protocol (receiver
holds SCL low during internal operations) is not used in the
PCF2103.
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a Serial Clock Line (SCL).
Both lines must be connected to a positive supply via a
pull-up resistor. Data transfer may be initiated only when
the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH-level signal put on the bus
by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
9.2.3
DEFINITIONS
• Transmitter: the device which sends the data to the bus
• Receiver: the device which receives the data from the
bus
• Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
• Slave: the device addressed by a master
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a STOP
condition.
1998 May 11
I2C-BUS PROTOCOL
• Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock
signals of two or more devices.
27
Philips Semiconductors
Product specification
LCD controllers/drivers
MASTER
TRANSMITTER/
RECEIVER
PCF2103 family
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.15 System configuration.
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.16 Bit transfer.
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.17 Definition of START and STOP conditions.
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.18 Acknowledgement on the I2C-bus.
1998 May 11
28
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Philips Semiconductors
LCD controllers/drivers
handbook, full pagewidth
1998 May 11
acknowledgement
from PCF2103
S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
A P
0
slave address
R/W
Co
2n ≥ 0 bytes
1 byte
Co
n ≥ 0 bytes
update
data pointer
29
MGL250
S
0 1 1 1 0 1 A 0
0
PCF2103
slave address
R/W
Product specification
PCF2103 family
Fig.19 Master transmits to slave receiver; write mode.
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DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE(1)
0
slave address
2n
R/W
0 bytes
n ≥ 0 bytes
1 byte
Co
A
Philips Semiconductors
S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
LCD controllers/drivers
agewidth
1998 May 11
acknowledgement
Co
acknowledgement
acknowledgement
no acknowledgement
30
S
SLAVE
ADDRESS
S
A 1 A
0
DATA BYTE
A
n bytes
R/W
Co
DATA BYTE
1 P
last byte
update
data pointer
update
data pointer
MGG003
Product specification
Fig.20 Master reads after setting word address; write word address, set RS; ‘read data’.
PCF2103 family
(1) Last data byte is a dummy byte (may be omitted).
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
acknowledgement
from PCF2103
dbook, full pagewidth
S
SLAVE
ADDRESS
S
A 1 A
0
acknowledgement
from master
DATA BYTE
A
no acknowledgement
from master
n bytes
R/W
Co
1 P
DATA BYTE
last byte
update
data pointer
update
data pointer
MGL251
Fig.21 Master reads slave immediately after first byte; read mode (RS previously defined).
dbook, full pagewidth
SDA
t BUF
tf
t LOW
SCL
t HD;STA
t HD;DAT
tr
t HIGH
t SU;DAT
SDA
MGA728
t SU;STA
Fig.22 I2C-bus timing diagram.
1998 May 11
31
t SU;STO
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+6.5
V
VLCD
LCD supply voltage
−0.5
+7.5
V
VI(1)
input voltage on pins OSC, RS, R/W, E and DB7 to DB0 −0.5
VDD + 0.5
V
VI(2)
input voltage on pins SCL and SDA
−0.5
+6.5
V
VO
output voltage on pins R1 to R18, C1 to C60 and VLCD
−0.5
VLCD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
IDD, ISS and ILCD
VDD, VSS or VLCD current
−50
+50
mA
Ptot
total power dissipation
−
400
mW
P/out
power dissipation per output
−
100
mW
Tstg
storage temperature
−65
+150
°C
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
1998 May 11
32
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
12 DC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
1.8
−
5.5
V
VLCD
LCD supply voltage
2.2
−
6.5
V
ISS
supply current
note 1
−
60
120
µA
VDD = 3 V; VLCD = 5 V;
notes 1 and 2
−
45
80
µA
icon mode; VDD = 3 V;
VLCD = 2.5 V;
notes 1 and 2
−
25
45
µA
power-down mode;
VDD = 3 V; VLCD = 2.5 V;
DB7 to DB0,
RS and R/W = 1;
OSC = 0; PD = 1; note 1
−
2
6
µA
note 3
−
1.3
1.6
V
VPOR
power-on reset voltage
Logic
VIL
LOW-level input voltage on
pins T1, E, RS, R/W,
DB7 to DB0 and SA0
0
−
0.3VDD
V
VIH
HIGH-level input voltage on
pins T1, E, RS, R/W,
DB7 to DB0 and SA0
0.7VDD
−
VDD
V
VIL(PD)
LOW-level input voltage on
pin PD
0
−
0.2VDD
V
VIH(PD)
HIGH-level input voltage on
pin PD
0.8VDD
−
VDD
V
VIL(OSC)
LOW-level input voltage on
pin OSC
0
−
VDD − 1.5 V
VIH(OSC)
HIGH-input voltage on pin OSC
VDD − 0.1 −
VDD
V
IOL(DB)
LOW-level output current on
pins DB7 to DB0
VOL = 0.4 V; VDD = 5 V
1.6
4
−
mA
IOH(DB)
HIGH-level output current on
pins DB7 to DB0
VOH = 4 V; VDD = 5 V
−1
−8
−
mA
Ipu
pull-up current on
pins DB7 to DB0
VI = VSS
0.04
0.12
1
µA
IL
leakage current on pins OSC, E,
RS, R/W, DB7 to DB0 and SA0
VI = VDD or VSS
−1
−
+1
µA
1998 May 11
33
Philips Semiconductors
Product specification
LCD controllers/drivers
SYMBOL
PARAMETER
PCF2103 family
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus
SDA AND SCL
VIL
LOW-level input voltage
0
−
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
−
5.5
V
IL
input leakage current
−1
−
+1
µA
Ci
input capacitance
note 4
−
−
10
pF
IOL
LOW-level output current
pin SDA
VOL = 0.4 V; VDD = 5 V
3
−
−
mA
VI = VDD or VSS
LCD outputs
Ro(ROW)
row output resistance on
pins R1 to R18
note 5
−
10
30
kΩ
Ro(COL)
column output resistance on
pins C1 to C60
note 5
−
15
40
kΩ
Vbias(tol)
bias tolerance on
pins R1 to R18 and C1 to C60
note 6
−
20
130
mV
Notes
1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive.
2. Tamb = 25 °C; fosc = 200 kHz.
3. Resets all logic when VDD < VPOR; 3 oscillator clock cycles required.
4. Tested on sample basis.
5. Resistance of output terminals (R1 to R18 and C1 to C60) with a load current of 20 µA; outputs measured one at a
time.
6. LCD outputs open-circuit.
1998 May 11
34
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
13 AC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.2 − 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ffr(LCD)
LCD frame frequency (internal clock)
fosc
oscillator frequency (not available at any pin)
140
250
450
kHz
fosc(ext)
external clock frequency
140
−
450
kHz
tOSCST
oscillator start-up time after PD going from
logic 1 to logic 0
−
200
300
µs
VDD = 5.0 V
45
81
147
Hz
Bus timing characteristics: parallel interface; note 1
WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2103); see Fig.23
Ten(cy)
enable cycle time
500
−
−
ns
tW(en)
enable pulse width
220
−
−
ns
tsu(A)
address set-up time
50
−
−
ns
th(A)
address hold time
25
−
−
ns
tsu(D)
data set-up time
60
−
−
ns
th(D)
data hold time
25
−
−
ns
READ OPERATION (READING DATA FROM PCF2103 TO MICROCONTROLLER); see Fig.24
Ten(cy)
enable cycle time
500
−
−
ns
tW(en)
enable pulse width
220
−
−
ns
tsu(A)
address set-up time
50
−
−
ns
th(A)
address hold time
25
−
−
ns
td(D)
data delay time
−
−
150
ns
th(D)
data hold time
20
−
100
ns
Timing characteristics: I2C-bus interface; note 1
fSCL
SCL clock frequency
−
−
400
kHz
tLOW
SCL clock LOW period
1.3
−
−
µs
tHIGH
SCL clock HIGH period
0.6
−
−
µs
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tr
SCL and SDA rise time
−
−
300
ns
tf
SCL and SDA fall time
−
−
300
ns
CB
capacitive bus line load
−
−
400
pF
tSU;STA
set-up time for a repeated START condition
0.6
−
−
µs
tHD;STA
START condition hold time
0.6
−
−
µs
tSU;STO
set-up time for STOP condition
0.6
−
−
µs
tSW
tolerable spike width on bus
−
−
50
ns
Note
1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.
1998 May 11
35
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
14 TIMING CHARACTERISTICS
handbook, full pagewidth
RS
VIH
V IL
VIH
VIL
tsu(A)
R/W
th(A)
V IL
VIL
tW(en)
VIH
VIL
E
th(A)
VIH
VIL
VIL
t h(D)
tsu(D)
VIH
VIL
DB0 to DB7
VIH
VIL
DATA
VALID
Ten(cy)
MGL252
Fig.23 Parallel bus write operation sequence; writing data from microcontroller to PCF2103.
handbook, full pagewidth
RS
VIH
V IL
VIH
VIL
tsu(A)
R/W
th(A)
VIH
VIH
tW(en)
E
VIL
VIH
th(A)
VIH
VIL
t d(D)
DB0 to DB7
VIL
t h(D)
VOH DATA
VOL VALID
Ten(cy)
VOH
VOL
MGL253
Fig.24 Parallel bus read operation sequence; reading data from PCF2103 to microcontroller.
1998 May 11
36
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
15 APPLICATION INFORMATION
handbook, full pagewidth
P20
RS
P21
R/W
P22
E
P80CL51
R17, R18
2
R1 to R16
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
16
PCF2103
P17 to P10
C1 to C60
DB7 to DB0
8
60
MGL254
Fig.25 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, full pagewidth
P10
RS
P11
R/W
P12
E
P80CL51
R17, R18
2
R1 to R16
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
16
PCF2103
P17 to P14
C1 to C60
DB7 to DB4
4
60
MGL255
Fig.26 Direct connection to 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
OSC
VDD
2
R1 to R16
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
VDD
VLCD
PCF2103
100
nF
VSS
R17, R18
16
VLCD
100
nF
C1 to C60
60
VSS
8
DB7 to DB0 E
RS R/W
MGL256
Fig.27 Application example using parallel interface.
1998 May 11
37
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth
PCF2103 family
VDD VDD
VDD
OSC
VDD
R17, R18
2
R1 to R16
2 × 12 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
VDD
VLCD
100
nF
DB3/SAO
PCF2103
16
VLCD
100
nF
VSS
VSS
C1 to C60
60
R17, R18
2
R1 to R16
1 × 24 CHARACTER
LCD DISPLAY
PLUS 120 ICONS
SCL SDA
VSS
OSC
VDD
VDD
VLCD
100
nF
VSS
SCL SDA
DB3/SAO
PCF2103
16
VLCD
100
nF
C1 to C60
VSS
60
SCL SDA
MASTER TRANSMITTER
PCF84C81A; P80CL410
MGL257
Fig.28 Application using I2C-bus interface.
1998 May 11
38
Philips Semiconductors
Product specification
LCD controllers/drivers
15.1
PCF2103 family
Since the display shift operation changes display position
only and DDRAM contents remain unchanged, display
data entered first can be displayed when the ‘return home’
operation is performed.
4-bit operation, 1-line display using internal
reset
The program must set functions prior to 4-bit operation;
Table 11 shows an example. When power is turned on,
8-bit operation is automatically selected and the PCF2103
attempts to perform the first write as an 8-bit operation.
Since nothing is connected to DB0 to DB3, a rewrite is
then required. However, since one operation is completed
in two accesses of 4-bit operation, a rewrite is required to
set the functions (see Table 11 step 3). Thus, DB4 to DB7
of the ‘function set’ are written twice.
15.2
15.3
8-bit operation, 2-line display
For a 2-line display, the cursor automatically moves from
the first to the second line after the 40th digit of the first line
has been written. Thus, if there are only 8 characters in the
first line, the DDRAM address must be set after the eighth
character is completed (see Table 6). It should be noted
that both lines of the display are always shifted together;
data does not shift from one line to the other.
8-bit operation, 1-line display using internal
reset
15.4
Table 12 shows an example of a 1-line display in 8-bit
operation. The PCF2103 functions must be set by the
‘function set’ instruction prior to display. Since the DDRAM
can store data for 80 characters, the RAM can be used for
advertising displays when combined with display shift
operation.
I2C-bus operation, 1-line display
A control byte is required with most commands
(see Table 15).
Table 11 4-bit operation, 1-line display example; using internal reset
STEP
INSTRUCTION
DISPLAY
1
power supply on (PCF2103 is initialized by
the internal reset circuit)
2
function set
3
4
5
6
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
0
OPERATION
initialized; no display appears
sets to 4-bit operation; in this instance operation
is handled as 8-bit by initialization and only this
instruction completes with one write
function set
0
0
0
0
1
0
0
0
0
0
0
0
sets to 4-bit operation, selects 1-line display and
VLCD = V0; 4-bit operation starts from this point
and resetting is needed
display on/off control
0
0
0
0
0
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is
blank after initialization
_
sets mode to increment the address by 1 and to
shift the cursor to the right at the time of write to
the DD/CGRAM; display is not shifted
P_
writes ‘P’; the DDRAM has already been selected
by initialization at power-on; the cursor is
incremented by 1 and shifted to the right
entry mode set
0
0
0
0
0
0
0
0
0
1
1
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
1
1
0
0
0
0
0
1998 May 11
39
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INSTRUCTION
1
power supply on (PCF2103 is initialized by the internal reset
function)
2
function set
RS
0
3
0
0
1
1
0
0
0
0
sets to 8-bit operation, selects 1-line display
0
0
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is blank after
initialization
0
0
0
0
1
1
0
_
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of the write to the
DD/CGRAM; display is not shifted
1
0
0
0
0
P_
writes ‘P’; the DDRAM has already been selected by
initialization at power-on; the cursor is incremented by 1
and shifted to the right
0
1
0
0
0
PH_
entry mode set
0
5
initialized; no display appears
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
40
6
OPERATION
display mode on/off control
0
4
DISPLAY
Philips Semiconductors
STEP
LCD controllers/drivers
1998 May 11
Table 12 8-bit operation, 1-line display example; using internal reset (character set ‘A’)
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
7 to 11
writes ‘H’
|
|
12
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
1
1
PHILIPS_
writes ‘S’
0
0
0
0
1
1
1
PHILIPS_
sets mode for display shift at the time of write
0
0
0
0
0
HILIPS _
writes space
0
1
1
0
1
ILIPS
writes ‘M’
13
entry mode set
14
‘write data’ to CGRAM/DDRAM
0
1
15
0
0
0
0
1
‘write data’ to CGRAM/DDRAM
1
16
0
0
0
1
0
M_
|
|
|
Product specification
0
PCF2103 family
1
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17
‘write data’ to CGRAM/DDRAM
18
cursor/display shift
1
0
19
0
1
0
0
1
1
1
1
MICROKO
writes ‘O’
0
0
1
0
0
0
0
MICROKO
shifts only the cursor position to the left
0
0
0
0
1
0
0
0
0
MICROKO
shifts only the cursor position to the left
‘write data’ to CGRAM/DDRAM
1
21
0
0
OPERATION
cursor/display shift
0
20
0
DISPLAY
0
0
1
0
0
0
0
1
1
ICROKO
writes ‘C’ correction; the display moves to the left
0
0
1
1
1
0
0
MICROKO
shifts the display and cursor to the right
0
0
1
0
1
0
0
MICROCO_
shifts only the cursor to the right
0
1
1
0
1
ICROCOM_
writes ‘M’
cursor/display shift
0
0
0
22
cursor/display shift
23
‘write data’ to CGRAM/DDRAM
0
1
0
0
0
0
1
0
24
Philips Semiconductors
INSTRUCTION
LCD controllers/drivers
1998 May 11
STEP
|
41
|
|
25
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS M
returns both display and cursor to the original position
(address 0)
Product specification
PCF2103 family
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INSTRUCTION
1
power supply on (PCF2103 is initialized by the internal reset
function)
2
function set
RS
0
3
0
1
1
0
0
0
0
sets to 8-bit operation, selects 1-line display
0
0
42
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is blank after
initialization
0
0
0
0
0
0
1
1
0
_
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of the write to the
DD/CGRAM; display is not shifted
0
0
0
0
0
0
_
sets the CGRAM address to position of character 0; the
CGRAM is selected
0
1
0
1
0
_
set CGRAM address
0
6
0
entry mode set
0
5
initialized; no display appears
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
OPERATION
display mode on/off control
0
4
DISPLAY
Philips Semiconductors
STEP
LCD controllers/drivers
1998 May 11
Table 13 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’)
0
0
1
‘write data’ to CGRAM/DDRAM
1
0
0
0
0
7
writes data to CGRAM for icon even phase; icons appear
|
|
8
set CGRAM address
0
9
0
0
1
1
1
0
0
0
0
_
0
1
0
1
0
_
sets the CGRAM address to position of character 4; the
CGRAM is selected
‘write data’ to CGRAM/DDRAM
1
0
0
0
0
10
writes data to CGRAM for icon odd phase
|
0
12
0
0
1
1
0
0
0
1
_
sets H = 1
0
0
0
0
1
0
1
0
_
icons blink
0
0
1
1
0
0
0
1
_
sets H = 0
icon control
0
13
0
0
function set
0
0
Product specification
function set
PCF2103 family
|
11
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0
1
0
0
0
0
0
0
0
sets the DDRAM address to the first position; DDRAM is
selected
1
0
0
0
0
P_
writes ‘P’; the cursor is incremented by 1 and shifted to
the right
0
1
0
0
0
PH_
writes ‘H’
‘write data’ to CGRAM/DDRAM
1
16
OPERATION
set DDRAM address
0
15
DISPLAY
0
0
1
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
17 to 20
|
|
21
Philips Semiconductors
14
INSTRUCTION
LCD controllers/drivers
1998 May 11
STEP
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS
returns both display and cursor to the original position
(address 0)
43
Product specification
PCF2103 family
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INSTRUCTION
1
power supply on (PCF2103 is initialized by the internal reset
function)
initialized; no display appears
2
function set
sets to 8-bit operation; selects 2-line display and voltage
generator off
RS
0
3
DISPLAY
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
0
0
0
display on/off control
turns on display and cursor; entire display is blank after
initialization
_
0
4
5
0
0
0
0
0
1
1
1
0
entry mode set
0
0
0
0
0
0
0
1
1
44
_
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of write to the CG/DDRAM;
display is not shifted
P_
writes ‘P’; the DDRAM has already been selected by
initialization at power-on; the cursor is incremented by 1
and shifted to the right
0
‘write data’ to CGRAM/DDRAM
1
OPERATION
0
0
1
0
1
0
0
0
0
6 to 10
Philips Semiconductors
STEP
LCD controllers/drivers
1998 May 11
Table 14 8-bit operation, 2-line display example; using internal reset
|
|
|
11
‘write data’ to CGRAM/DDRAM
writes ‘S’
PHILIPS_
1
12
0
0
1
0
1
0
0
1
1
set DDRAM address
PHILIPS
0
1
1
0
0
0
0
0
0
_
‘write data’ to CGRAM/ DDRAM
writes ‘M’
1
14 to 19
0
0
1
0
0
1
1
0
1
M_
|
|
|
Product specification
PHILIPS
PCF2103 family
0
13
sets DDRAM address to position the cursor at the head of
the 2nd line
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DISPLAY
‘write data’ to CGRAM/DDRAM
OPERATION
writes ‘O’
PHILIPS
1
21
0
0
1
0
0
1
1
1
1
MICROCO_
‘write data’ to CGRAM/DDRAM
sets mode for display shift at the time of write
PHILIPS
0
22
0
0
0
0
0
0
1
1
1
MICROCO_
‘write data’ to CGRAM/DDRAM
HILIPS
1
0
0
1
0
0
1
1
0
1
23
writes ‘M’; display is shifted to the left; the first and second
lines shift together
ICROCOM_
|
Philips Semiconductors
20
INSTRUCTION
LCD controllers/drivers
1998 May 11
STEP
|
|
24
return home
PHILIPS
45
0
0
0
0
0
0
0
0
1
0
returns both display and cursor to the original position
(address 0)
MICROCOM
Product specification
PCF2103 family
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INSTRUCTION
1
I2C-bus
2
slave address for write
DISPLAY
start
initialized; no display appears
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
3
4
1
1
1
0
1
0
0
1
during the acknowledge cycle SDA will be pulled-down by the
PCF2103
send a control byte for ‘function set’
Co
RS
0
0
0
0
0
0
Ack
0
0
0
0
0
0
0
0
1
control byte sets RS for following data bytes
function set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
5
0
1
X
0
0
0
0
selects 1-line display; SCL pulse during acknowledge cycle
starts execution of instruction
1
display on/off control
_
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
6
0
0
0
1
1
1
0
turns on display and cursor; entire display shows character 20H
(blank in ASCII-like character sets)
1
entry mode set
_
46
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
7
OPERATION
0
0
Philips Semiconductors
STEP
LCD controllers/drivers
1998 May 11
Table 15 Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1)
0
0
1
1
0
sets mode to increment the address by 1 and to shift the cursor
to the right at the time of write to the DDRAM or CGRAM; display
is not shifted
1
I2C-bus start
_
for writing data to DDRAM, RS must be set to 1; therefore a
control byte is needed
8
slave address for write
_
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
9
1
1
0
1
0
0
1
_
RS
0
0
0
0
0
0
Ack
0
1
0
0
0
0
0
0
1
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
1
0
0
0
0
1
P_
writes ‘P’; the DDRAM has been selected at power-up; the
cursor is incremented by 1 and shifted to the right
Product specification
Co
PCF2103 family
10
1
send a control byte for ‘write data’
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DISPLAY
OPERATION
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
0
1
0
0
0
1
writes ‘H’
PH_
12 to 15
|
|
|
|
16
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
17
18
47
19
1
0
1
0
0
1
1
writes ‘S’
1
PHILIPS_
(optional I2C-bus stop) I2C-bus start + slave address
for write (as step 8)
PHILIPS_
control byte
Co
RS
0
0
0
0
0
0
Ack
1
0
0
0
0
0
0
0
1
PHILIPS_
return home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
0
0
0
20
I2C-bus start
21
slave address for read
0
0
1
0
1
PHILIPS
0
1
sets DDRAM address 0 in address counter (also returns shifted
display to original position; DDRAM contents unchanged); this
instruction does not update the Data Register (DR)
PHILIPS
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
1
1
0
1
0
1
1
PHILIPS
during the acknowledge cycle the content of the DR is loaded
into the internal I2C-bus interface to be shifted out; in the
previous instruction neither a ‘set address’ nor a ‘read data’ has
been performed; therefore the content of the DR was unknown;
R/W has to be set to logic 1 while still in I2C-bus write mode
control byte for read
RS
0
0
0
0
0
0
Ack
0
1
1
0
0
0
0
0
1
DDRAM content will be read from following instructions
PHILIPS
Product specification
Co
PCF2103 family
22
Philips Semiconductors
11
INSTRUCTION
LCD controllers/drivers
1998 May 11
STEP
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DISPLAY
‘read data’: 8 × SCL + master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
X
24
X
X
X
X
X
X
X
0
PHILIPS
0
1
0
0
1
0
0
0
0
PHILIPS
8 × SCL; code of letter ‘H’ is read first; during master
acknowledge code of ‘I’ is loaded into the I2C-bus interface
‘read data’: 8 × SCL + no master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
26
8 × SCL; content loaded into interface during previous
acknowledge cycle is shifted out over SDA; MSB is DB7; during
master acknowledge content of DDRAM address 01 is loaded
into the I2C-bus interface
‘read data’: 8 × SCL + master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
25
OPERATION
1
I2C-bus stop
0
0
1
0
0
1
1
PHILIPS
no master acknowledge; after the content of the I2C-bus
interface register is shifted out no internal action is performed;
no new data is loaded to the interface register, Data Register
(DR) is not updated, Address Counter (AC) is not incremented
and cursor is not shifted
Philips Semiconductors
23
INSTRUCTION
LCD controllers/drivers
1998 May 11
STEP
PHILIPS
Notes
48
1. X = don’t care.
2. SDA is left at high-impedance by the microcontroller during the read acknowledge.
Product specification
PCF2103 family
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DESCRIPTION
power-on or unknown state
|
wait 2 ms after VDD rises above VPOR
|
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
0
0
1
1
X
X
X
DB0 BF cannot be checked before this instruction
X
function set (interface is 8 bits long)
|
wait 2 ms
|
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
0
0
1
1
X
X
X
DB4
DB3
DB2
DB1
1
X
X
X
Philips Semiconductors
STEP
LCD controllers/drivers
1998 May 11
Table 16 Initialization by instruction, 8-bit interface (note 1)
DB0 BF cannot be checked before this instruction
X
function set (interface is 8 bits long)
|
wait more than 40 µs
|
49
RS
R/W
DB7
DB6
DB5
0
0
0
0
1
DB0 BF cannot be checked before this instruction
X
|
function set (interface is 8 bits long)
BF can be checked after the following instructions; when BF is not checked,
the waiting time between instructions is the specified instruction time
(see Table 4)
|
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
0
0
1
1
0
M
0
H
0
0
0
0
0
0
1
0
0
0
display off
0
0
0
0
0
0
0
0
0
1
clear display
0
0
0
0
0
0
0
1
I/D
S
entry mode set
Initialization ends
1. X = don’t care.
Product specification
Note
PCF2103 family
|
DB0 function set (interface is 8 bits long); specify the number of display lines
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DESCRIPTION
Power-on or unknown state
|
Wait 2 ms after VDD rises above VPOR
|
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
1
DB6
DB5
DB4
0
1
1
BF cannot be checked before this instruction
function set (interface is 8 bits long)
|
Wait 2 ms
|
RS
R/W
DB7
0
0
0
Philips Semiconductors
STEP
LCD controllers/drivers
1998 May 11
Table 17 Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation
BF cannot be checked before this instruction
function set (interface is 8 bits long)
|
Wait 40 µs
|
50
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
1
|
BF cannot be checked before this instruction
function set (interface is 8 bits long)
BF can be checked after the following instructions; when BF is not checked, the waiting time
between instructions is the specified instruction time (see Table 4)
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
0
0
0
0
0
1
0
function set (interface is 4 bits long)
0
0
0
M
0
H
specify number of display lines
0
0
0
0
0
0
0
0
1
0
0
0
display off
0
0
0
0
0
0
clear display
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
I/D
S
entry mode set
Product specification
Initialization ends
interface is 8 bits long
PCF2103 family
|
function set (set interface to 4 bits long)
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
78 77 76 75 74 73 72 71 70
≈ 3.18
mm
C27(dummy)
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
79
80
C1
81
R8
82
R7
83
R6
84
R5
85
R4
86
R3
87
R2
88
R1
89
R17
90
SCL
91
SDA
92
PCF2103-2
C2
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
ROM xxx
C2(dummy)
C11
C10
C9
C8
C7
C6
C5
C4
C3(dummy)
handbook, full pagewidth
C3
16 BONDING PAD LOCATIONS
x
0
0
y
51
C28(dummy)
50
C28
49
C29
48
C30
47
C31
46
C32
45
C33
44
C34
43
C35
42
C36
41
C37
40
C38
39
C39
38
C40
37
C41
36
C42
35
C43
34
C44
33
C45
32
C46
31
C47
30
C48
29
C49
DB7
96
DB6
97
DB5
98
DB4
99
DB3
100
DB2
101
28
C50
DB1
102
27
C51
DB0
103
26
C52
DB0(dummy)
104
25
C52(dummy)
Fig.29 Bonding pad locations.
1998 May 11
51
C53
C54
C55
C56
C57
C58
C53(dummy)
≈ 2.99 mm
C59
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C60
8
R18
7
R16
6
R15
5
R14
4
R13
3
R12
2
VLCD
1
VDD
OSC
VDD(dummy)
105
R11
95
R9
R/W
R10
94
VSS
RS
T1
93
PD
E
MGL258
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
Table 18 Bonding pad locations (dimensions in µm).
All x/y coordinates are referenced to centre of
chip (see Fig.29)
SYMBOL
PAD
X
SYMBOL
Y
PAD
X
Y
VDD (dummy)
105
−1228
−1414
C40
38
1344
−2
VDD
1
−1048
−1414
C39
39
1344
88
OSC
2
−958
−1414
C38
40
1344
178
PD
3
−868
−1414
C37
41
1344
268
T1
4
−778
−1414
C36
42
1344
358
VSS
5
−688
−1414
C35
43
1344
448
VLCD
6
−516
−1414
C34
44
1344
538
R9
7
−349
−1414
C33
45
1344
628
R10
8
−259
−1414
C32
46
1344
718
R11
9
−169
−1414
C31
47
1344
808
R12
10
−79
−1414
C30
48
1344
898
R13
11
11
−1414
C29
49
1344
1070
R14
12
101
−1414
C28
50
1344
1160
R15
13
191
−1414
C28 (dummy)
51
1344
1250
R16
14
281
−1414
C27 (dummy)
52
1262
1414
R18
15
371
−1414
C27
53
1172
1414
C60
16
461
−1414
C26
54
1082
1414
C59
17
551
−1414
C25
55
992
1414
C58
18
641
−1414
C24
56
902
1414
57
805
1414
C57
19
731
−1414
C23
C56
20
821
−1414
C22
58
715
1414
C55
21
911
−1414
C21
59
625
1414
60
535
1414
C54
22
1001
−1414
C20
C53
23
1091
−1414
C19
61
445
1414
C53 (dummy)
24
1181
−1414
C18
62
355
1414
C52 (dummy)
25
1344
−1254
C17
63
265
1414
C52
26
1344
−1164
C16
64
175
1414
C51
27
1344
−1074
C15
65
85
1414
C50
28
1344
−948
C14
66
−5
1414
C49
29
1344
−812
C13
67
−95
1414
C48
30
1344
−722
C12
68
−185
1414
C47
31
1344
−632
C11
69
−275
1414
C46
32
1344
−542
C10
70
−446
1414
C45
33
1344
−452
C9
71
−536
1414
C44
34
1344
−362
C8
72
−626
1414
73
−716
1414
C43
35
1344
−272
C7
C42
36
1344
−182
C6
74
−806
1414
C41
37
1344
−92
C5
75
−896
1414
1998 May 11
52
Philips Semiconductors
Product specification
LCD controllers/drivers
SYMBOL
PAD
PCF2103 family
X
Table 19 Bump specifications
Y
C4
76
−986
1414
C3
77
−1076
1414
Bump variant
N
−
C3 (dummy)
78
−1166
1414
Type
−
C2 (dummy)
79
−1344
1303
galvanic; pure
aurum
C2
80
−1344
1213
Bump width
60 ±6
µm
90 ±6
µm
PARAMETER
SPECIFICATION
UNIT
C1
81
−1344
1123
Bump length
R8
82
−1344
1033
Bump height
17.5 ±5
µm
R7
83
−1344
943
<2
µm
R6
84
−1344
853
Height difference in one
die
R5
85
−1344
763
Convex deformation
<5
µm
R4
86
−1344
673
Pad size; aluminium
80 × 100
µm
R3
87
−1344
583
R2
88
−1344
493
R1
89
−1344
403
R17
90
−1344
313
SCL
91
−1344
131
SDA
92
−1344
−9
E
93
−1344
−195
RS
94
−1344
−289
RW
95
−1344
−382
DB7
96
−1344
−476
DB6
97
−1344
−572
DB5
98
−1344
−668
DB4
99
−1344
−765
DB3
100
−1344
−861
DB2
101
−1344
−957
DB1
102
−1344
−1054
DB0
103
−1344
−1150
DB0 (dummy)
104
−1344
−1240
Rec. Pat. C1
1335
−1405
Rec. Pat. C2
−1335
1405
Rec. Pat. F
−1340
−1397
1998 May 11
Passivation opening CBB 46 × 76
53
µm
Wafer thickness
380 ±25
µm
Minimum pitch
90
µm
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
17 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 May 11
54
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
NOTES
1998 May 11
55
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For all other countries apply to: Philips Semiconductors,
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/01/pp56
Date of release: 1998 May 11
Document order number:
9397 750 02649