Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) DESCRIPTION PLS153/A FEATURES The PLS153 and PLS153A are two-level logic elements, consisting of 42 AND gates and 10 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 8 inputs (I) and 10 bidirectional I/O lines (B). These yield variable I/O gate configurations via 10 direction control gates (D), ranging from 18 inputs to 10 outputs. On-chip T/C buffers couple either True (I, B) or Complement (I, B) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Their output polarity, in turn, is individually programmable through a set of EX-OR gates for implementing AND/OR or AND/NOR logic functions. The PLS153 and PLS153A are field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment. • Field-Programmable (Ni-Cr links) • 8 inputs • 42 AND gates • 10 OR gates • 10 bidirectional I/O lines • Active-High or -Low outputs • 42 product terms: PIN CONFIGURATIONS N Package – 32 logic terms – 10 control terms • I/O propagation delay: – PLS153: 40ns (max) I0 1 20 VCC I1 2 19 B9 I2 3 18 B8 I3 4 17 B7 I4 5 16 B6 I5 6 15 B5 I6 7 14 B4 I7 8 13 B3 B0 9 12 B2 11 B1 GND 10 – PLS153A: 30ns (max) • Input loading: –100µA (max) • Power dissipation: 650mW (typ) • 3-State outputs • TTL compatible APPLICATIONS • Random logic • Code converters • Fault detectors • Function generators • Address mapping • Multiplexing N = Plastic DIP (300mil-wide) A Package I2 I1 I0 VCC B9 3 2 1 20 19 I3 4 18 B8 I4 5 17 B7 I5 6 16 B6 I6 7 15 B5 I7 8 14 B4 9 10 11 12 13 B0 GND B1 B2 B3 A = Plastic Leaded Chip Carrier SP00274 ORDERING INFORMATION DESCRIPTION ORDER CODE DRAWING NUMBER 20-Pin Plastic Dual In-Line, 300mil-wide PLS153N, PLS153AN 0408B 20-Pin Plastic Leaded Chip Carrier PLS153A, PLS153AA 0400E October 22, 1993 1 853–0311 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLS153/A LOGIC DIAGRAM (LOGIC TERMS–P) I0 1 I1 2 I2 3 I3 4 I4 5 I5 6 I6 7 I7 8 (CONTROL TERMS) B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 S9 X9 X8 X7 X6 X5 X4 X3 X2 X1 31 24 23 16 15 8 7 0 NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. October 22, 1993 X0 S8 S7 S6 S5 S4 S3 S2 S1 S0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 19 B9 18 B8 17 B7 16 B6 15 B5 14 B4 13 B3 12 B2 11 B1 9 B0 SP00276 2 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLS153/A FUNCTIONAL DIAGRAM P31 P0 D0 D9 I0 I7 B0 B9 S9 B9 X9 S0 B0 X0 SP00277 ABSOLUTE MAXIMUM RATINGS1 RATINGS SYMBOL PARAMETER MAX UNIT +7 VDC Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC IIN Input currents +30 mA IOUT Output currents +100 mA Tamb Operating temperature range 0 +75 °C Tstg Storage temperature range –65 +150 °C VCC Supply voltage VIN MIN –30 NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. October 22, 1993 3 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) LOGIC FUNCTION PLS153/A THERMAL RATINGS TYPICAL PRODUCT TERM: Pn = A B C D . . . ⋅ ⋅ ⋅ ⋅ TYPICAL LOGIC FUNCTION: AT OUTPUT POLARITY = H Z = P0 + P1 + P2 . . . AT OUTPUT POLARITY = L Z = P0 + P1 + P2 + . . . Z = P0 P1 P2 . . . ⋅ ⋅ ⋅ NOTES: 1. For each of the 10 outputs, either function Z (Active-High) or Z (Active-Low) is available, but not both. The desired output polarity is programmed via the Ex-OR gates. 2. Z, A, B, C, etc. are user defined connections to fixed inputs (I) and bidirectional pins (B). SP00275 TEMPERATURE Maximum junction 150C Maximum ambient 75C Allowable thermal rise ambient to junction 75C The PLS153/A devices are also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the Philips Semiconductors Military Data Handbook. DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT 0.8 V Input voltage2 VIL Low VCC = MIN VIH High VCC = MAX VIC Clamp3 Output 2.0 VCC = MIN, IIN = –12mA V –0.8 –1.2 V 0.5 V voltage2 VCC = MIN VOL Low4 IOL = 15mA VOH High5 IOH = –2mA Input 2.4 V current9 VCC = MAX IIL Low VIN = 0.45V –100 µA IIH High VIN = 5.5V 40 µA VOUT = 5.5V 80 µA VOUT = 0.45V –140 Output current VCC = MAX IO(OFF) IOS ICC Hi-Z state8 Short circuit3, 5, 6 VCC supply current7 VOUT = 0V VCC = MAX –15 130 –70 mA 155 mA Capacitance VCC = 5V CIN Input VIN = 2.0V 8 pF CB I/O VB = 2.0V 15 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with +10V applied to I7. 5. Measured with +10V applied to I0–7. Output sink current is supplied through a resistor to VCC. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with I0, I1 at 0V, I2 – I7 and B0–9 at 4.5V. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I7). October 22, 1993 4 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLS153/A AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 = 300Ω, R2 = 390Ω LIMITS SYMBOL PARAMETER FROM TO TEST PLS153 PLS153A CONDITION TYP1 MAX TYP1 MAX MIN MIN UNIT tPD Propagation delay Input ± Output ± CL = 30pF 30 40 20 30 ns tOE Output enable2 Input ± Output – CL = 30pF 25 35 20 30 ns tOD Output disable2 Input ± Output + CL = 5pF 25 35 20 30 ns NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORMS TIMING DEFINITIONS SYMBOL +3.0V 90% PARAMETER tPD Propagation delay between input and output. tOD Delay between input change and when output is off (Hi-Z or High). tOE Delay between input change and when output reflects specified output level. 10% 0V 5ns tF tR 5ns +3.0V 90% 10% 0V 5ns 5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses SP00017 TEST LOAD CIRCUIT VCC C1 +5V S1 C2 R1 BY I0 INPUTS I7 BW BX R2 DUT GND BZ OUTPUTS NOTE: C1 and C2 are to bypass VCC to GND. October 22, 1993 CL SP00278 5 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLS153/A TIMING DIAGRAM +3V I, B 1.5V 1.5V 1.5V 0V VOH B 1.5V 1.5V VT VOL tPD tOD LOGIC PROGRAMMING The PLS153/A is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP, Data I/O’s ABEL and Logical Devices, Inc. CUPL design software packages. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. tOE SP00279 PLS153/A logic designs can also be generated using the program table entry format detailed on the following page. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package. PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/ Software Support) of this data handbook for additional information To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. OUTPUT POLARITY – (B) S S B B X X ACTIVE LEVEL ACTIVE LEVEL CODE HIGH1 (NON–INVERTING) LOW H (INVERTING) CODE L SP00280 AND ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B P, D I, B I, B I, B P, D I, B P, D P, D STATE CODE STATE CODE STATE CODE STATE CODE INACTIVE1, 2 O I, B H I, B L DON’T CARE – SP00281 ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 6 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLS153/A OR ARRAY – (B) P P S S Pn STATUS CODE Pn STATUS ACTIVE1 A INACTIVE CODE • SP00282 NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Pn will be unconditionally inhibited if both the True and Complement of an input (either I or B) are left intact. VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. October 22, 1993 CAUTION: PLS153A TEST COLUMNS The PLS153A incorporates two columns not shown in the logic block diagram. These columns are used for in-house testing of the device in the unprogrammed state. These columns must be disabled prior to using the PLS153A in your application. If you are using a Philips Semiconductors-approved programmer, the disabling is accomplished during the device programming sequence. If these columns are not disabled, abnormal operation is possible. Furthermore, because of these test columns, the PLS153A cannot be programmed using the programmer algorithm for the PLS153. 7 October 22, 1993 H L — I, B I, B DON’T CARE VARIABLE NAME 0 INACTIVE AND I, B(I) LOW HIGH L H B(0) (POL) A CONTROL INACTIVE ACTIVE OR Unused I and B bits in the AND array should be programmed as Don’t Care (–). Unused product terms in the OR array should be programmed as INACTIVE (o). Output polarity is non–inverting. All AND gates are pulled to a logic “0” (Low). NOTES In the unprogrammed state: CF(XXXX) PROGRAM TABLE # REV TOTAL NUMBER OF PARTS DATE CUSTOMER SYMBOLIZED PART # PHILIPS DEVICE # PURCHASE ORDER # CUSTOMER NAME Philips Semiconductors Programmable Logic Devices T E R M PIN Product specification Programmable logic arrays (18 × 42 × 10) PLS153/A PROGRAM TABLE POLARITY I AND B(I) 0 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 D9 31 D8 D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 9 8 8 7 6 5 B(0) OR 4 3 2 1 19 18 17 16 15 14 13 12 11 0 9 9 1 0 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 3 2 SP00283 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLS153/A SNAP RESOURCE SUMMARY DESIGNATIONS P31 P0 D0 D9 DIN153 I0 NIN153 I7 DIN153 B0 NIN153 B9 AND CAND TOUT153 S9 B9 X9 OR S0 B0 X0 EXOR153 SP00284 October 22, 1993 9