INTEGRATED CIRCUITS SA1620 Low voltage GSM front-end transceiver Product specification Supersedes data of 1996 Oct 08 IC17 Data Handbook 1997 May 22 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 • Feedthrough attenuation LNA1 to Rx mixer ≥ 35dB • Tx power adjustable from -3 to +12dBm by external resistor • Direct supply: 2.7V to 5.5V • Battery supply voltage VBATT = 3.3V to 7.5V or direct supply • Two DC regulators programmable for 3.0V, 3.4V, 3.7V or 5.1V • Low current consumption: 28mA for Rx or 59mA for Tx • Fully compatible with SA1638 GSM IF Digital I/Q circuit DESCRIPTION The SA1620 is a combined receive (Rx) and transmit (Tx) front-end for GSM cellular telephones. The receive path contains two low noise amplifiers (LNA1 and LNA2) with four switchable attenuation steps. A Gilbert Cell mixer in the receive path down-converts the RF signal to a first IF of 70 to 500 MHz. A second Gilbert Cell in the transmit path transposes a GMSK or phase modulated IF to RF by image reject mixing and has a fixed IF of 400 MHz. A buffered LO signal is fed to Rx and Tx mixers. Rx or Tx path or the entire circuit may be powered-down. FEATURES • Excellent noise figure: <2dB for the LNAs at 950MHz • LNAs matched to 50Ω with external matching components • LNAs with gain control, 59dB dynamic range in four discrete steps • LNA gain stability ±0.5dB within -40 to 85°C APPLICATIONS • 900MHz front end for GSM hand-held units • Portable radio, TDMA systems PIN CONFIGURATION 48 47 46 45 44 43 42 PONBUF PDTx GNDTx4 PON 3 34 GNDREG1 4 33 VREG1 5 32 VREGF2 31 VREG2 30 GNDREG2 29 CON1 28 LO INX 27 LO IN 26 CON2 25 GNDTx2 IN2 2 GNDL2 GNDL2A B 6 A 7 48–PIN LQFP 8 INMX 9 COMP2 10 COMP1 11 VCCBM Tx0X VBATT 35 1 INM 41 40 39 38 37 36 VCCL2 OUT2 TxO GNDTx3 RETx IN1 GNDL1 GNDL1A OUT1 VccL1 LQFP Package 12 VccTx2 GNDTx1 VccTx1 GND3 TxIFX TxIF GND2 RxIFX RxIF GND1 PONRx GNDBM 13 14 15 16 17 18 19 20 21 22 23 24 SR00127 Figure 1. Pin Configuration ORDERING INFORMATION DESCRIPTION 48-Pin Thin Quad Flat Pack (TQFP) TEMPERATURE RANGE ORDER CODE DWG # -40 to +85°C SA1620BE SOT313-2 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER RATING UNITS VCCXX Supply voltages 2.7 to 5.5 V VBATT Battery voltage 3.3 to 7.5 V Operating ambient temperature range -40 to +85 °C TA 1997 May 22 2 853-1784 18066 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 CON2 CON1 V BATT PON GND3 GND2 GND1 GNDTx4 GNDTx3 GNDTx2 GNDTx1 GNDBM COMP2 V CC BM COMP1 BLOCK DIAGRAM PDTx PONRx BANDGAP BIAS SUPPLIES PONBUF VREG2 VREG2F2 GNDREG2 GNDREG1 VREG1 VOLTAGE REGULATORS VCCTx1 VCCTx2 TxO TxIF SINGLE SIDEBAND MIXER TxOX LINEAR IF LEVEL CONTROL TxIFX RETx TLO LO IN LO INPUT BUFFER BUFFER A LO INX TLOX ATTENUATION CONTROL LOGIC RLO BUFFER VCCL1 RLOX B VCCL2 RxIF IN1 LNA2 INMX INM OUT2 GNDL2A RxIFX GNDL2 IN2 OUT1 GNDL1A GNDL1 LNA1 SR00129 Figure 2. Block Diagram 1997 May 22 3 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 PIN DESCRIPTIONS Pin No. Pin Name Description Pin No. DC Regulators Pin Name Description 13 GNDBM Ground for Rx Bias and Rx mixer 15 GND1 Ground of regulator supply 14 PONRx Power on input for Rx bias supply 18 GND2 Ground of regulator supply 16 RxIF IF output, open collector 21 GND3 Ground of regulator supply 17 RxIFX Inverse IF output, open collector 26 CON2 Control 2, voltage select for regulator 1 and 2 44 IN1 Input to LNA1 45 GNDL1 Ground L1 for LNA1 29 CON1 Control 1, voltage select for regulator 1 and 2 46 GNDL1A Ground L1A for LNA1 30 GNDREG2 Ground of regulator 2 47 OUT1 Output LNA1 48 VCCL1 Positive supply for LNA1 31 VREG2 Output of regulator 2 32 VREG2F2 Feedback of regulator 2 33 VREG1 Output of regulator 1 19 TxIF IF input for Tx 34 GNDREG1 Ground of regulator 1 20 TxIFX Inverse IF input for Tx VCCTx1 Positive supply for Tx input Tx Path 35 PON Power-on input of regulators 22 36 VBATT Input of regulator 1 and 2 23 GNDTx1 Ground for Tx input 24 VCCTx2 Positive supply for LO and Tx input Rx Path 1 VCCL2 Positive supply for LNA2 25 GNDTx2 Ground for LO and Tx input 2 IN2 Input LNA2 38 PDTx Power down Tx input GNDTx4 Ground for Tx output 3 GNDL2 Ground L2 for LNA2 39 4 GNDL2A Ground L2A for LNA2 40 TxOX Inverse Tx output, open collector TxO Tx output, open collector 5 OUT2 Output LNA2 41 6 B Attenuation select B for LNA1 and LNA2 42 GNDTx3 Ground 1 for Tx output side 43 RETx Reference resistor for Tx output current 7 A Attenuation select A for LNA1 and LNA2 8 INM RF input for Rx mixer, open emitter 9 INMX Inverse RF input for Rx mixer, open emitter 27 LO IN Input for Local Oscillator signal 28 LO INX Inverse input for LO or AC ground 10 COMP2 Capacitor for bias stabilization 37 PONBUF 11 COMP1 Capacitor for bias stabilization Power on first stage LO input buffer and bias 12 VCCBM VCC for Rx Bias and Rx mixer Elements for Tx and Rx Path NOTES: 1. Device is ESD sensitive. There are no ESD protection diodes at Pins 16, 17, 40 and 41. Thus, open-collector outputs may have increased DC voltage or higher AC peak voltage. 2. Pins 15, 18 and 21 are connected to each other and to a separate ground in REG1 and REG2. 3. Pins 23, 25, 42 and 39 are connected to each other and to the Tx path, LO buffer and associated bias supplies. 4. Pins 22 and 24 are connected to each other providing a sense input. They are also connected to the Tx path, LO buffer and associated bias supplies. 5. Pins 30 and 34 are not internally connected. They must be connected to external grounds. 6. Pins 48, 1, and 12 are not internally connected and have no ESD protection diodes between them. Power may be saved by connecting VCCL1 and IN1 or VCCL2 and IN2 to ground if LNA1 or LNA2 is not needed. 1997 May 22 4 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNITS VCCXX Supply voltages -0.3 to +6.0 V VBATT Battery voltage -0.3 to +8.0 V -0.3 to (VCCXX+0.3) V -0.3 to +1 V 0 V VIN Voltage applied to any other pin ∆V VCCTx1,2 pins to VCCBM ∆VG PD Any GND pin to any other GND pin Power dissipation, TA = 25°C (still air) 800 mW TJMAX Maximum operating junction temperature 150 °C PMAX Maximum power input/output TSTG Storage temperature range +20 dBm –65 to +150 °C VTXO, VTXOX Positive RF peak voltage at Tx outputs 6 V VRXIF, VRXIFX Positive IF peak voltage at Rx mixer outputs 6 V NOTE: 1. Maximum junction temperature is determined by the power dissipation is determined by the operating ambient temperature and the thermal resistance, θJA. 48-pin TQFP: θJA = 67°C/W. DC REGULATORS Table 1. DC Reg Output Voltage Control Pins Two low drop regulators (REG1 and REG2) are included on the chip and may be used to deliver the supply voltage of the main circuitry (e.g., 3V) out of the battery (at VBATT = 3.3 to 7.5V) as shown in Figure 4 and in Table 1. CON1 REG1 is intended to supply, at least, the internal functions of the SA1620. Both regulators may also be used for external circuitry. For this application, different voltages may be programmed as shown in Table 1. VREG1 VREG2 UNITS L L 3 ± 5% 3 ± 5% V L H 3.4 ± 5% 3.4 ± 5% V H L 3.7 ± 5% 3.7 ± 5% V H H 5.1 ± 5% 5.1 ± 10% V NOTES: 1. Logic levels at CON1 and CON2: H – Open circuit. Pin must not be connected externally. Logic high level supplied on chip. L – Connected to ground. 2. Currents at CON1 and CON2: H – 0µA L (PON = H) – 50µA L (PON = L) – <1µA The transmitter supply pins (VCCTx1,2) also operate as a sensor connection in the feedback loop of REG1 and must be externally connected to pin VREG1. For REG2, the sensor pin VREGF2 must be connected to VREG2. All ground pins are internally bonded to the header except for pins GNDL1, GNDREG1 and GNDREG2. When both regulators are not used, connect pins VBATT, PON, CON1, CON2, VREG1, VREG2 and VREG2F2 to ground. 1997 May 22 CON2 5 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 Table 2. DC Regulators SYMBOL VBATT VREG1, VREG2 PARAMETER TEST CONDITIONS Common positive input voltage at both regulators Output voltages of regulators 1 and 2 LIMITS MIN TYP MAX VREG1+0.3 VBATT = 3.3V 2.85 UNITS V 3 3.15 V IINT1 Internal current of REG1 in power-on mode 4 + IVREG1/10 mA IINT2 Internal current of REG2 in power-on mode 2.5 + IVREG2/10 mA µA IINT01, IINT02 Internal current in power-down mode IVREG1MAX5 Max output current at VREG1 100 mA IVREG2MAX5 Max output current at VREG2 30 mA BW6 <15 VBATT = 3.3V, IREG1 = 0.1mA 0.03 VBATT = 3.3V, IREG1 = 100mA 60 VBATT = 7.5V, IREG1 = 100mA 7 FREG G f kHz 80 ≤100kHz ≤–61 10MHz ≤–32 100MHz ≤–37 400MHz ≤–48 dB NOTES: 1. Power-on pin of Regulator 1 and 2: PON 2. Input currents at PON: <1µA. There are no pull-up or pull-down resistors. 3. Feedthrough attenuation from the logic input PON to the outputs VREG1 and VREG2: ≥40dB. 4. Recommended load capacitors: C529 = C530 = 1µF to ground with series resistance ≤0.1Ω. See Figure 4. Additional optional capacitor ≤1000µF with series resistance ≤5Ω. 5. At Tj ≥ 150°C a thermal switch reduces the output current. 6. Typical open loop bandwidths of regulator 1 at VREG1 = 3V and C529 = 1µF. 7. Feedthrough attenuation (at the indicated frequency f) from the input VBATT to the outputs VREG1 and VREG2 at VBATT = 3.3V, (CON1=CON2=L) 1997 May 22 6 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 DC ELECTRICAL CHARACTERISTICS VCCxxx = +3V, TA = 25°C; unless otherwise stated. LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX 59 90 UNITS Transmitter IVCC Transmit mode R546 = 240Ω Total supply current R1 External resistor1 VR1 Internal supply at pin RETx IR1 Current at pin RETx Ω 240 VCCTx1,2 = 2.7V 0.43 VCCTx1,2 = 5.5V 0.45 R546 = 240Ω, VCCTx1,2 = 2.7V 1.7 R546 = 240Ω, VCCTx1,2 = 5.5V 1.8 mA V mA Low noise amplifiers IVCCL1 Current at pin VCCL1 G1hi mode 2.5 3.5 5 mA IVCCL2 Current at pin VCCL2 G2hi mode 2.5 3.5 5 mA 28 39 mA 2.85 3.0 3.15 V Receiver IVCC Receive mode R546 = 240Ω Total supply current Regulators Vreg1 Voltage @ 100mA load Con1 Con2 L L L H 3.23 3.4 3.57 V H L 3.515 3.7 3.885 V H 4.61 5.1 5.61 V H Vreg2 Logic Voltage @ 30mA load Con1 Con2 L L 2.85 3.0 3.15 V L H 3.23 3.4 3.57 V H L 3.515 3.7 3.885 V H H 4.61 5.1 5.61 V levels2 VIH Logic 1 level PONBUF, PDTx, PONRx, A, B 2.0 VCCBM3 V VIH Logic 1 level PON 2.0 VBATT V VIL Logic 0 level 0 0.8 V 1 µA II CIa Input logic current Input logic capacitance 1.7 NOTES: 1. The output current ITXO + ITXOX is adjustable by the external resistor R546. ITXO + ITXOX = 10 * IR546, IR546 = VR1/R546, 2. Thresholds are independent of supply voltages. Thus the SA1620 is compatible with SA1638 and with the power down inputs of usual external voltage regulators. 3. PON logic 1 max is VBATT. 1997 May 22 7 pF Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 AC ELECTRICAL CHARACTERISTICS VCCXX = +3V, TA = 25°C; RF = 940MHZ; IF=400MHz, fLO=RF + IF; LO = –15dBm; unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS LIMITS1 MIN1 -3σ TYP 3σ 9.4 10 10.6 MAX1 UNITS Low Noise Amplifier LNA12 G1hi mode S21 G1hi mode, RF = 1800MHz Gain G1lo mode IP3 –2.5 –13 –12 G1lo mode 28 G1hi mode 0.003 G1lo mode 0.0140 –11 dB ∆S21/∆T Gain temperature sensitivity ∆S21/ ∆VCCL1 Gain/voltage sensitivity 0.1 dB/V ∆S21/∆f Gain frequency variation 0.01 dB/MHz G1hi mode –19 dB 50Ω –11 dB S12 Reverse isolation S11 Input match3 S22 P-1dB Output match3 Input 1dB gain compression IIP3 Input third order intercept IIP3/∆t Input third order intercept 50Ω dB/°C –14 G1hi mode –15.5 –5.5 dB –14 –12.5 –4 –2.5 dBm dBm 0.011 dB/°C NF Noise figure 1.9 dB tON Turn-on time 7 µs tOFF Turn-off time 0.5 µs Low Noise Amplifier LNA22 G2hi mode 9 G2hi mode, RF = 1800MHz Gain S21 IP3 ∆S21/∆T Gain temperature sensitivity ∆S21/ ∆VCCL2 Gain/voltage sensitivity ∆S21/∆f Gain frequency variation 10 11 –1.5 dB G2lo1 mode –8.5 –7.5 –6.5 G2lo2 mode –22.5 –21.5 –20.5 G2lo3 mode –30 –28.5 –27 G2lo1 mode 18 G2lo2 mode 20 G2lo3 mode 25 G2hi mode 0.003 G2lo1,2,3 modes 0.014 dB dB dB/°C 0.1 dB/V 0.01 dB/MHz S12 Reverse isolation G2hi mode –24 dB S11 Input match3 50Ω –13 dB S22 Output match3 50Ω –15 dB P-1dB Input 1dB gain compression IIP3 Input third order intercept IIP3/∆t Input third order intercept –18 –16 –14 dBm –8 –6 –4 dBm 0.019 dB/°C 2 dB Turn-on time 7 µs Turn-off time 0.5 µs NF Noise figure tON tOFF 1997 May 22 G2hi mode 8 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 AC ELECTRICAL CHARACTERISTICS (continued) SYMBOL PARAMETER TEST CONDITIONS LIMITS1 MIN1 -3σ TYP 3σ 7.5 +8.5 9.5 MAX1 UNITS Rx Mixer PGC Power conversion gain5 S11 Mixer input match at ports INM and INMX4 NFM SSB combined noise figure P-1dB Input 1dB compression IIP3 Input third order intercept IIP3/∆t Input third order intercept IIP2 RF = 1800MHz dB –4 –13 0 Input second order intercept dB 10 dB –7.3 dBm 2 4 dBm 0.005 dB/°C 19 dBm GRFM-IF RF feedthrough 400MHz –26 dB GLOfloor LO floor feedthrough 400MHz –30 dB GLO-IF LO feedthrough to IF 1.3GHz –16 dB GLO-RFM LO to mixer input feedthrough 1.3GHz –50 dBm GLO-RF1 LO to RF LNA1 input feedthrough 1.3GHz –65 dBm GLNA1-2 LNA1 output to LNA2 input feedthrough 400MHz 1290-1760MHz –41 –26 dB GLNA2-M LNA2 output to mixer input feedthrough 1290-1760MHz –23 dB GLNA1-M LNA1 output to mixer input feedthrough 400MHz 1290-1760MHz –50 –35 dB Cascaded gain A,B Logic Level Receiver 6 Input IP3 @ RFin=–40dBm H,H 23.5 26.5 28.5 30.5 33.5 dB H,L 6 9 11 13 16 dB L,H –8 –5 –3 –1 +2 dB L,L –41 –36 –32 +28 –23 –20 –18 –16 H,H dB dBm LO input ZIN Input impedance (each single-ended input) PIN Input power ASAT 1.3GHz –257 Transistor saturation limit, max input amplitude 35-j97 Ω –15 dBm 500 mV Tx IF input |ZIN| Input impedance PIN Input power 400MHz 2 kΩ –20 dBm Tx RF output POUT R546 = 240Ω, VCCTx1,2 = 3V 5 7.5 8.5 9.5 dBm NOTES: 1. Due to our automatic test equipment accuracy and repeatability test limits may not reflect the ultimate device performance. Standard deviations are calculated from characterization data. 2. If the LNA1 is not needed, connect pin VCCL1 and IN1 to GND. If the LNA2 is not needed, connect pin VCCL2 and IN2 to GND. 3. Simple L/C elements are needed to achieve specified return loss. 4. The mixer RF inputs (emitters of a Gilbert Cell) may be driven by a symmetrical matching network. 5. Input symmetry suppression is such that the product 6*RF–4*LO is to be suppressed by at least 66dB relative to the wanted IF output when the input to the mixer is at –32dBm. 6. LNA1, LNA2, and the mixer are cascaded. 0 db insertion loss between LNA1 out to LNA2 in and LNA2 out to mixer in. 7. Lowering the LO input power (PIN) from TYP to MIN will lower the mixer gain (PGC) by 1 dB. 1997 May 22 9 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 Table 3. Power-Down and Tx/Rx Control Logic No. PONBUF PDTX PONRX MODE RESULT 1 H H L Standby LO buffer active, Tx and Rx path inactive 2 H L L Transmit LO buffer active, Tx path active, Rx path inactive (LNAs + mixer) 3 H H H Receive Tx path inactive, LO buffer and Rx path active (LNAs + mixer) 4 H L H Calibrate Tx path and Rx LNAs inactive, LO buffer and Rx mixer active 5 L x x Power-Down Tx- and Rx-path, LO buffers and Bias inactive NOTES: 1. Logic levels of PONBUF, PDTx and PONRx: TTL, see DC Electrical Characteristics. 2. Logic levels / polarities are compatible with Philips Semiconductors Power Amp Controller PCA5075 and synthesizers UMA1019 or SA8025. 3. First stage of LO buffer and parts of bias supply are powered on by PONBUF. 4. Tx- or Rx-paths may be activated for special timeslots. Lines 1 and 4 show options to support DC offset calibrations at baseband mixers, following in the receiver chain (SA1638). Table 4. Gain Control Logic for LNA1 and LNA2 INPUT GAIN POWER CONSUMPTION a b ATTENUATION STEP LNA1 LNA2 LNA1 LNA2 H H 0 G1hi G2hi on on H L 1 G1hi G2lo1 on off L H 2 G1hi G2lo2 on off L L 3 G1lo G2lo3 off off NOTES: 1. Logic levels of a and b: TTL 2. For values of G1hi and G1lo, G2hi, G2lo1, G2lo2 and G2lo3 see LNA1 and LNA2 AC Electrical Characteristics. 1997 May 22 10 1997 May 22 Rx: 890–915MHz Tx: 935–960MHz PA B A PCA5075 SERIAL POWER AMP INPUT CONTROLLER SSB MIXER LNA1 PD Figure 3. 11 PD LNA2 ATTENUATION CONTROL LOGIC POWER SUPPLY Tx/Rx SA1620 INTERFACE TO MICROCONTROLLER BUFFER LINEAR IF LEVEL CONTROL (SA8025, UMA1019) FREQUENCY SYNTHESIZER SAW 400MHz LO1 (1290–1360MHz) 400MHz LO2 800MHz CLKIN 13MHz ÷ ÷ INTERFACE TO MICROCONTROLLER ÷ SA1638 BOUT (to SA1620 ATTENUATION CONTROL LOGIC INPUTS) AOUT Q Q I I Q Q I I Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 SR00130 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 Overview of Dual GSM/PCN Architecture Receive Path The SA1620 RF front-end and SA1638 IF transceivers form a dual conversion architecture which uses a common IF and standard I/Q baseband interface for both transmit and receive paths. This approach avoids the screening difficulties of direct modulation in the transmit direction and the mass production and practical performance issues related to direct conversion in the receive direction. The time division multiplex nature of the GSM system permits integration of the transmit and receive functions together on the one RF and one IF chips. This simplifies the distribution of local oscillator signals, maximizes circuitry commonality, and reduces power consumption. Multiple LNAs allow the flexibility to exploit the best choice of currently available filters (on performance, size, or cost grounds). This approach is preferable to a single high-gain stage as the stray cross-coupling effects between pins remain manageable. In a single stage amplifier this would limit the amount of rejection of out-of-band signals that could be achieved, and would also limit the amount of AGC attenuation that could be practically implemented. The LNAs are powered up only when PONBUF, PDTx and PONRx are high, to allow a high degree of battery economy. If greater sensitivity is required for an application, an external preamplifier circuit can be used instead of LNA1, and LNA1 left unconnected. The SA1620 and SA1638 allow considerable flexibility to optimize the transceiver design for particular price/size/performance requirements, through choice of appropriate RF and IF filters. The receive IF may be chosen freely in the range 70–500MHz, while the transmit IF is fixed to 400 MHz. The comparison frequency of the SA1638 PLL is high in order to provide fast switching time. A special mode is provided with just the IF output related circuitry active in order to allow calibration of the DC offset at the SA1638 baseband receive outputs. This offset contains a contribution due to coupling effects between the second local oscillator and the IF circuitry, and therefore the receiver is set up in the receive state (but with incoming signals excluded) to allow accurate offset calibration. With suitable choice of the IF, an identical SA1638 IF receiver design can be used for both 900MHz GSM and 1800MHz PCN (DCS1800) equipment. Gain Control Gain control is implemented in the SA1620 RF front-end. This avoids the disruption of the DC offset at the baseband IQ outputs that is typically caused by changes in the AGC. The SA1620 and SA1638 are designed so that the GSM dynamic range requirements can be met with the AGC remaining on the maximum gain setting. General Benefits/Advantages • 2.7V operation. Compatible with 3V digital technology and portable applications. (Higher voltage operation also possible, if desired.) These gain steps scale the dynamic range of the received signal (e.g., 90dB for GSM) into the dynamic range of the baseband processing device. • Excellent dynamic range. The availability of two LNAs allows flexibility in receiver dynamic design for portable and mobile GSM spec. applications with appropriate filters. If for a particular application a GaAs or discrete front-end is desired, one of the LNAs can be left unpowered. The placing of the AGC gains switches at the front means that for most of the time some attenuation will be inserted, further increasing typical dynamic performance beyond that specified by GSM. The absolute gain tolerances may be measured together with the attenuation tolerances of external filters during production of the receiver equipment. After software calibration switching from one dynamic range to another will cause only minor errors. Tx Path • High power transmit output driver, delivering +8.5dBm output. TXIF and TXIFX are differential IF inputs for phase modulated signals (e.g., GMSK). There is an IF level control loop which provides a constant amplitude to an image reject up mixer. Thus, this mixer operates linearly in the IF path, independent of IF level tolerances. This is sufficient to drive a filter and power amplifier input, without a driver amplifier. To avoid unnecessary current consumption the output power can be reduced, if not required, by appropriate choice of an external resistor. • DC offsets generated in the receive channel are independent of The single sideband up mixer is sufficient in quadrature to achieve the typical performance indicated in Table 6 over an IF range of 250 to 500MHz. The mixer is operating in switching mode by well matched 0° and 90° LO signals, optimized for 1.1 to 1.5GHz. the AGC setting, and correctable by software to prevent erosion of signal handling dynamic range by DC offsets. Independence of DC from AGC setting is achieved by putting the gain switches in the RF front-end. The Tx output stage operates in switching mode. Thus, parasitic AM at the IF is not transferred. The outputs TXO and TXOX may be used symmetrically or single-ended. Some spurious emissions will be very low when a symmetrical output signal is used. • Minimal high-quality filter requirements. As a result of the integration in the SA1638 of high quality channel selectivity filters, only sufficient filtering is needed in the receive path to provide blocking protection for the second mixers. This reduces receiver cost and size. POUT = R e 6.25V (Z Pin 40 Z Pin 41) (I R546) 2 • Operation at a high IF allows RF image reject filters to be relaxed. V R546 according to DC Electrical R 546 Characteristics. POUT is adjustable with R546 and is accurate to within ±1dB over the full voltage range 2.7 to 5.5V, and ±0.5dB from a given supply voltage. The absolute limit of the negative peak voltage swing at pins TxO and TxOX is VSAT = VCCTx1,2 – 1V. The absolute limit of the positive peak voltage is +6V. according to Figure 4 and I R546 For example, at a 400MHz IF, the natural gain roll-off in the LNAs and mixer suppresses the image signal in the 1800MHz band by typically 28dB below the desired 900MHz band signal. 1997 May 22 12 R641 r=100 C644 c=33p RMXR_In LNA2_Out LNA2_In c=33p C336 C643 c=33p C535 c=100n 650 890 c=3.3p C619 c=33p C626 340 340 Vcc/Gnd Vcc/Gnd c=10n C380 c=10n C645 RMXR+Out C631 c=4.7p o L648 I=56n C339 c=1n C534 c=33p VCCBM COMP2 COMP1 INMX INM A B OUT2 GNDL2A GNDL2 IN2 VCCL2 r=240 R546 605 C628 c=100n o I=56n L612 C613 c=33p Vcc/Gnd 10 mils wide, xxx mils long on 31 mils thick FR4 substrate. o L624 o L627 I=56n I=22n C623 c=10p o C618 c=8.2p 8/12/96 SA 1620 C622 c=10p xxx C650 c=33p GNDL1A C609 c=3.9p RxIF 350 C533 c=33p C573 c:1p RxIFX 350 180 r=100 R651 GNDL1 GND2 C574 c=33p RETx C575 c=33p GNDTx3 TxIF 350 OUT1 PONRx 940 IN1 C610 c=3.9p C620 c=3.3p L617 I=22n C615 c=10p GDN3 VccL1 GNDBM GNDTx4 VccTx1 LNA1_Out Vcc/Gnd 335 TxOX 690 335 TxO TxIFX 13 GND1 PDTx TMXR_Out PON VBATT Vcc/Gnd GNDTx2 CON2 LOIN LOINX CON1 GNDREG2 VREG2 VREGF2 VREG1 GNDREG1 C539 c=33p GNDTx1 PONBUF 1997 May 22 350 Figure 4. Application Circuit VccTx2 LNA_In gnd C527 c=100n Open/Gnd C565 c=33p Open/Gnd Vbatt C564 C=33p C530 c=1u (ceramic!!!) LO_In VRegF2 Vcc C528 c=100n c=10u C636 C635 c–100n TMXR_In C=1u C529 (ceramic!!!) Vbatt/Gnd –+ V503 vdc=7.5 C611 c=33p Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 SR01332 420 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 recommended to be the receiver band plus 400MHz. Additionally, the LO leakage at the input of LNA1 is extremely low, which can greatly alleviate the LO re–radiation problem. APPLICATION CIRCUIT LNA Impedance Match: Intrinsic return losses at the input and output ports are 7dB and 11dB, respectively. However, since long and narrow traces are always needed to fan out the pins, the user can adjust the traces’ dimensions so that only one shunt capacitor at the input is required to achieve excellent impedance match for both ports. If the user wants to skip the input matching network for simplicity, then roughly 0.7dB gain would be lost, although it benefits the system IP3. Outband Blocking: For optimum performance, passive R/C network is added at each input of the mixer. The resistors degenerate the noise conversion gain, while the capacitors preserve the gain and noise figure at RF frequencies. Noise Figure and IP3: The resonant balun is superior to the conventional balun in terms of insertion loss, size and cost. As a result, the user can expect excellent SSB noise figure and gain which is 10dB and 8.5dB, respectively, at 400MHz IF. And the associated input IP3 is 2dBm typically. In the meantime, due to the internal LO buffer, the noise figure and IP3 are not sensitive to the LO levels. As discussed in the LNA Impedance Match session, a better system IP3 can be achieved (if necessary) through LNAs’ gain reduction. Noise Match: The LNA1 and LNA2 can achieve 1.9dB and 2.0dB noise figure, respectively, when S11 = –11dB. Further improvement in S11 will slightly decrease NF and increase S21. Gain Control: The LNA1 can be switched to the attenuation mode, while LNA2 has three attenuation modes to choose from. When gain and loss modes from two LNAs are combined, there will be a total dynamic range of 59dB in the RF block; 3.0V operation is preferred to achieve better IP3 for both LNA1 and LNA2. Transmitter The resonant balun is applied again to maximize the gain and output power, for a given bias current. Typical output power is 8.5dBm when the input level exceeds –25dBm. Temperature Compensation: Both LNAs have a built–in temperature compensation scheme to reduce the gain drift rate to 0.003dB/°C from –40°C to +85°C. LO Input Supply Voltage Compensation: Unique circuitry provides gain stabilization over wide supply voltage range. The gain changes no more than 0.5dB when VCC increases from 2.7V to 5.5V. The LO input is used in Tx- and in Rx-mode. Mixer The LO input buffer should only be set in power-down mode together with the PLL. As further buffering is included on chip there will be no influence on the PLL in active mode when the SA1620 Rxor Tx-path is power On or Off. Current consumption can thus be saved by powering on the Rx- and Tx-circuitry just before it is required, without disruption of the LO circuitry. LO input pins LO IN and LO INX may be used single-ended or symmetrically. Only one synthesizer PLL is necessary to supply the LO input with different frequencies in Tx and Rx timeslots. Mixer Input Match: The mixer is configured for best gain, noise figure and spurious response. The user must supply an external, patented resonant balun to provide the differential drive as well as the impedance match (embedded in). Because the mixer consists of two single–balance mixers, whose inputs are connected in parallel instead of in series, the differential and common–mode impedances are equal. Table 5. GSM/DSC1800 Frequency Specification Output Match: The mixer output circuit also features an external, patented resonant balun to optimize the conversion gain and noise figure. The principal IF operating frequency is 400 MHz. (GSM 05.05, Version 4.2.0, April 1992) Mobile Stations Frequency Bands LO Drive: The internal buffer only requires –15dBm from an external source. Furthermore, the transmitter incorporates an integrated SSB upconverter that consists of narrowband phase shifters at 1300MHz (LO side) and 400MHz (IF side), so the LO frequency is 1997 May 22 14 GSM EGSM DCS1800 Unit Tx 890 to 915 880.2 to 915 1710 to 1785 MHz Rx 935 to 960 925.2 to 960 1805 to 1880 MHz Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 Table 6. Measured Tx Output Frequency and Tx Mixer Products IF=400MHz, symmetrical load at pins TxO, TxOX. SPECTRAL LINE f=n*IF+m*LO MHz No. LO = 1280MHz LO = 1300MHz 1 80 2 160 3 4 RELATIVE POWER OF SPECTRAL LINE Order REMARKS LO = 1315MHz n m 100 115 –3 1 –70 200 230 –6 2 –76 320 300 285 4 –1 –60 400 400 400 1 0 –46 5 480 500 515 –2 1 –31 6 560 600 630 –5 2 –62 7 720 700 685 5 –1 –56 8 800 800 800 2 0 –37 Note 2 9 880 900 915 –1 1 0 Note 1 10 960 1000 1030 –4 2 –46 Note 3 11 1020 1100 1185 6 –1 –63 12 1200 1200 1200 3 0 –60 13 1280 1300 1315 0 1 –32 14 1360 1400 1430 –3 2 –46 15 1440 1500 1545 –6 3 –64 16 1600 1600 1600 4 0 –75 17 1680 1700 1715 1 1 –50 Notes 4 and 5 18 1760 1800 1830 –2 2 –34 Note 3 19 1840 1900 1945 –5 3 –68 Note 3 20 2000 2000 2000 5 0 –77 21 2080 2100 2115 2 1 –74 22 2160 2200 2230 –1 2 –67 23 2240 2300 2345 –4 3 –59 24 2400 2400 2400 6 0 –75 25 2480 2500 2515 3 1 –76 26 2560 2600 2630 0 2 –70 NOTES: 1. Desired Tx output frequency LO–IF corresponding to EGSM Tx band in Table 5. 2. (LO+IF)–(LO–IF) = 2 * IF 3. See Rx bands in Table 5. 4. LO+IF = mixer image frequency 5. See Tx bands in Table 5. 1997 May 22 15 min dBc typ dBc max dBc IF LO 2LO Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 Table 7. Measured Tx Output Noise Floor dBc/Hz Freq ency MHz Frequency MIN TYP < 860 –135 860 to 880 –134 880.2 to 890 –133 EGSM TX extension 890 to 915 –133 GSM TX 915 to 925 –133 925.2 to 935 –134 EGSM RX extension GSM RX 935 to 960 –135 960 to 1000 –135 1000 to 1710 –135 1710 to 1785 –146 1785 to 1805 –145 1805 to 1880 –144 1880 to 12750 –147 Adjacent Channel –130 1997 May 22 REMARKS MAX 16 DCS1800 TX DCS1800 RX Philips Semiconductors Product specification Low voltage GSM front-end transceiver 40 35 3V 3.5 Icc (mA) 5 4.5 4 Icc (mA) SA1620 4V 5V 3 30 3V 4V 25 5V 20 2.5 15 2 -40° 25° Temp (°C) 85° -40° 25° Temp (°C) SR01334 SR01333 Figure 8. Receive ICC vs. Temp Figure 5. LNA1_ICC vs. Temp 5 10 9 5V 4 3V 3.5 8 4V Icc (mA) Icc (mA) 4.5 5V 3 2.5 4V 7 3V 6 5 2 -40° 25° Temp (°C) 4 85° -40° 25° Temp (°C) SR01339 70 5V 4V 60 Icc (mA) Icc (mA) 65 3V 55 50 45 -40° 25° Temp (°C) 85° 28 26 24 22 20 18 16 14 12 10 3V 4V 5V -40° 25° Temp (°C) SR01344 Figure 10. Calibrate_ICC vs. Temp Figure 7. Transmit_ICC vs. Temp 1997 May 22 85° SR01338 Figure 9. Standby_ICC vs. Temp Figure 6. LNA_2 ICC vs. Temp 40 85° 17 85° SR01337 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 -20 34 -22 32 GAIN (dB) GAIN (dB) -24 30 3V 28 4V 26 5V -26 -28 24 -32 22 -34 -36 20 -40° 25° Temp (°C) 3V -30 85° 4V 5V -40° Figure 11. Receive_Gain Mode1 vs. Temp 13 IP3 (dBm) GAIN (dB) 3V 11 4V 9 5V 7 5 25° Temp (°C) 85° Figure 12. Receive_Gain_Mode2 vs. Temp GAIN (dB) -1 -2 5V -3 4V -5 -6 -40° 25° Temp (°C) 85° SR01341 Figure 13. Receive_Gain_Mode3 vs. Temp 1997 May 22 5V 4V 3V 25° Temp (°C) Figure 15. Receive IIP3 vs. Temp 0 3V -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -40° SR01335 -4 85° SR01336 Figure 14. Receive_Gain_Mode4 vs. Temp 15 -40° 25° Temp (°C) SR01342 18 85° SR01343 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 2.0 10.80 3.0V 3.0V NOISE FIGURE (dB) 5.0V 2.7V 1.8 10.40 NOISE FIGURE (dB) 1.9 5.5V 2.7V 10.00 5.0V 5.5V 9.60 1.7 1.6 –40 0 25 9.20 –40 85 0 25 85 TEMPERATURE (°C) TEMPERATURE (°C) SR00140 SR00134 Figure 16. Receive LNA1 Noise Figure Figure 18. Receive Mixer Noise Figure 10.00 2.50 2.30 9.00 5.5V POWER (dBm) 5.0V 2.10 NOISE FIGURE (dB) 3.0V 2.7V 1.90 5.5V 8.00 3.0V 5.0V 2.7V 7.00 1.70 1.50 –40 0 25 6.00 –40 85 0 TEMPERATURE (°C) 25 TEMPERATURE (°C) SR00137 85 SR00149 Figure 17. Receive LNA2 Noise Figure Figure 19. Transmit Power @ -25dBm 12 POWER (dBm) 11 5V 10 4V 9 3V 8 7 6 5 4 -40° 25° Temp (°C) Figure 20. Transmit_Power @ –20 dBm Input 1997 May 22 19 85° SR01345 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 3.02 9.50 3.01 –40 0 5.5V 5.0V 3.00 8.50 Vreg (Volts) POWER (dBm) 9.00 2.7V 8.00 3.0V 2.99 25 2.98 7.50 7.00 –40 85 2.97 0 25 TEMPERATURE (°C) 85 0 3 15 18 21 9 12 FORCED CURRENT (mA) 6 24 27 SR00150 30 SR00153 Figure 21. Transmit Power @ -15dBm Figure 24. Regulator 2 Load Regulation (VBATT = 3.5V) 3.01 –40 9.00 3.00 5.5V 0 2.98 5.0V 25 Vreg (Volts) POWER (dBm) 2.99 3.0V 8.50 8.00 2.7V 2.97 85 2.96 2.95 7.50 2.94 7.00 –25.00 –20.00 INPUT POWER (dBm) 2.93 3.3 –15.00 3.5 4.5 5.5 6.5 7.5 FORCED CURRENT (mA) SR00151 SR00154 Figure 22. Transmit Power @ 25°C Figure 25. Regulator 1 Line Regulation @ 100mA Load 3.01 –40 –40 3.00 0 25 2.98 2.99 Vreg (Volts) Vreg (Volts) 0 85 25 2.98 85 2.97 2.93 0 10 20 30 40 50 60 70 80 90 2.96 3.3 100 FORCED CURRENT (mA) 4.5 5.5 FORCED CURRENT (mA) SR00152 Figure 23. Regulator 1 Load Regulation (VBATT = 3.5V) 1997 May 22 3.5 6.5 7.5 SR00155 Figure 26. Regulator 2 Line Regulation @ 30mA Load 20 Philips Semiconductors Product specification Low voltage GSM front-end transceiver 100 90 910 1000 820 510 430 360 130 330 20 R546 (Ω) 300 910 1000 820 750 620 560 510 430 360 330 300 270 240 220 180 30 150 40 -4 130 -2 270 50 240 0 60 220 2 180 4 Temp = 25°C 70 150 Temp = 25°C 6 VCC = 3V 80 CURRENT (mA) 8 750 VCC = 3V 620 10 560 12 TRANSMITTER POWER (dBm) SA1620 R546 (Ω) SR00156 SR00157 Figure 27. Transmit Output Power vs R(546) @ VCC = 3V 1997 May 22 Figure 28. Transmit Mode Current vs R(546) @ VCC = 3V 21 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 PIN FUNCTIONS PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT 1 1 2 VCC IN2 12 3.0 12 VCCBM 3.0 13 GND 0.0 2 0.8 POnRx 3 GNDL2 0.0 4 GNDL2a 0.0 5 OUT2 5 2.2 B 6 — 6 CMOS INPUT — 14 14 CMOS INPUT 15 GND 0.0 16 Rxif 3.0 17 RxifX 3.0 18 GND 0.0 19 Txif 2.2 + 16 17 + 19 A 7 — 7 CMOS INPUT + 20 TxifX 2.2 21 GND 0.0 22 VCCTx 3.0 23 GND 0.0 24 VCCTx 3.0 25 GND 0.0 26 CMOS INPUT 20 22 8 INM 8 0.4 24 9 10 INMX COMP2 9 0.4 2.2 10 or 11 COMP1 CON2 11 — 26 + 2.2 SR00162 Figure 29. Pin Functions 1997 May 22 22 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 PIN FUNCTIONS (continued) PIN PIN DC V No. MNEMONIC 27 LOin PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT 27 28 LOinX — POnBuf 2.2 37 CMOS INPUT 38 CMOS INPUT 39 GndTx 28 EQUIVALENT CIRCUIT 37 + 2.2 PDTx CON1 29 — 38 + — 29 CMOS INPUT + 0.0 40 30 GndReg1 0.0 40 TxOx 3.0 41 TxO 3.0 42 GndTx 0.0 43 RETx 0.4 41 VBATT — 31 VReg2 3.0 + 31 GndReg2 32 32 VRegF2 VBATT 43 — 3.0 + – + GndReg2 VBATT 44 IN1 0.8 45 GndL1 0.0 46 GndTx 0.0 47 OUT1 2.2 48 VCCL1 3.0 44 — 33 VReg1 3.0 + 33 GndReg1 34 GndReg1 0.0 POn 35 45 — 35 CMOS INPUT + 47 36 48 — 36 VBATT 3.0 + SR00163 Figure 29. Pin Functions (continued) 1997 May 22 23 Philips Semiconductors Product specification Low voltage GSM front-end transceiver LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm 1997 May 22 24 SA1620 SOT313-2 Philips Semiconductors Product specification Low voltage GSM front-end transceiver NOTES 1997 May 22 25 SA1620 Philips Semiconductors Product specification Low voltage GSM front-end transceiver SA1620 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1997 May 22 26